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2ac07f75 DL |
1 | /* |
2 | * Copyright (C) 2016 David Lechner <david@lechnology.com> | |
3 | * | |
4 | * Based on da850evm.h | |
5 | * | |
6 | * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ | |
7 | * | |
8 | * Based on davinci_dvevm.h. Original Copyrights follow: | |
9 | * | |
10 | * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> | |
11 | * | |
12 | * SPDX-License-Identifier: GPL-2.0+ | |
13 | */ | |
14 | ||
15 | #ifndef __CONFIG_H | |
16 | #define __CONFIG_H | |
17 | ||
18 | /* | |
19 | * SoC Configuration | |
20 | */ | |
2ac07f75 DL |
21 | #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH |
22 | #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) | |
23 | #define CONFIG_SYS_OSCIN_FREQ 24000000 | |
24 | #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE | |
25 | #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) | |
2ac07f75 | 26 | |
2ac07f75 DL |
27 | /* |
28 | * Memory Info | |
29 | */ | |
30 | #define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ | |
31 | #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ | |
32 | #define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */ | |
33 | #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ | |
34 | ||
35 | /* memtest start addr */ | |
36 | #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) | |
37 | ||
38 | /* memtest will be run on 16MB */ | |
39 | #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024) | |
40 | ||
41 | #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ | |
42 | ||
43 | #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ | |
44 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ | |
45 | DAVINCI_SYSCFG_SUSPSRC_SPI0 | \ | |
46 | DAVINCI_SYSCFG_SUSPSRC_UART1 | \ | |
47 | DAVINCI_SYSCFG_SUSPSRC_EMAC | \ | |
48 | DAVINCI_SYSCFG_SUSPSRC_I2C) | |
49 | ||
50 | /* | |
51 | * PLL configuration | |
52 | */ | |
2ac07f75 DL |
53 | |
54 | #define CONFIG_SYS_DA850_PLL0_PLLM 24 | |
55 | #define CONFIG_SYS_DA850_PLL1_PLLM 21 | |
56 | ||
57 | /* | |
58 | * DDR2 memory configuration | |
59 | */ | |
60 | #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ | |
61 | DV_DDR_PHY_EXT_STRBEN | \ | |
62 | (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT)) | |
63 | ||
64 | #define CONFIG_SYS_DA850_DDR2_SDBCR ( \ | |
65 | (1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \ | |
66 | (1 << DV_DDR_SDCR_DDREN_SHIFT) | \ | |
67 | (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \ | |
68 | (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \ | |
69 | (0x3 << DV_DDR_SDCR_CL_SHIFT) | \ | |
70 | (0x2 << DV_DDR_SDCR_IBANK_SHIFT) | \ | |
71 | (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT)) | |
72 | ||
73 | /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */ | |
74 | #define CONFIG_SYS_DA850_DDR2_SDBCR2 0 | |
75 | ||
76 | #define CONFIG_SYS_DA850_DDR2_SDTIMR ( \ | |
77 | (14 << DV_DDR_SDTMR1_RFC_SHIFT) | \ | |
78 | (2 << DV_DDR_SDTMR1_RP_SHIFT) | \ | |
79 | (2 << DV_DDR_SDTMR1_RCD_SHIFT) | \ | |
80 | (1 << DV_DDR_SDTMR1_WR_SHIFT) | \ | |
81 | (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \ | |
82 | (8 << DV_DDR_SDTMR1_RC_SHIFT) | \ | |
83 | (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \ | |
84 | (0 << DV_DDR_SDTMR1_WTR_SHIFT)) | |
85 | ||
86 | #define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \ | |
87 | (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ | |
88 | (0 << DV_DDR_SDTMR2_XP_SHIFT) | \ | |
89 | (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ | |
90 | (17 << DV_DDR_SDTMR2_XSNR_SHIFT) | \ | |
91 | (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \ | |
92 | (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \ | |
93 | (0 << DV_DDR_SDTMR2_CKE_SHIFT)) | |
94 | ||
95 | #define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000494 | |
96 | #define CONFIG_SYS_DA850_DDR2_PBBPR 0x30 | |
97 | ||
98 | /* | |
99 | * Serial Driver info | |
100 | */ | |
101 | #define CONFIG_SYS_NS16550_SERIAL | |
102 | #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ | |
103 | #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART1_BASE /* Base address of UART1 */ | |
104 | #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) | |
105 | #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ | |
2ac07f75 DL |
106 | |
107 | #define CONFIG_SPI | |
2ac07f75 DL |
108 | #define CONFIG_SYS_SPI_BASE DAVINCI_SPI0_BASE |
109 | #define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI0_CLKID) | |
110 | #define CONFIG_SF_DEFAULT_SPEED 50000000 | |
111 | #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED | |
112 | ||
113 | /* | |
114 | * I2C Configuration | |
115 | */ | |
116 | #define CONFIG_SYS_I2C | |
117 | #define CONFIG_SYS_I2C_DAVINCI | |
118 | #define CONFIG_SYS_DAVINCI_I2C_SPEED 400000 | |
119 | #define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ | |
120 | ||
121 | /* | |
122 | * U-Boot general configuration | |
123 | */ | |
2ac07f75 DL |
124 | #define CONFIG_BOOTFILE "uImage" /* Boot file name */ |
125 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
2ac07f75 DL |
126 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ |
127 | #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) | |
2ac07f75 | 128 | #define CONFIG_MX_CYCLIC |
2ac07f75 DL |
129 | |
130 | /* | |
131 | * Linux Information | |
132 | */ | |
133 | #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) | |
134 | #define CONFIG_HWCONFIG /* enable hwconfig */ | |
135 | #define CONFIG_CMDLINE_TAG | |
136 | #define CONFIG_REVISION_TAG | |
137 | #define CONFIG_SERIAL_TAG | |
138 | #define CONFIG_SETUP_MEMORY_TAGS | |
139 | #define CONFIG_SETUP_INITRD_TAG | |
2ac07f75 DL |
140 | #define CONFIG_BOOTCOMMAND \ |
141 | "if mmc rescan; then " \ | |
142 | "if run loadbootscr; then " \ | |
143 | "run bootscript; " \ | |
144 | "else " \ | |
145 | "if run loadimage; then " \ | |
146 | "run mmcargs; " \ | |
147 | "run mmcboot; " \ | |
148 | "else " \ | |
149 | "run flashargs; " \ | |
150 | "run flashboot; " \ | |
151 | "fi; " \ | |
152 | "fi; " \ | |
153 | "else " \ | |
154 | "run flashargs; " \ | |
155 | "run flashboot; " \ | |
156 | "fi" | |
157 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
158 | "hostname=EV3\0" \ | |
159 | "memsize=64M\0" \ | |
160 | "filesyssize=10M\0" \ | |
161 | "verify=n\0" \ | |
162 | "console=ttyS1,115200n8\0" \ | |
163 | "bootscraddr=0xC0600000\0" \ | |
164 | "loadaddr=0xC0007FC0\0" \ | |
165 | "filesysaddr=0xC1180000\0" \ | |
166 | "fwupdateboot=mw 0xFFFF1FFC 0x5555AAAA; reset\0" \ | |
167 | "mmcargs=setenv bootargs mem=${memsize} console=${console} root=/dev/mmcblk0p2 rw rootwait lpj=747520\0" \ | |
168 | "mmcboot=bootm ${loadaddr}\0" \ | |
169 | "flashargs=setenv bootargs mem=${memsize} initrd=${filesysaddr},${filesyssize} root=/dev/ram0 rw rootfstype=squashfs console=${console} lpj=747520\0" \ | |
170 | "flashboot=sf probe 0; sf read ${loadaddr} 0x50000 0x300000; sf read ${filesysaddr} 0x350000 0x960000; bootm ${loadaddr}\0" \ | |
171 | "loadimage=fatload mmc 0 ${loadaddr} uImage\0" \ | |
172 | "loadbootscr=fatload mmc 0 ${bootscraddr} boot.scr\0" \ | |
173 | "bootscript=source ${bootscraddr}\0" \ | |
174 | ||
2ac07f75 DL |
175 | #ifdef CONFIG_CMD_BDI |
176 | #define CONFIG_CLOCKS | |
177 | #endif | |
178 | ||
2ac07f75 DL |
179 | #define CONFIG_ENV_SIZE (16 << 10) |
180 | ||
2ac07f75 DL |
181 | /* additions for new relocation code, must added to all boards */ |
182 | #define CONFIG_SYS_SDRAM_BASE 0xc0000000 | |
183 | ||
184 | #define CONFIG_SYS_INIT_SP_ADDR 0x80010000 | |
185 | ||
89f5eaa1 SG |
186 | #include <asm/arch/hardware.h> |
187 | ||
2ac07f75 | 188 | #endif /* __CONFIG_H */ |