[people/ms/u-boot.git] / include / configs / ls1012a_common.h

/*
 * Copyright 2016 Freescale Semiconductor
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __LS1012A_COMMON_H
#define __LS1012A_COMMON_H

#define CONFIG_FSL_LAYERSCAPE
#define CONFIG_GICV2

#include <asm/arch/config.h>
#include <asm/arch/stream_id_lsch2.h>

#define CONFIG_SUPPORT_RAW_INITRD

#define CONFIG_DISPLAY_BOARDINFO_LATE

#define CONFIG_SYS_TEXT_BASE		0x40100000

#define CONFIG_SYS_CLK_FREQ		125000000

#define CONFIG_SKIP_LOWLEVEL_INIT

#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)

#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000
#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY	0
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_DDR_BLOCK2_BASE     0x880000000ULL

/* Generic Timer Definitions */
#define COUNTER_FREQUENCY		25000000	/* 25MHz */

/* CSU */
#define CONFIG_LAYERSCAPE_NS_ACCESS

/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128 * 1024)

/*SPI device */
#ifdef CONFIG_QSPI_BOOT
#define CONFIG_SYS_QE_FW_IN_SPIFLASH
#define CONFIG_SYS_FMAN_FW_ADDR		0x400d0000
#define CONFIG_ENV_SPI_BUS		0
#define CONFIG_ENV_SPI_CS		0
#define CONFIG_ENV_SPI_MAX_HZ		1000000
#define CONFIG_ENV_SPI_MODE		0x03
#define CONFIG_SPI_FLASH_SPANSION
#define CONFIG_FSL_SPI_INTERFACE
#define CONFIG_SF_DATAFLASH

#define CONFIG_FSL_QSPI
#define QSPI0_AMBA_BASE		0x40000000
#define CONFIG_SPI_FLASH_SPANSION

#define FSL_QSPI_FLASH_SIZE		SZ_64M
#define FSL_QSPI_FLASH_NUM		2

/*
 * Environment
 */
#define CONFIG_ENV_OVERWRITE

#define CONFIG_ENV_SIZE			0x40000          /* 256KB */
#define CONFIG_ENV_OFFSET		0x200000        /* 2MB */
#define CONFIG_ENV_SECT_SIZE		0x40000
#endif

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */

#define CONFIG_CONS_INDEX       1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE     1
#define CONFIG_SYS_NS16550_CLK          (get_serial_clock())

#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

#define CONFIG_SYS_HZ			1000

#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE		128

/* Initial environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"verify=no\0"				\
	"loadaddr=0x80100000\0"			\
	"kernel_addr=0x100000\0"		\
	"fdt_high=0xffffffffffffffff\0"		\
	"initrd_high=0xffffffffffffffff\0"	\
	"kernel_start=0xa00000\0"		\
	"kernel_load=0xa0000000\0"		\
	"kernel_size=0x2800000\0"		\

#define CONFIG_BOOTCOMMAND		"sf probe 0:0; sf read $kernel_load "\
					"$kernel_start $kernel_size && "\
					"bootm $kernel_load"

/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
#define CONFIG_SYS_LONGHELP
#define CONFIG_CMDLINE_EDITING		1
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_MAXARGS		64	/* max command args */

#define CONFIG_PANIC_HANG
#define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */

#include <asm/arch/soc.h>

#endif /* __LS1012A_COMMON_H */
Commit	Line	Data
9d044fcb PK	1	/*
	2	* Copyright 2016 Freescale Semiconductor
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#ifndef __LS1012A_COMMON_H
	8	#define __LS1012A_COMMON_H
	9
	10	#define CONFIG_FSL_LAYERSCAPE
9d044fcb PK	11	#define CONFIG_GICV2
9d044fcb PK	12
9d044fcb	13	#include <asm/arch/config.h>
9f076dbe	14	#include <asm/arch/stream_id_lsch2.h>
9d044fcb PK	15
	16	#define CONFIG_SUPPORT_RAW_INITRD
	17
	18	#define CONFIG_DISPLAY_BOARDINFO_LATE
	19
	20	#define CONFIG_SYS_TEXT_BASE 0x40100000
	21
904110c7	22	#define CONFIG_SYS_CLK_FREQ 125000000
9d044fcb PK	23
9d044fcb PK	24	#define CONFIG_SKIP_LOWLEVEL_INIT
9d044fcb PK	25
	26	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
	27	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
	28
	29	#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
	30	#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
	31	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
7d559604	32	#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
9d044fcb PK	33
9d044fcb PK	34	/* Generic Timer Definitions */
b584510f	35	#define COUNTER_FREQUENCY 25000000 /* 25MHz */
9d044fcb PK	36
	37	/* CSU */
	38	#define CONFIG_LAYERSCAPE_NS_ACCESS
	39
	40	/* Size of malloc() pool */
	41	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
	42
	43	/SPI device /
	44	#ifdef CONFIG_QSPI_BOOT
	45	#define CONFIG_SYS_QE_FW_IN_SPIFLASH
	46	#define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000
	47	#define CONFIG_ENV_SPI_BUS 0
	48	#define CONFIG_ENV_SPI_CS 0
	49	#define CONFIG_ENV_SPI_MAX_HZ 1000000
	50	#define CONFIG_ENV_SPI_MODE 0x03
	51	#define CONFIG_SPI_FLASH_SPANSION
	52	#define CONFIG_FSL_SPI_INTERFACE
	53	#define CONFIG_SF_DATAFLASH
	54
	55	#define CONFIG_FSL_QSPI
	56	#define QSPI0_AMBA_BASE 0x40000000
	57	#define CONFIG_SPI_FLASH_SPANSION
9d044fcb	58
5e3f763a	59	#define FSL_QSPI_FLASH_SIZE SZ_64M
9d044fcb PK	60	#define FSL_QSPI_FLASH_NUM 2
	61
	62	/*
	63	* Environment
	64	*/
	65	#define CONFIG_ENV_OVERWRITE
	66
9d044fcb PK	67	#define CONFIG_ENV_SIZE 0x40000 /* 256KB */
	68	#define CONFIG_ENV_OFFSET 0x200000 /* 2MB */
	69	#define CONFIG_ENV_SECT_SIZE 0x40000
	70	#endif
	71
	72	/* I2C */
	73	#define CONFIG_SYS_I2C
	74	#define CONFIG_SYS_I2C_MXC
	75	#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
	76	#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
	77
	78	#define CONFIG_CONS_INDEX 1
	79	#define CONFIG_SYS_NS16550_SERIAL
	80	#define CONFIG_SYS_NS16550_REG_SIZE 1
904110c7	81	#define CONFIG_SYS_NS16550_CLK (get_serial_clock())
9d044fcb	82
9d044fcb PK	83	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
9d044fcb PK	84
9d044fcb PK	85	#define CONFIG_SYS_HZ 1000
	86
	87	#define CONFIG_HWCONFIG
	88	#define HWCONFIG_BUFFER_SIZE 128
	89
9d044fcb PK	90	/* Initial environment variables */
9d044fcb PK	91	#define CONFIG_EXTRA_ENV_SETTINGS \
9d044fcb	92	"verify=no\0" \
9d044fcb PK	93	"loadaddr=0x80100000\0" \
9d044fcb PK	94	"kernel_addr=0x100000\0" \
9d044fcb PK	95	"fdt_high=0xffffffffffffffff\0" \
	96	"initrd_high=0xffffffffffffffff\0" \
	97	"kernel_start=0xa00000\0" \
	98	"kernel_load=0xa0000000\0" \
	99	"kernel_size=0x2800000\0" \
9d044fcb	100
9d044fcb PK	101	#define CONFIG_BOOTCOMMAND "sf probe 0:0; sf read $kernel_load "\
	102	"$kernel_start $kernel_size && "\
	103	"bootm $kernel_load"
9d044fcb PK	104
	105	/* Monitor Command Prompt */
	106	#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
9d044fcb PK	107	#define CONFIG_SYS_LONGHELP
	108	#define CONFIG_CMDLINE_EDITING 1
	109	#define CONFIG_AUTO_COMPLETE
	110	#define CONFIG_SYS_MAXARGS 64 /* max command args */
	111
	112	#define CONFIG_PANIC_HANG
	113	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
	114
457e51cf SG	115	#include <asm/arch/soc.h>
457e51cf SG	116
9d044fcb	117	#endif /* __LS1012A_COMMON_H */