[people/ms/u-boot.git] / include / configs / ls1012a_common.h

/*
 * Copyright 2016 Freescale Semiconductor
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __LS1012A_COMMON_H
#define __LS1012A_COMMON_H

#define CONFIG_FSL_LAYERSCAPE
#define CONFIG_GICV2

#include <asm/arch/config.h>
#define CONFIG_SYS_NO_FLASH

#define CONFIG_SUPPORT_RAW_INITRD

#define CONFIG_DISPLAY_BOARDINFO_LATE

#define CONFIG_SYS_TEXT_BASE		0x40100000

#define CONFIG_SYS_FSL_CLK
#define CONFIG_SYS_CLK_FREQ		100000000
#define CONFIG_DDR_CLK_FREQ		125000000

#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_BOARD_EARLY_INIT_F	1

#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)

#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000
#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY	0
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE

/* Generic Timer Definitions */
#define COUNTER_FREQUENCY		CONFIG_SYS_CLK_FREQ/4	/* 25MHz */

/* CSU */
#define CONFIG_LAYERSCAPE_NS_ACCESS

/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128 * 1024)

/*SPI device */
#ifdef CONFIG_QSPI_BOOT
#define CONFIG_SYS_QE_FW_IN_SPIFLASH
#define CONFIG_SYS_FMAN_FW_ADDR		0x400d0000
#define CONFIG_ENV_SPI_BUS		0
#define CONFIG_ENV_SPI_CS		0
#define CONFIG_ENV_SPI_MAX_HZ		1000000
#define CONFIG_ENV_SPI_MODE		0x03
#define CONFIG_SPI_FLASH_SPANSION
#define CONFIG_FSL_SPI_INTERFACE
#define CONFIG_SF_DATAFLASH

#define CONFIG_FSL_QSPI
#define QSPI0_AMBA_BASE		0x40000000
#define CONFIG_SPI_FLASH_SPANSION
#define CONFIG_SPI_FLASH_BAR

#define FSL_QSPI_FLASH_SIZE		(1 << 24)
#define FSL_QSPI_FLASH_NUM		2

/*
 * Environment
 */
#define CONFIG_ENV_OVERWRITE

#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SIZE			0x40000          /* 256KB */
#define CONFIG_ENV_OFFSET		0x200000        /* 2MB */
#define CONFIG_ENV_SECT_SIZE		0x40000
#endif

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */

#define CONFIG_CONS_INDEX       1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE     1
#define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)

#define CONFIG_BAUDRATE			115200
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

/* Command line configuration */
#define CONFIG_CMD_ENV
#undef CONFIG_CMD_IMLS

#define CONFIG_ARCH_EARLY_INIT_R

#define CONFIG_SYS_HZ			1000

#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE		128

#define CONFIG_DISPLAY_CPUINFO

/* Initial environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"initrd_high=0xffffffff\0"		\
	"verify=no\0"				\
	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
	"loadaddr=0x80100000\0"			\
	"kernel_addr=0x100000\0"		\
	"ramdisk_addr=0x800000\0"		\
	"ramdisk_size=0x2000000\0"		\
	"fdt_high=0xffffffffffffffff\0"		\
	"initrd_high=0xffffffffffffffff\0"	\
	"kernel_start=0xa00000\0"		\
	"kernel_load=0xa0000000\0"		\
	"kernel_size=0x2800000\0"		\
	"console=ttyAMA0,38400n8\0"

#define CONFIG_BOOTARGS		"console=ttyS0,115200 root=/dev/ram0 " \
				"earlycon=uart8250,mmio,0x21c0500"
#define CONFIG_BOOTCOMMAND		"sf probe 0:0; sf read $kernel_load "\
					"$kernel_start $kernel_size && "\
					"bootm $kernel_load"

/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Boot args buffer */
#define CONFIG_SYS_LONGHELP
#define CONFIG_CMDLINE_EDITING		1
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_MAXARGS		64	/* max command args */

#define CONFIG_PANIC_HANG
#define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */

#include <asm/fsl_secure_boot.h>

#endif /* __LS1012A_COMMON_H */
Commit	Line	Data
9d044fcb PK	1	/*
	2	* Copyright 2016 Freescale Semiconductor
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#ifndef __LS1012A_COMMON_H
	8	#define __LS1012A_COMMON_H
	9
	10	#define CONFIG_FSL_LAYERSCAPE
9d044fcb PK	11	#define CONFIG_GICV2
9d044fcb PK	12
9d044fcb PK	13	#include <asm/arch/config.h>
	14	#define CONFIG_SYS_NO_FLASH
	15
	16	#define CONFIG_SUPPORT_RAW_INITRD
	17
	18	#define CONFIG_DISPLAY_BOARDINFO_LATE
	19
	20	#define CONFIG_SYS_TEXT_BASE 0x40100000
	21
	22	#define CONFIG_SYS_FSL_CLK
	23	#define CONFIG_SYS_CLK_FREQ 100000000
	24	#define CONFIG_DDR_CLK_FREQ 125000000
	25
	26	#define CONFIG_SKIP_LOWLEVEL_INIT
	27	#define CONFIG_BOARD_EARLY_INIT_F 1
	28
	29	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
	30	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
	31
	32	#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
	33	#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
	34	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
	35
	36	/* Generic Timer Definitions */
	37	#define COUNTER_FREQUENCY CONFIG_SYS_CLK_FREQ/4 /* 25MHz */
	38
	39	/* CSU */
	40	#define CONFIG_LAYERSCAPE_NS_ACCESS
	41
	42	/* Size of malloc() pool */
	43	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
	44
	45	/SPI device /
	46	#ifdef CONFIG_QSPI_BOOT
	47	#define CONFIG_SYS_QE_FW_IN_SPIFLASH
	48	#define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000
	49	#define CONFIG_ENV_SPI_BUS 0
	50	#define CONFIG_ENV_SPI_CS 0
	51	#define CONFIG_ENV_SPI_MAX_HZ 1000000
	52	#define CONFIG_ENV_SPI_MODE 0x03
	53	#define CONFIG_SPI_FLASH_SPANSION
	54	#define CONFIG_FSL_SPI_INTERFACE
	55	#define CONFIG_SF_DATAFLASH
	56
	57	#define CONFIG_FSL_QSPI
	58	#define QSPI0_AMBA_BASE 0x40000000
	59	#define CONFIG_SPI_FLASH_SPANSION
	60	#define CONFIG_SPI_FLASH_BAR
	61
	62	#define FSL_QSPI_FLASH_SIZE (1 << 24)
	63	#define FSL_QSPI_FLASH_NUM 2
	64
	65	/*
	66	* Environment
	67	*/
	68	#define CONFIG_ENV_OVERWRITE
	69
	70	#define CONFIG_ENV_IS_IN_SPI_FLASH
	71	#define CONFIG_ENV_SIZE 0x40000 /* 256KB */
	72	#define CONFIG_ENV_OFFSET 0x200000 /* 2MB */
	73	#define CONFIG_ENV_SECT_SIZE 0x40000
	74	#endif
	75
	76	/* I2C */
77	#define CONFIG_SYS_I2C
78	#define CONFIG_SYS_I2C_MXC
79	#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
80	#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
81
82	#define CONFIG_CONS_INDEX 1
83	#define CONFIG_SYS_NS16550_SERIAL
84	#define CONFIG_SYS_NS16550_REG_SIZE 1
85	#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
86
87	#define CONFIG_BAUDRATE 115200
88	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
89
90	/* Command line configuration */
91	#define CONFIG_CMD_ENV
92	#undef CONFIG_CMD_IMLS
93
94	#define CONFIG_ARCH_EARLY_INIT_R
95
96	#define CONFIG_SYS_HZ 1000
97
98	#define CONFIG_HWCONFIG
99	#define HWCONFIG_BUFFER_SIZE 128
100
101	#define CONFIG_DISPLAY_CPUINFO
102
103	/* Initial environment variables */
104	#define CONFIG_EXTRA_ENV_SETTINGS \
105	"initrd_high=0xffffffff\0" \
106	"verify=no\0" \
107	"hwconfig=fsl_ddr:bank_intlv=auto\0" \
108	"loadaddr=0x80100000\0" \
109	"kernel_addr=0x100000\0" \
110	"ramdisk_addr=0x800000\0" \
111	"ramdisk_size=0x2000000\0" \
112	"fdt_high=0xffffffffffffffff\0" \
113	"initrd_high=0xffffffffffffffff\0" \
114	"kernel_start=0xa00000\0" \
115	"kernel_load=0xa0000000\0" \
116	"kernel_size=0x2800000\0" \
117	"console=ttyAMA0,38400n8\0"
118
119	#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \
120	"earlycon=uart8250,mmio,0x21c0500"
121	#define CONFIG_BOOTCOMMAND "sf probe 0:0; sf read $kernel_load "\
122	"$kernel_start $kernel_size && "\
123	"bootm $kernel_load"
9d044fcb PK	124
	125	/* Monitor Command Prompt */
	126	#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
	127	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	128	sizeof(CONFIG_SYS_PROMPT) + 16)
	129	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
	130	#define CONFIG_SYS_LONGHELP
	131	#define CONFIG_CMDLINE_EDITING 1
	132	#define CONFIG_AUTO_COMPLETE
	133	#define CONFIG_SYS_MAXARGS 64 /* max command args */
	134
	135	#define CONFIG_PANIC_HANG
	136	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
	137
	138	#include <asm/fsl_secure_boot.h>
	139
	140	#endif /* __LS1012A_COMMON_H */