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| Commit | Line | Data |
|---|---|---|
| 9d044fcb PK |
1 | /* |
| 2 | * Copyright 2016 Freescale Semiconductor, Inc. | |
| 3 | * | |
| 4 | * SPDX-License-Identifier: GPL-2.0+ | |
| 5 | */ | |
| 6 | ||
| 7 | #ifndef __LS1012AQDS_H__ | |
| 8 | #define __LS1012AQDS_H__ | |
| 9 | ||
| 10 | #include "ls1012a_common.h" | |
| 11 | ||
| b9e745bb | 12 | /* DDR */ |
| 9d044fcb PK |
13 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
| 14 | #define CONFIG_CHIP_SELECTS_PER_CTRL 1 | |
| 15 | #define CONFIG_NR_DRAM_BANKS 2 | |
| 16 | #define CONFIG_SYS_SDRAM_SIZE 0x40000000 | |
| b9e745bb SL |
17 | #define CONFIG_CMD_MEMINFO |
| 18 | #define CONFIG_CMD_MEMTEST | |
| 19 | #define CONFIG_SYS_MEMTEST_START 0x80000000 | |
| 20 | #define CONFIG_SYS_MEMTEST_END 0x9fffffff | |
| 21 | ||
| 9d044fcb PK |
22 | /* |
| 23 | * QIXIS Definitions | |
| 24 | */ | |
| 25 | #define CONFIG_FSL_QIXIS | |
| 26 | ||
| 27 | #ifdef CONFIG_FSL_QIXIS | |
| 28 | #define CONFIG_QIXIS_I2C_ACCESS | |
| 29 | #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 | |
| 30 | #define QIXIS_LBMAP_BRDCFG_REG 0x04 | |
| 31 | #define QIXIS_LBMAP_SWITCH 6 | |
| 3b4dbd37 | 32 | #define QIXIS_LBMAP_MASK 0x08 |
| 9d044fcb PK |
33 | #define QIXIS_LBMAP_SHIFT 0 |
| 34 | #define QIXIS_LBMAP_DFLTBANK 0x00 | |
| 35 | #define QIXIS_LBMAP_ALTBANK 0x08 | |
| 3b4dbd37 | 36 | #define QIXIS_RST_CTL_RESET 0x31 |
| 9d044fcb PK |
37 | #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 |
| 38 | #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 | |
| 39 | #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 | |
| 40 | #endif | |
| 41 | ||
| 42 | /* | |
| 43 | * I2C bus multiplexer | |
| 44 | */ | |
| 45 | #define I2C_MUX_PCA_ADDR_PRI 0x77 | |
| 46 | #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ | |
| 47 | #define I2C_RETIMER_ADDR 0x18 | |
| 48 | #define I2C_MUX_CH_DEFAULT 0x8 | |
| 49 | #define I2C_MUX_CH_CH7301 0xC | |
| 50 | #define I2C_MUX_CH5 0xD | |
| 51 | #define I2C_MUX_CH7 0xF | |
| 52 | ||
| 53 | #define I2C_MUX_CH_VOL_MONITOR 0xa | |
| 54 | ||
| 55 | /* | |
| 56 | * RTC configuration | |
| 57 | */ | |
| 58 | #define RTC | |
| 59 | #define CONFIG_RTC_PCF8563 1 | |
| 60 | #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ | |
| 9d044fcb PK |
61 | |
| 62 | /* EEPROM */ | |
| 63 | #define CONFIG_ID_EEPROM | |
| 9d044fcb PK |
64 | #define CONFIG_SYS_I2C_EEPROM_NXID |
| 65 | #define CONFIG_SYS_EEPROM_BUS_NUM 0 | |
| 66 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 | |
| 67 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
| 68 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
| 69 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 | |
| 70 | ||
| 71 | ||
| 72 | /* Voltage monitor on channel 2*/ | |
| 73 | #define I2C_VOL_MONITOR_ADDR 0x40 | |
| 74 | #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 | |
| 75 | #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 | |
| 76 | #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 | |
| 77 | ||
| 78 | /* DSPI */ | |
| 79 | #define CONFIG_FSL_DSPI1 | |
| 80 | #define CONFIG_DEFAULT_SPI_BUS 1 | |
| 81 | ||
| 82 | #define CONFIG_CMD_SPI | |
| 83 | #define MMAP_DSPI DSPI1_BASE_ADDR | |
| 84 | ||
| 85 | #define CONFIG_SYS_DSPI_CTAR0 1 | |
| 86 | ||
| 87 | #define CONFIG_SYS_DSPI_CTAR1 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\ | |
| 88 | DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \ | |
| 89 | DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \ | |
| 90 | DSPI_CTAR_DT(0)) | |
| 91 | #define CONFIG_SPI_FLASH_SST /* cs1 */ | |
| 92 | ||
| 93 | #define CONFIG_SYS_DSPI_CTAR2 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\ | |
| 94 | DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \ | |
| 95 | DSPI_CTAR_CSSCK(0) | DSPI_CTAR_ASC(0) | \ | |
| 96 | DSPI_CTAR_DT(0)) | |
| 97 | #define CONFIG_SPI_FLASH_STMICRO /* cs2 */ | |
| 98 | ||
| 99 | #define CONFIG_SYS_DSPI_CTAR3 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\ | |
| 100 | DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \ | |
| 101 | DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \ | |
| 102 | DSPI_CTAR_DT(0)) | |
| 103 | #define CONFIG_SPI_FLASH_EON /* cs3 */ | |
| 104 | ||
| 105 | #define CONFIG_SF_DEFAULT_SPEED 10000000 | |
| 106 | #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 | |
| 107 | #define CONFIG_SF_DEFAULT_BUS 1 | |
| 108 | #define CONFIG_SF_DEFAULT_CS 0 | |
| 109 | ||
| 110 | /* | |
| 111 | * USB | |
| 112 | */ | |
| 113 | /* EHCI Support - disbaled by default */ | |
| 114 | /*#define CONFIG_HAS_FSL_DR_USB*/ | |
| 115 | ||
| 116 | #ifdef CONFIG_HAS_FSL_DR_USB | |
| 9d044fcb PK |
117 | #define CONFIG_USB_EHCI_FSL |
| 118 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
| 119 | #endif | |
| 120 | ||
| 121 | /*XHCI Support - enabled by default*/ | |
| 9d044fcb | 122 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
| 9d044fcb PK |
123 | |
| 124 | /* MMC */ | |
| 9d044fcb PK |
125 | #ifdef CONFIG_MMC |
| 126 | #define CONFIG_FSL_ESDHC | |
| 127 | #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 | |
| 9d044fcb PK |
128 | #endif |
| 129 | ||
| 130 | /* SATA */ | |
| 131 | #define CONFIG_LIBATA | |
| 9d044fcb PK |
132 | #define CONFIG_SCSI_AHCI |
| 133 | #define CONFIG_SCSI_AHCI_PLAT | |
| 9d044fcb PK |
134 | |
| 135 | #define CONFIG_SYS_SATA AHCI_BASE_ADDR | |
| 136 | ||
| 137 | #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 | |
| 138 | #define CONFIG_SYS_SCSI_MAX_LUN 1 | |
| 139 | #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ | |
| 140 | CONFIG_SYS_SCSI_MAX_LUN) | |
| 9e0bb4c1 | 141 | |
| 9d044fcb | 142 | #define CONFIG_PCIE1 /* PCIE controller 1 */ |
| 9d044fcb | 143 | |
| 9d044fcb | 144 | #define CONFIG_NET_MULTI |
| 9d044fcb | 145 | #define CONFIG_PCI_SCAN_SHOW |
| 9d044fcb PK |
146 | |
| 147 | #define CONFIG_CMD_MEMINFO | |
| 148 | #define CONFIG_CMD_MEMTEST | |
| 149 | #define CONFIG_SYS_MEMTEST_START 0x80000000 | |
| 150 | #define CONFIG_SYS_MEMTEST_END 0x9fffffff | |
| 151 | ||
| 152 | #define CONFIG_MISC_INIT_R | |
| 153 | ||
| 154 | #endif /* __LS1012AQDS_H__ */ |