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| Commit | Line | Data |
|---|---|---|
| 9d044fcb PK |
1 | /* |
| 2 | * Copyright 2016 Freescale Semiconductor, Inc. | |
| 3 | * | |
| 4 | * SPDX-License-Identifier: GPL-2.0+ | |
| 5 | */ | |
| 6 | ||
| 7 | #ifndef __LS1012AQDS_H__ | |
| 8 | #define __LS1012AQDS_H__ | |
| 9 | ||
| 10 | #include "ls1012a_common.h" | |
| 11 | ||
| b9e745bb | 12 | /* DDR */ |
| 9d044fcb PK |
13 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
| 14 | #define CONFIG_CHIP_SELECTS_PER_CTRL 1 | |
| 15 | #define CONFIG_NR_DRAM_BANKS 2 | |
| 16 | #define CONFIG_SYS_SDRAM_SIZE 0x40000000 | |
| b9e745bb SL |
17 | #define CONFIG_CMD_MEMINFO |
| 18 | #define CONFIG_CMD_MEMTEST | |
| 19 | #define CONFIG_SYS_MEMTEST_START 0x80000000 | |
| 20 | #define CONFIG_SYS_MEMTEST_END 0x9fffffff | |
| 21 | ||
| 9d044fcb PK |
22 | /* |
| 23 | * QIXIS Definitions | |
| 24 | */ | |
| 25 | #define CONFIG_FSL_QIXIS | |
| 26 | ||
| 27 | #ifdef CONFIG_FSL_QIXIS | |
| 28 | #define CONFIG_QIXIS_I2C_ACCESS | |
| 29 | #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 | |
| 30 | #define QIXIS_LBMAP_BRDCFG_REG 0x04 | |
| 31 | #define QIXIS_LBMAP_SWITCH 6 | |
| 3b4dbd37 | 32 | #define QIXIS_LBMAP_MASK 0x08 |
| 9d044fcb PK |
33 | #define QIXIS_LBMAP_SHIFT 0 |
| 34 | #define QIXIS_LBMAP_DFLTBANK 0x00 | |
| 35 | #define QIXIS_LBMAP_ALTBANK 0x08 | |
| 3b4dbd37 | 36 | #define QIXIS_RST_CTL_RESET 0x31 |
| 9d044fcb PK |
37 | #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 |
| 38 | #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 | |
| 39 | #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 | |
| 40 | #endif | |
| 41 | ||
| 42 | /* | |
| 43 | * I2C bus multiplexer | |
| 44 | */ | |
| 45 | #define I2C_MUX_PCA_ADDR_PRI 0x77 | |
| 46 | #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ | |
| 47 | #define I2C_RETIMER_ADDR 0x18 | |
| 48 | #define I2C_MUX_CH_DEFAULT 0x8 | |
| 49 | #define I2C_MUX_CH_CH7301 0xC | |
| 50 | #define I2C_MUX_CH5 0xD | |
| 51 | #define I2C_MUX_CH7 0xF | |
| 52 | ||
| 53 | #define I2C_MUX_CH_VOL_MONITOR 0xa | |
| 54 | ||
| 55 | /* | |
| 56 | * RTC configuration | |
| 57 | */ | |
| 58 | #define RTC | |
| 59 | #define CONFIG_RTC_PCF8563 1 | |
| 60 | #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ | |
| 61 | #define CONFIG_CMD_DATE | |
| 62 | ||
| 63 | /* EEPROM */ | |
| 64 | #define CONFIG_ID_EEPROM | |
| 65 | #define CONFIG_CMD_EEPROM | |
| 66 | #define CONFIG_SYS_I2C_EEPROM_NXID | |
| 67 | #define CONFIG_SYS_EEPROM_BUS_NUM 0 | |
| 68 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 | |
| 69 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
| 70 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
| 71 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 | |
| 72 | ||
| 73 | ||
| 74 | /* Voltage monitor on channel 2*/ | |
| 75 | #define I2C_VOL_MONITOR_ADDR 0x40 | |
| 76 | #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 | |
| 77 | #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 | |
| 78 | #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 | |
| 79 | ||
| 80 | /* DSPI */ | |
| 81 | #define CONFIG_FSL_DSPI1 | |
| 82 | #define CONFIG_DEFAULT_SPI_BUS 1 | |
| 83 | ||
| 84 | #define CONFIG_CMD_SPI | |
| 85 | #define MMAP_DSPI DSPI1_BASE_ADDR | |
| 86 | ||
| 87 | #define CONFIG_SYS_DSPI_CTAR0 1 | |
| 88 | ||
| 89 | #define CONFIG_SYS_DSPI_CTAR1 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\ | |
| 90 | DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \ | |
| 91 | DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \ | |
| 92 | DSPI_CTAR_DT(0)) | |
| 93 | #define CONFIG_SPI_FLASH_SST /* cs1 */ | |
| 94 | ||
| 95 | #define CONFIG_SYS_DSPI_CTAR2 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\ | |
| 96 | DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \ | |
| 97 | DSPI_CTAR_CSSCK(0) | DSPI_CTAR_ASC(0) | \ | |
| 98 | DSPI_CTAR_DT(0)) | |
| 99 | #define CONFIG_SPI_FLASH_STMICRO /* cs2 */ | |
| 100 | ||
| 101 | #define CONFIG_SYS_DSPI_CTAR3 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\ | |
| 102 | DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \ | |
| 103 | DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \ | |
| 104 | DSPI_CTAR_DT(0)) | |
| 105 | #define CONFIG_SPI_FLASH_EON /* cs3 */ | |
| 106 | ||
| 107 | #define CONFIG_SF_DEFAULT_SPEED 10000000 | |
| 108 | #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 | |
| 109 | #define CONFIG_SF_DEFAULT_BUS 1 | |
| 110 | #define CONFIG_SF_DEFAULT_CS 0 | |
| 111 | ||
| 112 | /* | |
| 113 | * USB | |
| 114 | */ | |
| 115 | /* EHCI Support - disbaled by default */ | |
| 116 | /*#define CONFIG_HAS_FSL_DR_USB*/ | |
| 117 | ||
| 118 | #ifdef CONFIG_HAS_FSL_DR_USB | |
| 119 | #define CONFIG_USB_EHCI | |
| 120 | #define CONFIG_USB_EHCI_FSL | |
| 121 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
| 122 | #endif | |
| 123 | ||
| 124 | /*XHCI Support - enabled by default*/ | |
| 125 | #define CONFIG_HAS_FSL_XHCI_USB | |
| 126 | ||
| 127 | #ifdef CONFIG_HAS_FSL_XHCI_USB | |
| 9d044fcb | 128 | #define CONFIG_USB_XHCI_FSL |
| 9d044fcb PK |
129 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
| 130 | #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 | |
| 9d044fcb PK |
131 | #endif |
| 132 | ||
| 133 | /* MMC */ | |
| 134 | #define CONFIG_MMC | |
| 135 | #ifdef CONFIG_MMC | |
| 136 | #define CONFIG_FSL_ESDHC | |
| 137 | #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 | |
| 138 | #define CONFIG_GENERIC_MMC | |
| 139 | #define CONFIG_DOS_PARTITION | |
| 140 | #endif | |
| 141 | ||
| 142 | /* SATA */ | |
| 143 | #define CONFIG_LIBATA | |
| 144 | #define CONFIG_SCSI | |
| 145 | #define CONFIG_SCSI_AHCI | |
| 146 | #define CONFIG_SCSI_AHCI_PLAT | |
| 147 | #define CONFIG_CMD_SCSI | |
| 148 | #define CONFIG_DOS_PARTITION | |
| 149 | #define CONFIG_BOARD_LATE_INIT | |
| 150 | ||
| 151 | #define CONFIG_SYS_SATA AHCI_BASE_ADDR | |
| 152 | ||
| 153 | #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 | |
| 154 | #define CONFIG_SYS_SCSI_MAX_LUN 1 | |
| 155 | #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ | |
| 156 | CONFIG_SYS_SCSI_MAX_LUN) | |
| 9d044fcb PK |
157 | #define CONFIG_PCIE1 /* PCIE controller 1 */ |
| 158 | #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ | |
| 159 | #define FSL_PCIE_COMPAT "fsl,ls1043a-pcie" | |
| 160 | ||
| 161 | #define CONFIG_SYS_PCI_64BIT | |
| 162 | ||
| 163 | #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 | |
| 164 | #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ | |
| 165 | #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 | |
| 166 | #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ | |
| 167 | ||
| 168 | #define CONFIG_SYS_PCIE_IO_BUS 0x00000000 | |
| 169 | #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 | |
| 170 | #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ | |
| 171 | ||
| 172 | #define CONFIG_SYS_PCIE_MEM_BUS 0x08000000 | |
| 173 | #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000 | |
| 174 | #define CONFIG_SYS_PCIE_MEM_SIZE 0x80000000 /* 128M */ | |
| 175 | ||
| 176 | #define CONFIG_NET_MULTI | |
| 177 | #define CONFIG_PCI_PNP | |
| 178 | #define CONFIG_PCI_SCAN_SHOW | |
| 179 | #define CONFIG_CMD_PCI | |
| 180 | ||
| 181 | #define CONFIG_CMD_MEMINFO | |
| 182 | #define CONFIG_CMD_MEMTEST | |
| 183 | #define CONFIG_SYS_MEMTEST_START 0x80000000 | |
| 184 | #define CONFIG_SYS_MEMTEST_END 0x9fffffff | |
| 185 | ||
| 186 | #define CONFIG_MISC_INIT_R | |
| 187 | ||
| 188 | #endif /* __LS1012AQDS_H__ */ |