]>
Commit | Line | Data |
---|---|---|
20c700f8 FL |
1 | /* |
2 | * Copyright 2016 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
6 | ||
7 | #ifndef __CONFIG_H | |
8 | #define __CONFIG_H | |
9 | ||
10 | #define CONFIG_LS102XA | |
11 | ||
12 | #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR | |
13 | ||
14 | #define CONFIG_SYS_FSL_CLK | |
15 | ||
20c700f8 FL |
16 | /* |
17 | * Size of malloc() pool | |
18 | */ | |
19 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) | |
20 | ||
21 | #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR | |
22 | #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE | |
23 | ||
24 | /* XHCI Support - enabled by default */ | |
25 | #define CONFIG_HAS_FSL_XHCI_USB | |
26 | ||
27 | #ifdef CONFIG_HAS_FSL_XHCI_USB | |
28 | #define CONFIG_USB_XHCI_FSL | |
29 | #define CONFIG_USB_XHCI_DWC3 | |
30 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 | |
31 | #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 | |
32 | #endif | |
33 | ||
34 | #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB) | |
35 | #define CONFIG_USB_STORAGE | |
36 | #define CONFIG_CMD_EXT2 | |
37 | #endif | |
38 | ||
39 | /* | |
40 | * Generic Timer Definitions | |
41 | */ | |
42 | #define GENERIC_TIMER_CLK 12500000 | |
43 | ||
44 | #define CONFIG_SYS_CLK_FREQ 100000000 | |
45 | #define CONFIG_DDR_CLK_FREQ 100000000 | |
46 | ||
47 | /* | |
48 | * DDR: 800 MHz ( 1600 MT/s data rate ) | |
49 | */ | |
50 | ||
51 | #define DDR_SDRAM_CFG 0x470c0008 | |
52 | #define DDR_CS0_BNDS 0x008000bf | |
53 | #define DDR_CS0_CONFIG 0x80014302 | |
54 | #define DDR_TIMING_CFG_0 0x50550004 | |
55 | #define DDR_TIMING_CFG_1 0xbcb38c56 | |
56 | #define DDR_TIMING_CFG_2 0x0040d120 | |
57 | #define DDR_TIMING_CFG_3 0x010e1000 | |
58 | #define DDR_TIMING_CFG_4 0x00000001 | |
59 | #define DDR_TIMING_CFG_5 0x03401400 | |
60 | #define DDR_SDRAM_CFG_2 0x00401010 | |
61 | #define DDR_SDRAM_MODE 0x00061c60 | |
62 | #define DDR_SDRAM_MODE_2 0x00180000 | |
63 | #define DDR_SDRAM_INTERVAL 0x18600618 | |
64 | #define DDR_DDR_WRLVL_CNTL 0x8655f605 | |
65 | #define DDR_DDR_WRLVL_CNTL_2 0x05060607 | |
66 | #define DDR_DDR_WRLVL_CNTL_3 0x05050505 | |
67 | #define DDR_DDR_CDR1 0x80040000 | |
68 | #define DDR_DDR_CDR2 0x00000001 | |
69 | #define DDR_SDRAM_CLK_CNTL 0x02000000 | |
70 | #define DDR_DDR_ZQ_CNTL 0x89080600 | |
71 | #define DDR_CS0_CONFIG_2 0 | |
72 | #define DDR_SDRAM_CFG_MEM_EN 0x80000000 | |
73 | #define SDRAM_CFG2_D_INIT 0x00000010 | |
74 | #define DDR_CDR2_VREF_TRAIN_EN 0x00000080 | |
75 | #define SDRAM_CFG2_FRC_SR 0x80000000 | |
76 | #define SDRAM_CFG_BI 0x00000001 | |
77 | ||
78 | #ifdef CONFIG_RAMBOOT_PBL | |
79 | #define CONFIG_SYS_FSL_PBL_PBI \ | |
80 | board/freescale/ls1021aiot/ls102xa_pbi.cfg | |
81 | #endif | |
82 | ||
83 | #ifdef CONFIG_SD_BOOT | |
84 | #define CONFIG_SYS_FSL_PBL_RCW \ | |
85 | board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg | |
86 | #define CONFIG_SPL_FRAMEWORK | |
87 | #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" | |
88 | #define CONFIG_SPL_LIBCOMMON_SUPPORT | |
89 | #define CONFIG_SPL_LIBGENERIC_SUPPORT | |
90 | #define CONFIG_SPL_ENV_SUPPORT | |
91 | #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT | |
92 | #define CONFIG_SPL_I2C_SUPPORT | |
93 | #define CONFIG_SPL_WATCHDOG_SUPPORT | |
94 | #define CONFIG_SPL_SERIAL_SUPPORT | |
95 | #define CONFIG_SPL_MMC_SUPPORT | |
96 | #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 | |
20c700f8 FL |
97 | |
98 | #define CONFIG_SPL_TEXT_BASE 0x10000000 | |
99 | #define CONFIG_SPL_MAX_SIZE 0x1a000 | |
100 | #define CONFIG_SPL_STACK 0x1001d000 | |
101 | #define CONFIG_SPL_PAD_TO 0x1c000 | |
102 | #define CONFIG_SYS_TEXT_BASE 0x82000000 | |
103 | ||
104 | #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ | |
105 | CONFIG_SYS_MONITOR_LEN) | |
106 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 | |
107 | #define CONFIG_SPL_BSS_START_ADDR 0x80100000 | |
108 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 | |
109 | #define CONFIG_SYS_MONITOR_LEN 0x80000 | |
20c700f8 FL |
110 | #endif |
111 | ||
112 | #ifdef CONFIG_QSPI_BOOT | |
113 | #define CONFIG_SYS_TEXT_BASE 0x40010000 | |
114 | #endif | |
115 | ||
20c700f8 FL |
116 | #define CONFIG_NR_DRAM_BANKS 1 |
117 | ||
118 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL | |
119 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
120 | ||
121 | #define CONFIG_FSL_CAAM /* Enable CAAM */ | |
122 | ||
123 | /* | |
124 | * Serial Port | |
125 | */ | |
126 | #define CONFIG_CONS_INDEX 1 | |
127 | #define CONFIG_SYS_NS16550_SERIAL | |
128 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
129 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() | |
130 | #define CONFIG_BAUDRATE 115200 | |
131 | ||
132 | /* | |
133 | * I2C | |
134 | */ | |
135 | #define CONFIG_CMD_I2C | |
136 | #define CONFIG_SYS_I2C | |
137 | #define CONFIG_SYS_I2C_MXC | |
138 | #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ | |
139 | #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ | |
140 | #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ | |
141 | ||
142 | /* EEPROM */ | |
143 | #define CONFIG_ID_EEPROM | |
144 | #define CONFIG_SYS_I2C_EEPROM_NXID | |
145 | #define CONFIG_SYS_EEPROM_BUS_NUM 0 | |
146 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x51 | |
147 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
148 | ||
149 | /* | |
150 | * MMC | |
151 | */ | |
20c700f8 FL |
152 | #define CONFIG_CMD_MMC |
153 | #define CONFIG_FSL_ESDHC | |
20c700f8 FL |
154 | |
155 | /* SATA */ | |
20c700f8 FL |
156 | #define CONFIG_CMD_SCSI |
157 | #define CONFIG_LIBATA | |
158 | #define CONFIG_SCSI_AHCI | |
159 | #define CONFIG_SCSI_AHCI_PLAT | |
160 | #ifndef PCI_DEVICE_ID_FREESCALE_AHCI | |
161 | #define PCI_DEVICE_ID_FREESCALE_AHCI 0x0440 | |
162 | #endif | |
163 | #define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_FREESCALE, \ | |
164 | PCI_DEVICE_ID_FREESCALE_AHCI} | |
165 | ||
166 | #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 | |
167 | #define CONFIG_SYS_SCSI_MAX_LUN 1 | |
168 | #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ | |
169 | CONFIG_SYS_SCSI_MAX_LUN) | |
170 | ||
171 | #define CONFIG_CMD_FAT | |
20c700f8 FL |
172 | |
173 | /* SPI */ | |
174 | #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) | |
175 | #define CONFIG_SPI_FLASH_SPANSION | |
176 | ||
177 | /* QSPI */ | |
178 | #define QSPI0_AMBA_BASE 0x40000000 | |
179 | #define FSL_QSPI_FLASH_SIZE (1 << 24) | |
180 | #define FSL_QSPI_FLASH_NUM 2 | |
181 | #define CONFIG_SPI_FLASH_BAR | |
182 | #define CONFIG_SPI_FLASH_SPANSION | |
183 | #endif | |
184 | ||
185 | /* DM SPI */ | |
186 | #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) | |
187 | #define CONFIG_CMD_SF | |
188 | #define CONFIG_DM_SPI_FLASH | |
189 | #endif | |
190 | ||
191 | /* | |
192 | * eTSEC | |
193 | */ | |
194 | #define CONFIG_TSEC_ENET | |
195 | ||
196 | #ifdef CONFIG_TSEC_ENET | |
197 | #define CONFIG_MII | |
198 | #define CONFIG_MII_DEFAULT_TSEC 1 | |
199 | #define CONFIG_TSEC1 1 | |
200 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
201 | #define CONFIG_TSEC2 1 | |
202 | #define CONFIG_TSEC2_NAME "eTSEC2" | |
203 | ||
204 | #define TSEC1_PHY_ADDR 1 | |
205 | #define TSEC2_PHY_ADDR 3 | |
206 | ||
207 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
208 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
209 | ||
210 | #define TSEC1_PHYIDX 0 | |
211 | #define TSEC2_PHYIDX 0 | |
212 | ||
213 | #define CONFIG_ETHPRIME "eTSEC2" | |
214 | ||
215 | #define CONFIG_PHY_GIGE | |
216 | #define CONFIG_PHYLIB | |
217 | #define CONFIG_PHY_ATHEROS | |
218 | ||
219 | #define CONFIG_HAS_ETH0 | |
220 | #define CONFIG_HAS_ETH1 | |
221 | #define CONFIG_HAS_ETH2 | |
222 | #endif | |
223 | ||
224 | /* PCIe */ | |
20c700f8 FL |
225 | #define CONFIG_PCIE1 /* PCIE controler 1 */ |
226 | #define CONFIG_PCIE2 /* PCIE controler 2 */ | |
227 | ||
20c700f8 FL |
228 | #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" |
229 | ||
20c700f8 | 230 | #ifdef CONFIG_PCI |
20c700f8 FL |
231 | #define CONFIG_PCI_SCAN_SHOW |
232 | #define CONFIG_CMD_PCI | |
233 | #endif | |
234 | ||
235 | #define CONFIG_CMD_PING | |
236 | #define CONFIG_CMD_DHCP | |
237 | #define CONFIG_CMD_MII | |
238 | ||
239 | #define CONFIG_CMDLINE_TAG | |
240 | #define CONFIG_CMDLINE_EDITING | |
241 | ||
242 | #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT) | |
243 | #undef CONFIG_CMD_IMLS | |
244 | #endif | |
245 | ||
246 | #define CONFIG_PEN_ADDR_BIG_ENDIAN | |
247 | #define CONFIG_LAYERSCAPE_NS_ACCESS | |
248 | #define CONFIG_SMP_PEN_ADDR 0x01ee0200 | |
249 | #define CONFIG_TIMER_CLK_FREQ 12500000 | |
250 | ||
251 | #define CONFIG_HWCONFIG | |
252 | #define HWCONFIG_BUFFER_SIZE 256 | |
253 | ||
254 | #define CONFIG_FSL_DEVICE_DISABLE | |
255 | ||
256 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
257 | "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ | |
258 | "initrd_high=0xffffffff\0" \ | |
259 | "fdt_high=0xffffffff\0" | |
260 | ||
261 | /* | |
262 | * Miscellaneous configurable options | |
263 | */ | |
264 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
265 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
266 | #define CONFIG_AUTO_COMPLETE | |
267 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
268 | #define CONFIG_SYS_PBSIZE \ | |
269 | (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
270 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
271 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
272 | ||
273 | #define CONFIG_CMD_GREPENV | |
274 | #define CONFIG_CMD_MEMINFO | |
275 | ||
276 | #define CONFIG_SYS_LOAD_ADDR 0x82000000 | |
277 | ||
278 | #define CONFIG_LS102XA_STREAM_ID | |
279 | ||
280 | /* | |
281 | * Stack sizes | |
282 | * The stack sizes are set up in start.S using the settings below | |
283 | */ | |
284 | #define CONFIG_STACKSIZE (30 * 1024) | |
285 | ||
286 | #define CONFIG_SYS_INIT_SP_OFFSET \ | |
287 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
288 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
289 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) | |
290 | ||
291 | #ifdef CONFIG_SPL_BUILD | |
292 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE | |
293 | #else | |
294 | /* start of monitor */ | |
295 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE | |
296 | #endif | |
297 | ||
298 | #define CONFIG_SYS_QE_FW_ADDR 0x67f40000 | |
299 | ||
300 | /* | |
301 | * Environment | |
302 | */ | |
303 | ||
304 | #define CONFIG_ENV_OVERWRITE | |
305 | ||
306 | #if defined(CONFIG_SD_BOOT) | |
307 | #define CONFIG_ENV_OFFSET 0x100000 | |
308 | #define CONFIG_ENV_IS_IN_MMC | |
309 | #define CONFIG_SYS_MMC_ENV_DEV 0 | |
310 | #define CONFIG_ENV_SIZE 0x2000 | |
311 | #elif defined(CONFIG_QSPI_BOOT) | |
312 | #define CONFIG_ENV_IS_IN_SPI_FLASH | |
313 | #define CONFIG_ENV_SIZE 0x2000 | |
314 | #define CONFIG_ENV_OFFSET 0x100000 | |
315 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
316 | #endif | |
317 | ||
318 | #define CONFIG_OF_BOARD_SETUP | |
319 | #define CONFIG_OF_STDOUT_VIA_ALIAS | |
320 | #define CONFIG_CMD_BOOTZ | |
321 | ||
322 | #define CONFIG_MISC_INIT_R | |
323 | ||
324 | /* Hash command with SHA acceleration supported in hardware */ | |
325 | ||
326 | #ifdef CONFIG_FSL_CAAM | |
327 | ||
328 | #define CONFIG_CMD_HASH | |
329 | ||
330 | #define CONFIG_SHA_HW_ACCEL | |
331 | ||
332 | #endif | |
333 | ||
334 | #include <asm/fsl_secure_boot.h> | |
335 | ||
336 | #endif |