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20c700f8 FL |
1 | /* |
2 | * Copyright 2016 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
6 | ||
7 | #ifndef __CONFIG_H | |
8 | #define __CONFIG_H | |
9 | ||
20c700f8 FL |
10 | #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR |
11 | ||
12 | #define CONFIG_SYS_FSL_CLK | |
13 | ||
20c700f8 FL |
14 | /* |
15 | * Size of malloc() pool | |
16 | */ | |
17 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) | |
18 | ||
19 | #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR | |
20 | #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE | |
21 | ||
20c700f8 FL |
22 | #define CONFIG_SYS_CLK_FREQ 100000000 |
23 | #define CONFIG_DDR_CLK_FREQ 100000000 | |
24 | ||
25 | /* | |
26 | * DDR: 800 MHz ( 1600 MT/s data rate ) | |
27 | */ | |
28 | ||
29 | #define DDR_SDRAM_CFG 0x470c0008 | |
30 | #define DDR_CS0_BNDS 0x008000bf | |
31 | #define DDR_CS0_CONFIG 0x80014302 | |
32 | #define DDR_TIMING_CFG_0 0x50550004 | |
33 | #define DDR_TIMING_CFG_1 0xbcb38c56 | |
34 | #define DDR_TIMING_CFG_2 0x0040d120 | |
35 | #define DDR_TIMING_CFG_3 0x010e1000 | |
36 | #define DDR_TIMING_CFG_4 0x00000001 | |
37 | #define DDR_TIMING_CFG_5 0x03401400 | |
38 | #define DDR_SDRAM_CFG_2 0x00401010 | |
39 | #define DDR_SDRAM_MODE 0x00061c60 | |
40 | #define DDR_SDRAM_MODE_2 0x00180000 | |
41 | #define DDR_SDRAM_INTERVAL 0x18600618 | |
42 | #define DDR_DDR_WRLVL_CNTL 0x8655f605 | |
43 | #define DDR_DDR_WRLVL_CNTL_2 0x05060607 | |
44 | #define DDR_DDR_WRLVL_CNTL_3 0x05050505 | |
45 | #define DDR_DDR_CDR1 0x80040000 | |
46 | #define DDR_DDR_CDR2 0x00000001 | |
47 | #define DDR_SDRAM_CLK_CNTL 0x02000000 | |
48 | #define DDR_DDR_ZQ_CNTL 0x89080600 | |
49 | #define DDR_CS0_CONFIG_2 0 | |
50 | #define DDR_SDRAM_CFG_MEM_EN 0x80000000 | |
51 | #define SDRAM_CFG2_D_INIT 0x00000010 | |
52 | #define DDR_CDR2_VREF_TRAIN_EN 0x00000080 | |
53 | #define SDRAM_CFG2_FRC_SR 0x80000000 | |
54 | #define SDRAM_CFG_BI 0x00000001 | |
55 | ||
56 | #ifdef CONFIG_RAMBOOT_PBL | |
57 | #define CONFIG_SYS_FSL_PBL_PBI \ | |
58 | board/freescale/ls1021aiot/ls102xa_pbi.cfg | |
59 | #endif | |
60 | ||
61 | #ifdef CONFIG_SD_BOOT | |
62 | #define CONFIG_SYS_FSL_PBL_RCW \ | |
63 | board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg | |
20c700f8 FL |
64 | #define CONFIG_SPL_LIBCOMMON_SUPPORT |
65 | #define CONFIG_SPL_LIBGENERIC_SUPPORT | |
66 | #define CONFIG_SPL_ENV_SUPPORT | |
67 | #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT | |
68 | #define CONFIG_SPL_I2C_SUPPORT | |
69 | #define CONFIG_SPL_WATCHDOG_SUPPORT | |
70 | #define CONFIG_SPL_SERIAL_SUPPORT | |
71 | #define CONFIG_SPL_MMC_SUPPORT | |
72 | #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 | |
20c700f8 FL |
73 | |
74 | #define CONFIG_SPL_TEXT_BASE 0x10000000 | |
75 | #define CONFIG_SPL_MAX_SIZE 0x1a000 | |
76 | #define CONFIG_SPL_STACK 0x1001d000 | |
77 | #define CONFIG_SPL_PAD_TO 0x1c000 | |
20c700f8 FL |
78 | |
79 | #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ | |
80 | CONFIG_SYS_MONITOR_LEN) | |
81 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 | |
82 | #define CONFIG_SPL_BSS_START_ADDR 0x80100000 | |
83 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 | |
84 | #define CONFIG_SYS_MONITOR_LEN 0x80000 | |
20c700f8 FL |
85 | #endif |
86 | ||
20c700f8 FL |
87 | #define CONFIG_NR_DRAM_BANKS 1 |
88 | ||
89 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL | |
90 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
91 | ||
20c700f8 FL |
92 | /* |
93 | * Serial Port | |
94 | */ | |
95 | #define CONFIG_CONS_INDEX 1 | |
96 | #define CONFIG_SYS_NS16550_SERIAL | |
97 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
98 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() | |
20c700f8 FL |
99 | |
100 | /* | |
101 | * I2C | |
102 | */ | |
103 | #define CONFIG_CMD_I2C | |
104 | #define CONFIG_SYS_I2C | |
105 | #define CONFIG_SYS_I2C_MXC | |
106 | #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ | |
107 | #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ | |
108 | #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ | |
109 | ||
110 | /* EEPROM */ | |
111 | #define CONFIG_ID_EEPROM | |
112 | #define CONFIG_SYS_I2C_EEPROM_NXID | |
113 | #define CONFIG_SYS_EEPROM_BUS_NUM 0 | |
114 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x51 | |
115 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
116 | ||
117 | /* | |
118 | * MMC | |
119 | */ | |
20c700f8 FL |
120 | #define CONFIG_CMD_MMC |
121 | #define CONFIG_FSL_ESDHC | |
20c700f8 FL |
122 | |
123 | /* SATA */ | |
20c700f8 FL |
124 | #define CONFIG_SCSI_AHCI_PLAT |
125 | #ifndef PCI_DEVICE_ID_FREESCALE_AHCI | |
126 | #define PCI_DEVICE_ID_FREESCALE_AHCI 0x0440 | |
127 | #endif | |
128 | #define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_FREESCALE, \ | |
129 | PCI_DEVICE_ID_FREESCALE_AHCI} | |
130 | ||
131 | #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 | |
132 | #define CONFIG_SYS_SCSI_MAX_LUN 1 | |
133 | #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ | |
134 | CONFIG_SYS_SCSI_MAX_LUN) | |
135 | ||
20c700f8 FL |
136 | /* SPI */ |
137 | #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) | |
138 | #define CONFIG_SPI_FLASH_SPANSION | |
139 | ||
140 | /* QSPI */ | |
141 | #define QSPI0_AMBA_BASE 0x40000000 | |
142 | #define FSL_QSPI_FLASH_SIZE (1 << 24) | |
143 | #define FSL_QSPI_FLASH_NUM 2 | |
144 | #define CONFIG_SPI_FLASH_BAR | |
145 | #define CONFIG_SPI_FLASH_SPANSION | |
146 | #endif | |
147 | ||
148 | /* DM SPI */ | |
149 | #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) | |
150 | #define CONFIG_CMD_SF | |
151 | #define CONFIG_DM_SPI_FLASH | |
152 | #endif | |
153 | ||
154 | /* | |
155 | * eTSEC | |
156 | */ | |
157 | #define CONFIG_TSEC_ENET | |
158 | ||
159 | #ifdef CONFIG_TSEC_ENET | |
160 | #define CONFIG_MII | |
161 | #define CONFIG_MII_DEFAULT_TSEC 1 | |
162 | #define CONFIG_TSEC1 1 | |
163 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
164 | #define CONFIG_TSEC2 1 | |
165 | #define CONFIG_TSEC2_NAME "eTSEC2" | |
166 | ||
167 | #define TSEC1_PHY_ADDR 1 | |
168 | #define TSEC2_PHY_ADDR 3 | |
169 | ||
170 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
171 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
172 | ||
173 | #define TSEC1_PHYIDX 0 | |
174 | #define TSEC2_PHYIDX 0 | |
175 | ||
176 | #define CONFIG_ETHPRIME "eTSEC2" | |
177 | ||
20c700f8 FL |
178 | #define CONFIG_PHY_ATHEROS |
179 | ||
180 | #define CONFIG_HAS_ETH0 | |
181 | #define CONFIG_HAS_ETH1 | |
182 | #define CONFIG_HAS_ETH2 | |
183 | #endif | |
184 | ||
185 | /* PCIe */ | |
20c700f8 FL |
186 | #define CONFIG_PCIE1 /* PCIE controler 1 */ |
187 | #define CONFIG_PCIE2 /* PCIE controler 2 */ | |
188 | ||
20c700f8 FL |
189 | #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" |
190 | ||
20c700f8 | 191 | #ifdef CONFIG_PCI |
20c700f8 | 192 | #define CONFIG_PCI_SCAN_SHOW |
20c700f8 FL |
193 | #endif |
194 | ||
20c700f8 FL |
195 | #define CONFIG_CMD_MII |
196 | ||
197 | #define CONFIG_CMDLINE_TAG | |
198 | #define CONFIG_CMDLINE_EDITING | |
199 | ||
20c700f8 FL |
200 | #define CONFIG_PEN_ADDR_BIG_ENDIAN |
201 | #define CONFIG_LAYERSCAPE_NS_ACCESS | |
202 | #define CONFIG_SMP_PEN_ADDR 0x01ee0200 | |
e4916e85 | 203 | #define COUNTER_FREQUENCY 12500000 |
20c700f8 FL |
204 | |
205 | #define CONFIG_HWCONFIG | |
206 | #define HWCONFIG_BUFFER_SIZE 256 | |
207 | ||
208 | #define CONFIG_FSL_DEVICE_DISABLE | |
209 | ||
210 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
211 | "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ | |
212 | "initrd_high=0xffffffff\0" \ | |
213 | "fdt_high=0xffffffff\0" | |
214 | ||
215 | /* | |
216 | * Miscellaneous configurable options | |
217 | */ | |
218 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
219 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
220 | #define CONFIG_AUTO_COMPLETE | |
20c700f8 FL |
221 | |
222 | #define CONFIG_CMD_GREPENV | |
223 | #define CONFIG_CMD_MEMINFO | |
224 | ||
225 | #define CONFIG_SYS_LOAD_ADDR 0x82000000 | |
226 | ||
227 | #define CONFIG_LS102XA_STREAM_ID | |
228 | ||
20c700f8 FL |
229 | #define CONFIG_SYS_INIT_SP_OFFSET \ |
230 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
231 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
232 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) | |
233 | ||
234 | #ifdef CONFIG_SPL_BUILD | |
235 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE | |
236 | #else | |
237 | /* start of monitor */ | |
238 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE | |
239 | #endif | |
240 | ||
241 | #define CONFIG_SYS_QE_FW_ADDR 0x67f40000 | |
242 | ||
243 | /* | |
244 | * Environment | |
245 | */ | |
246 | ||
247 | #define CONFIG_ENV_OVERWRITE | |
248 | ||
249 | #if defined(CONFIG_SD_BOOT) | |
250 | #define CONFIG_ENV_OFFSET 0x100000 | |
20c700f8 FL |
251 | #define CONFIG_SYS_MMC_ENV_DEV 0 |
252 | #define CONFIG_ENV_SIZE 0x2000 | |
253 | #elif defined(CONFIG_QSPI_BOOT) | |
20c700f8 FL |
254 | #define CONFIG_ENV_SIZE 0x2000 |
255 | #define CONFIG_ENV_OFFSET 0x100000 | |
256 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
257 | #endif | |
258 | ||
259 | #define CONFIG_OF_BOARD_SETUP | |
260 | #define CONFIG_OF_STDOUT_VIA_ALIAS | |
20c700f8 FL |
261 | |
262 | #define CONFIG_MISC_INIT_R | |
263 | ||
20c700f8 FL |
264 | #include <asm/fsl_secure_boot.h> |
265 | ||
266 | #endif |