[people/ms/u-boot.git] / include / configs / ls1021aqds.h

/*
 * Copyright 2014 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_ARMV7_PSCI_1_0

#define CONFIG_ARMV7_SECURE_BASE	OCRAM_BASE_S_ADDR

#define CONFIG_SYS_FSL_CLK

#define CONFIG_SKIP_LOWLEVEL_INIT

#define CONFIG_DEEP_SLEEP

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 16 * 1024 * 1024)

#define CONFIG_SYS_INIT_RAM_ADDR	OCRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE	OCRAM_SIZE

#ifndef __ASSEMBLY__
unsigned long get_board_sys_clk(void);
unsigned long get_board_ddr_clk(void);
#endif

#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_SYS_CLK_FREQ		100000000
#define CONFIG_DDR_CLK_FREQ		100000000
#define CONFIG_QIXIS_I2C_ACCESS
#else
#define CONFIG_SYS_CLK_FREQ		get_board_sys_clk()
#define CONFIG_DDR_CLK_FREQ		get_board_ddr_clk()
#endif

#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_SYS_FSL_PBL_PBI	board/freescale/ls1021aqds/ls102xa_pbi.cfg
#endif

#ifdef CONFIG_SD_BOOT
#ifdef CONFIG_SD_BOOT_QSPI
#define CONFIG_SYS_FSL_PBL_RCW	\
	board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg
#else
#define CONFIG_SYS_FSL_PBL_RCW	\
	board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg
#endif
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_LDSCRIPT	"arch/$(ARCH)/cpu/u-boot-spl.lds"

#define CONFIG_SPL_TEXT_BASE		0x10000000
#define CONFIG_SPL_MAX_SIZE		0x1a000
#define CONFIG_SPL_STACK		0x1001d000
#define CONFIG_SPL_PAD_TO		0x1c000
#define CONFIG_SYS_TEXT_BASE		0x82000000

#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SYS_TEXT_BASE + \
		CONFIG_SYS_MONITOR_LEN)
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
#define CONFIG_SPL_BSS_START_ADDR	0x80100000
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
#define CONFIG_SYS_MONITOR_LEN		0xc0000
#endif

#ifdef CONFIG_QSPI_BOOT
#define CONFIG_SYS_TEXT_BASE		0x40010000
#endif

#ifdef CONFIG_NAND_BOOT
#define CONFIG_SYS_FSL_PBL_RCW	board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_LDSCRIPT	"arch/$(ARCH)/cpu/u-boot-spl.lds"

#define CONFIG_SPL_TEXT_BASE		0x10000000
#define CONFIG_SPL_MAX_SIZE		0x1a000
#define CONFIG_SPL_STACK		0x1001d000
#define CONFIG_SPL_PAD_TO		0x1c000
#define CONFIG_SYS_TEXT_BASE		0x82000000

#define CONFIG_SYS_NAND_U_BOOT_SIZE	(400 << 10)
#define CONFIG_SYS_NAND_U_BOOT_OFFS	CONFIG_SPL_PAD_TO
#define CONFIG_SYS_NAND_PAGE_SIZE	2048
#define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE

#define CONFIG_SYS_SPL_MALLOC_START	0x80200000
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
#define CONFIG_SPL_BSS_START_ADDR	0x80100000
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
#define CONFIG_SYS_MONITOR_LEN		0x80000
#endif

#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE		0x60100000
#endif

#define CONFIG_NR_DRAM_BANKS		1

#define CONFIG_DDR_SPD
#define SPD_EEPROM_ADDRESS		0x51
#define CONFIG_SYS_SPD_BUS_NUM		0

#define CONFIG_FSL_DDR_INTERACTIVE	/* Interactive debugging */
#ifndef CONFIG_SYS_FSL_DDR4
#define CONFIG_SYS_DDR_RAW_TIMING
#endif
#define CONFIG_DIMM_SLOTS_PER_CTLR	1
#define CONFIG_CHIP_SELECTS_PER_CTRL	4

#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000UL
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE

#define CONFIG_DDR_ECC
#ifdef CONFIG_DDR_ECC
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE           0xdeadbeef
#endif

#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
	!defined(CONFIG_QSPI_BOOT)
#define CONFIG_U_QE
#endif

/*
 * IFC Definitions
 */
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_FSL_IFC
#define CONFIG_SYS_FLASH_BASE		0x60000000
#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE

#define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
#define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
				CSPR_PORT_SIZE_16 | \
				CSPR_MSEL_NOR | \
				CSPR_V)
#define CONFIG_SYS_NOR1_CSPR_EXT	(0x0)
#define CONFIG_SYS_NOR1_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
				+ 0x8000000) | \
				CSPR_PORT_SIZE_16 | \
				CSPR_MSEL_NOR | \
				CSPR_V)
#define CONFIG_SYS_NOR_AMASK		IFC_AMASK(128 * 1024 * 1024)

#define CONFIG_SYS_NOR_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
					CSOR_NOR_TRHZ_80)
#define CONFIG_SYS_NOR_FTIM0		(FTIM0_NOR_TACSE(0x4) | \
					FTIM0_NOR_TEADC(0x5) | \
					FTIM0_NOR_TEAHC(0x5))
#define CONFIG_SYS_NOR_FTIM1		(FTIM1_NOR_TACO(0x35) | \
					FTIM1_NOR_TRAD_NOR(0x1a) | \
					FTIM1_NOR_TSEQRAD_NOR(0x13))
#define CONFIG_SYS_NOR_FTIM2		(FTIM2_NOR_TCS(0x4) | \
					FTIM2_NOR_TCH(0x4) | \
					FTIM2_NOR_TWPH(0xe) | \
					FTIM2_NOR_TWP(0x1c))
#define CONFIG_SYS_NOR_FTIM3		0

#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_FLASH_SHOW_PROGRESS	45
#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
#define CONFIG_SYS_WRITE_SWAPPED_DATA

#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */

#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS, \
					CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}

/*
 * NAND Flash Definitions
 */
#define CONFIG_NAND_FSL_IFC

#define CONFIG_SYS_NAND_BASE		0x7e800000
#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE

#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)

#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
				| CSPR_PORT_SIZE_8	\
				| CSPR_MSEL_NAND	\
				| CSPR_V)
#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
				| CSOR_NAND_ECC_MODE_4	/* 4-bit ECC */ \
				| CSOR_NAND_RAL_3	/* RAL = 3 Bytes */ \
				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
				| CSOR_NAND_SPRZ_64	/* Spare size = 64 */ \
				| CSOR_NAND_PB(64))	/* 64 Pages Per Block */

#define CONFIG_SYS_NAND_ONFI_DETECTION

#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x7) | \
					FTIM0_NAND_TWP(0x18)   | \
					FTIM0_NAND_TWCHT(0x7) | \
					FTIM0_NAND_TWH(0xa))
#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
					FTIM1_NAND_TWBE(0x39)  | \
					FTIM1_NAND_TRR(0xe)   | \
					FTIM1_NAND_TRP(0x18))
#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0xf) | \
					FTIM2_NAND_TREH(0xa) | \
					FTIM2_NAND_TWHRE(0x1e))
#define CONFIG_SYS_NAND_FTIM3           0x0

#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_CMD_NAND

#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
#endif

/*
 * QIXIS Definitions
 */
#define CONFIG_FSL_QIXIS

#ifdef CONFIG_FSL_QIXIS
#define QIXIS_BASE			0x7fb00000
#define QIXIS_BASE_PHYS			QIXIS_BASE
#define CONFIG_SYS_I2C_FPGA_ADDR	0x66
#define QIXIS_LBMAP_SWITCH		6
#define QIXIS_LBMAP_MASK		0x0f
#define QIXIS_LBMAP_SHIFT		0
#define QIXIS_LBMAP_DFLTBANK		0x00
#define QIXIS_LBMAP_ALTBANK		0x04
#define QIXIS_PWR_CTL			0x21
#define QIXIS_PWR_CTL_POWEROFF		0x80
#define QIXIS_RST_CTL_RESET		0x44
#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
#define QIXIS_CTL_SYS			0x5
#define QIXIS_CTL_SYS_EVTSW_MASK	0x0c
#define QIXIS_CTL_SYS_EVTSW_IRQ		0x04
#define QIXIS_RST_FORCE_3		0x45
#define QIXIS_RST_FORCE_3_PCIESLOT1	0x80
#define QIXIS_PWR_CTL2			0x21
#define QIXIS_PWR_CTL2_PCTL		0x2

#define CONFIG_SYS_FPGA_CSPR_EXT	(0x0)
#define CONFIG_SYS_FPGA_CSPR		(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
					CSPR_PORT_SIZE_8 | \
					CSPR_MSEL_GPCM | \
					CSPR_V)
#define CONFIG_SYS_FPGA_AMASK		IFC_AMASK(64 * 1024)
#define CONFIG_SYS_FPGA_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
					CSOR_NOR_NOR_MODE_AVD_NOR | \
					CSOR_NOR_TRHZ_80)

/*
 * QIXIS Timing parameters for IFC GPCM
 */
#define CONFIG_SYS_FPGA_FTIM0		(FTIM0_GPCM_TACSE(0xe) | \
					FTIM0_GPCM_TEADC(0xe) | \
					FTIM0_GPCM_TEAHC(0xe))
#define CONFIG_SYS_FPGA_FTIM1		(FTIM1_GPCM_TACO(0xe) | \
					FTIM1_GPCM_TRAD(0x1f))
#define CONFIG_SYS_FPGA_FTIM2		(FTIM2_GPCM_TCS(0xe) | \
					FTIM2_GPCM_TCH(0xe) | \
					FTIM2_GPCM_TWP(0xf0))
#define CONFIG_SYS_FPGA_FTIM3		0x0
#endif

#if defined(CONFIG_NAND_BOOT)
#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR1_CSPR_EXT
#define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR1_CSPR
#define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR3_EXT		CONFIG_SYS_FPGA_CSPR_EXT
#define CONFIG_SYS_CSPR3		CONFIG_SYS_FPGA_CSPR
#define CONFIG_SYS_AMASK3		CONFIG_SYS_FPGA_AMASK
#define CONFIG_SYS_CSOR3		CONFIG_SYS_FPGA_CSOR
#define CONFIG_SYS_CS3_FTIM0		CONFIG_SYS_FPGA_FTIM0
#define CONFIG_SYS_CS3_FTIM1		CONFIG_SYS_FPGA_FTIM1
#define CONFIG_SYS_CS3_FTIM2		CONFIG_SYS_FPGA_FTIM2
#define CONFIG_SYS_CS3_FTIM3		CONFIG_SYS_FPGA_FTIM3
#else
#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR1_CSPR_EXT
#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR
#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR3_EXT		CONFIG_SYS_FPGA_CSPR_EXT
#define CONFIG_SYS_CSPR3		CONFIG_SYS_FPGA_CSPR
#define CONFIG_SYS_AMASK3		CONFIG_SYS_FPGA_AMASK
#define CONFIG_SYS_CSOR3		CONFIG_SYS_FPGA_CSOR
#define CONFIG_SYS_CS3_FTIM0		CONFIG_SYS_FPGA_FTIM0
#define CONFIG_SYS_CS3_FTIM1		CONFIG_SYS_FPGA_FTIM1
#define CONFIG_SYS_CS3_FTIM2		CONFIG_SYS_FPGA_FTIM2
#define CONFIG_SYS_CS3_FTIM3		CONFIG_SYS_FPGA_FTIM3
#endif

/*
 * Serial Port
 */
#ifdef CONFIG_LPUART
#define CONFIG_LPUART_32B_REG
#else
#define CONFIG_CONS_INDEX		1
#define CONFIG_SYS_NS16550_SERIAL
#ifndef CONFIG_DM_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#endif
#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
#endif

/*
 * I2C
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */

/*
 * I2C bus multiplexer
 */
#define I2C_MUX_PCA_ADDR_PRI		0x77
#define I2C_MUX_CH_DEFAULT		0x8
#define I2C_MUX_CH_CH7301		0xC

/*
 * MMC
 */
#define CONFIG_FSL_ESDHC

/* SPI */
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
/* QSPI */
#define QSPI0_AMBA_BASE			0x40000000
#define FSL_QSPI_FLASH_SIZE		(1 << 24)
#define FSL_QSPI_FLASH_NUM		2

/* DSPI */

/* DM SPI */
#if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
#define CONFIG_DM_SPI_FLASH
#define CONFIG_SPI_FLASH_DATAFLASH
#endif
#endif

/*
 * USB
 */
/* EHCI Support - disbaled by default */
/*#define CONFIG_HAS_FSL_DR_USB*/

#ifdef CONFIG_HAS_FSL_DR_USB
#define CONFIG_USB_EHCI_FSL
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#endif

/*XHCI Support - enabled by default*/
#define CONFIG_HAS_FSL_XHCI_USB

#ifdef CONFIG_HAS_FSL_XHCI_USB
#define CONFIG_USB_XHCI_FSL
#define CONFIG_USB_MAX_CONTROLLER_COUNT		1
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS	2
#endif

/*
 * Video
 */
#ifdef CONFIG_VIDEO_FSL_DCU_FB
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO

#define CONFIG_FSL_DIU_CH7301
#define CONFIG_SYS_I2C_DVI_BUS_NUM	0
#define CONFIG_SYS_I2C_QIXIS_ADDR	0x66
#define CONFIG_SYS_I2C_DVI_ADDR		0x75
#endif

/*
 * eTSEC
 */
#define CONFIG_TSEC_ENET

#ifdef CONFIG_TSEC_ENET
#define CONFIG_MII
#define CONFIG_MII_DEFAULT_TSEC		3
#define CONFIG_TSEC1			1
#define CONFIG_TSEC1_NAME		"eTSEC1"
#define CONFIG_TSEC2			1
#define CONFIG_TSEC2_NAME		"eTSEC2"
#define CONFIG_TSEC3			1
#define CONFIG_TSEC3_NAME		"eTSEC3"

#define TSEC1_PHY_ADDR			1
#define TSEC2_PHY_ADDR			2
#define TSEC3_PHY_ADDR			3

#define TSEC1_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC2_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC3_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)

#define TSEC1_PHYIDX			0
#define TSEC2_PHYIDX			0
#define TSEC3_PHYIDX			0

#define CONFIG_ETHPRIME			"eTSEC1"

#define CONFIG_PHY_GIGE
#define CONFIG_PHYLIB
#define CONFIG_PHY_REALTEK

#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#define CONFIG_HAS_ETH2

#define CONFIG_FSL_SGMII_RISER		1
#define SGMII_RISER_PHY_OFFSET		0x1b

#ifdef CONFIG_FSL_SGMII_RISER
#define CONFIG_SYS_TBIPA_VALUE		8
#endif

#endif

/* PCIe */
#define CONFIG_PCIE1		/* PCIE controller 1 */
#define CONFIG_PCIE2		/* PCIE controller 2 */

#ifdef CONFIG_PCI
#define CONFIG_PCI_SCAN_SHOW
#define CONFIG_CMD_PCI
#endif

#define CONFIG_CMDLINE_TAG
#define CONFIG_CMDLINE_EDITING

#define CONFIG_PEN_ADDR_BIG_ENDIAN
#define CONFIG_LAYERSCAPE_NS_ACCESS
#define CONFIG_SMP_PEN_ADDR		0x01ee0200
#define COUNTER_FREQUENCY		12500000

#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE		256

#define CONFIG_FSL_DEVICE_DISABLE


#define CONFIG_SYS_QE_FW_ADDR     0x600c0000

#ifdef CONFIG_LPUART
#define CONFIG_EXTRA_ENV_SETTINGS       \
	"bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
	"fdt_high=0xffffffff\0"         \
	"initrd_high=0xffffffff\0"      \
	"hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
#else
#define CONFIG_EXTRA_ENV_SETTINGS	\
	"bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
	"fdt_high=0xffffffff\0"		\
	"initrd_high=0xffffffff\0"      \
	"hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
#endif

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE		\
		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE

#define CONFIG_SYS_MEMTEST_START	0x80000000
#define CONFIG_SYS_MEMTEST_END		0x9fffffff

#define CONFIG_SYS_LOAD_ADDR		0x82000000

#define CONFIG_LS102XA_STREAM_ID

#define CONFIG_SYS_INIT_SP_OFFSET \
	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)

#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
#else
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
#endif

/*
 * Environment
 */
#define CONFIG_ENV_OVERWRITE

#if defined(CONFIG_SD_BOOT)
#define CONFIG_ENV_OFFSET		0x100000
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV		0
#define CONFIG_ENV_SIZE			0x2000
#elif defined(CONFIG_QSPI_BOOT)
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SIZE			0x2000          /* 8KB */
#define CONFIG_ENV_OFFSET		0x100000        /* 1MB */
#define CONFIG_ENV_SECT_SIZE		0x10000
#elif defined(CONFIG_NAND_BOOT)
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SIZE			0x2000
#define CONFIG_ENV_OFFSET		(10 * CONFIG_SYS_NAND_BLOCK_SIZE)
#else
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE			0x2000
#define CONFIG_ENV_SECT_SIZE		0x20000 /* 128K (one sector) */
#endif

#define CONFIG_MISC_INIT_R

/* Hash command with SHA acceleration supported in hardware */
#ifdef CONFIG_FSL_CAAM
#define CONFIG_CMD_HASH
#define CONFIG_SHA_HW_ACCEL
#endif

#include <asm/fsl_secure_boot.h>
#define CONFIG_SYS_BOOTM_LEN	(64 << 20) /* Increase max gunzip size */

#endif
Commit	Line	Data
550e3dc0 WH	1	/*
	2	* Copyright 2014 Freescale Semiconductor, Inc.
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#ifndef __CONFIG_H
	8	#define __CONFIG_H
	9
aeb901f2	10	#define CONFIG_ARMV7_PSCI_1_0
340848b1	11
3288628a HZ	12	#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
3288628a HZ	13
18fb0e3c	14	#define CONFIG_SYS_FSL_CLK
550e3dc0	15
550e3dc0	16	#define CONFIG_SKIP_LOWLEVEL_INIT
550e3dc0	17
41ba57d0	18	#define CONFIG_DEEP_SLEEP
41ba57d0	19
550e3dc0 WH	20	/*
	21	* Size of malloc() pool
	22	*/
	23	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
	24
	25	#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
	26	#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
	27
550e3dc0 WH	28	#ifndef __ASSEMBLY__
	29	unsigned long get_board_sys_clk(void);
	30	unsigned long get_board_ddr_clk(void);
	31	#endif
	32
70097027	33	#if defined(CONFIG_QSPI_BOOT) \|\| defined(CONFIG_SD_BOOT_QSPI)
d612f0ab AW	34	#define CONFIG_SYS_CLK_FREQ 100000000
	35	#define CONFIG_DDR_CLK_FREQ 100000000
	36	#define CONFIG_QIXIS_I2C_ACCESS
	37	#else
550e3dc0 WH	38	#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
550e3dc0 WH	39	#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
d612f0ab	40	#endif
550e3dc0	41
86949c2b AW	42	#ifdef CONFIG_RAMBOOT_PBL
	43	#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021aqds/ls102xa_pbi.cfg
	44	#endif
	45
	46	#ifdef CONFIG_SD_BOOT
70097027 AW	47	#ifdef CONFIG_SD_BOOT_QSPI
	48	#define CONFIG_SYS_FSL_PBL_RCW \
	49	board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg
	50	#else
	51	#define CONFIG_SYS_FSL_PBL_RCW \
	52	board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg
	53	#endif
86949c2b AW	54	#define CONFIG_SPL_FRAMEWORK
86949c2b AW	55	#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
86949c2b AW	56
	57	#define CONFIG_SPL_TEXT_BASE 0x10000000
	58	#define CONFIG_SPL_MAX_SIZE 0x1a000
	59	#define CONFIG_SPL_STACK 0x1001d000
	60	#define CONFIG_SPL_PAD_TO 0x1c000
	61	#define CONFIG_SYS_TEXT_BASE 0x82000000
	62
41ba57d0	63	#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
41ba57d0	64	CONFIG_SYS_MONITOR_LEN)
86949c2b AW	65	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
	66	#define CONFIG_SPL_BSS_START_ADDR 0x80100000
	67	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
7ee52af4	68	#define CONFIG_SYS_MONITOR_LEN 0xc0000
86949c2b AW	69	#endif
86949c2b AW	70
d612f0ab AW	71	#ifdef CONFIG_QSPI_BOOT
d612f0ab AW	72	#define CONFIG_SYS_TEXT_BASE 0x40010000
70097027 AW	73	#endif
70097027 AW	74
8ab967b6 AW	75	#ifdef CONFIG_NAND_BOOT
	76	#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
	77	#define CONFIG_SPL_FRAMEWORK
	78	#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
8ab967b6 AW	79
	80	#define CONFIG_SPL_TEXT_BASE 0x10000000
	81	#define CONFIG_SPL_MAX_SIZE 0x1a000
	82	#define CONFIG_SPL_STACK 0x1001d000
	83	#define CONFIG_SPL_PAD_TO 0x1c000
	84	#define CONFIG_SYS_TEXT_BASE 0x82000000
	85
	86	#define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10)
	87	#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
	88	#define CONFIG_SYS_NAND_PAGE_SIZE 2048
	89	#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
	90	#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
	91
	92	#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
	93	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
	94	#define CONFIG_SPL_BSS_START_ADDR 0x80100000
	95	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
	96	#define CONFIG_SYS_MONITOR_LEN 0x80000
	97	#endif
	98
550e3dc0	99	#ifndef CONFIG_SYS_TEXT_BASE
1c69a51c	100	#define CONFIG_SYS_TEXT_BASE 0x60100000
550e3dc0 WH	101	#endif
	102
	103	#define CONFIG_NR_DRAM_BANKS 1
	104
	105	#define CONFIG_DDR_SPD
	106	#define SPD_EEPROM_ADDRESS 0x51
	107	#define CONFIG_SYS_SPD_BUS_NUM 0
550e3dc0 WH	108
550e3dc0 WH	109	#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
c7eae7fc	110	#ifndef CONFIG_SYS_FSL_DDR4
c7eae7fc YS	111	#define CONFIG_SYS_DDR_RAW_TIMING
c7eae7fc YS	112	#endif
550e3dc0 WH	113	#define CONFIG_DIMM_SLOTS_PER_CTLR 1
	114	#define CONFIG_CHIP_SELECTS_PER_CTRL 4
	115
	116	#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
	117	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
	118
	119	#define CONFIG_DDR_ECC
	120	#ifdef CONFIG_DDR_ECC
	121	#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
	122	#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
	123	#endif
	124
4c59ab9c AW	125	#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
4c59ab9c AW	126	!defined(CONFIG_QSPI_BOOT)
63e75fd7 ZQ	127	#define CONFIG_U_QE
	128	#endif
	129
550e3dc0 WH	130	/*
	131	* IFC Definitions
	132	*/
70097027	133	#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
550e3dc0 WH	134	#define CONFIG_FSL_IFC
	135	#define CONFIG_SYS_FLASH_BASE 0x60000000
	136	#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
	137
	138	#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
	139	#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \| \
	140	CSPR_PORT_SIZE_16 \| \
	141	CSPR_MSEL_NOR \| \
	142	CSPR_V)
	143	#define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
	144	#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
	145	+ 0x8000000) \| \
	146	CSPR_PORT_SIZE_16 \| \
	147	CSPR_MSEL_NOR \| \
	148	CSPR_V)
	149	#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
	150
	151	#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) \| \
	152	CSOR_NOR_TRHZ_80)
	153	#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) \| \
	154	FTIM0_NOR_TEADC(0x5) \| \
	155	FTIM0_NOR_TEAHC(0x5))
	156	#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) \| \
	157	FTIM1_NOR_TRAD_NOR(0x1a) \| \
	158	FTIM1_NOR_TSEQRAD_NOR(0x13))
	159	#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) \| \
	160	FTIM2_NOR_TCH(0x4) \| \
	161	FTIM2_NOR_TWPH(0xe) \| \
	162	FTIM2_NOR_TWP(0x1c))
	163	#define CONFIG_SYS_NOR_FTIM3 0
	164
	165	#define CONFIG_FLASH_CFI_DRIVER
	166	#define CONFIG_SYS_FLASH_CFI
	167	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
	168	#define CONFIG_SYS_FLASH_QUIET_TEST
	169	#define CONFIG_FLASH_SHOW_PROGRESS 45
	170	#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
272c5265	171	#define CONFIG_SYS_WRITE_SWAPPED_DATA
550e3dc0 WH	172
	173	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
	174	#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
	175	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	176	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
	177
	178	#define CONFIG_SYS_FLASH_EMPTY_INFO
	179	#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
	180	CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
	181
	182	/*
	183	* NAND Flash Definitions
	184	*/
	185	#define CONFIG_NAND_FSL_IFC
	186
	187	#define CONFIG_SYS_NAND_BASE 0x7e800000
	188	#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
	189
	190	#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
	191
	192	#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
	193	\| CSPR_PORT_SIZE_8 \
	194	\| CSPR_MSEL_NAND \
	195	\| CSPR_V)
	196	#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
	197	#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
	198	\| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
	199	\| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
	200	\| CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
	201	\| CSOR_NAND_PGS_2K /* Page Size = 2K */ \
	202	\| CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
	203	\| CSOR_NAND_PB(64)) /* 64 Pages Per Block */
	204
	205	#define CONFIG_SYS_NAND_ONFI_DETECTION
	206
	207	#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) \| \
	208	FTIM0_NAND_TWP(0x18) \| \
	209	FTIM0_NAND_TWCHT(0x7) \| \
	210	FTIM0_NAND_TWH(0xa))
	211	#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) \| \
	212	FTIM1_NAND_TWBE(0x39) \| \
	213	FTIM1_NAND_TRR(0xe) \| \
	214	FTIM1_NAND_TRP(0x18))
	215	#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) \| \
	216	FTIM2_NAND_TREH(0xa) \| \
	217	FTIM2_NAND_TWHRE(0x1e))
	218	#define CONFIG_SYS_NAND_FTIM3 0x0
	219
	220	#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
	221	#define CONFIG_SYS_MAX_NAND_DEVICE 1
550e3dc0 WH	222	#define CONFIG_CMD_NAND
	223
	224	#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
d612f0ab	225	#endif
550e3dc0 WH	226
	227	/*
	228	* QIXIS Definitions
	229	*/
	230	#define CONFIG_FSL_QIXIS
	231
	232	#ifdef CONFIG_FSL_QIXIS
	233	#define QIXIS_BASE 0x7fb00000
	234	#define QIXIS_BASE_PHYS QIXIS_BASE
	235	#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
	236	#define QIXIS_LBMAP_SWITCH 6
	237	#define QIXIS_LBMAP_MASK 0x0f
	238	#define QIXIS_LBMAP_SHIFT 0
	239	#define QIXIS_LBMAP_DFLTBANK 0x00
	240	#define QIXIS_LBMAP_ALTBANK 0x04
aeb901f2 HZ	241	#define QIXIS_PWR_CTL 0x21
aeb901f2 HZ	242	#define QIXIS_PWR_CTL_POWEROFF 0x80
550e3dc0 WH	243	#define QIXIS_RST_CTL_RESET 0x44
	244	#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
	245	#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
	246	#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
349cfc97 HZ	247	#define QIXIS_CTL_SYS 0x5
	248	#define QIXIS_CTL_SYS_EVTSW_MASK 0x0c
	249	#define QIXIS_CTL_SYS_EVTSW_IRQ 0x04
	250	#define QIXIS_RST_FORCE_3 0x45
	251	#define QIXIS_RST_FORCE_3_PCIESLOT1 0x80
	252	#define QIXIS_PWR_CTL2 0x21
	253	#define QIXIS_PWR_CTL2_PCTL 0x2
550e3dc0 WH	254
	255	#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
	256	#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \| \
	257	CSPR_PORT_SIZE_8 \| \
	258	CSPR_MSEL_GPCM \| \
	259	CSPR_V)
	260	#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
	261	#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) \| \
	262	CSOR_NOR_NOR_MODE_AVD_NOR \| \
	263	CSOR_NOR_TRHZ_80)
	264
	265	/*
	266	* QIXIS Timing parameters for IFC GPCM
	267	*/
	268	#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) \| \
	269	FTIM0_GPCM_TEADC(0xe) \| \
	270	FTIM0_GPCM_TEAHC(0xe))
	271	#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) \| \
	272	FTIM1_GPCM_TRAD(0x1f))
	273	#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) \| \
	274	FTIM2_GPCM_TCH(0xe) \| \
	275	FTIM2_GPCM_TWP(0xf0))
	276	#define CONFIG_SYS_FPGA_FTIM3 0x0
	277	#endif
	278
8ab967b6 AW	279	#if defined(CONFIG_NAND_BOOT)
	280	#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
	281	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
	282	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
	283	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
	284	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
	285	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
	286	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
	287	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
	288	#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
	289	#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
	290	#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
	291	#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
	292	#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
	293	#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
	294	#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
	295	#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
	296	#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
	297	#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
	298	#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
	299	#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
	300	#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
	301	#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
	302	#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
	303	#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
	304	#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
	305	#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
	306	#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
	307	#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
	308	#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
	309	#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
	310	#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
	311	#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
	312	#else
550e3dc0 WH	313	#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
	314	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
	315	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
	316	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
	317	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
	318	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
	319	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
	320	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
	321	#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
	322	#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
	323	#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
	324	#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
	325	#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
	326	#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
	327	#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
	328	#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
	329	#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
	330	#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
	331	#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
	332	#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
	333	#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
	334	#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
	335	#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
	336	#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
	337	#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
	338	#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
	339	#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
	340	#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
	341	#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
	342	#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
	343	#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
	344	#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
8ab967b6	345	#endif
550e3dc0 WH	346
	347	/*
	348	* Serial Port
	349	*/
8fc2121a	350	#ifdef CONFIG_LPUART
8fc2121a AW	351	#define CONFIG_LPUART_32B_REG
8fc2121a AW	352	#else
550e3dc0	353	#define CONFIG_CONS_INDEX 1
550e3dc0	354	#define CONFIG_SYS_NS16550_SERIAL
d83b47b7	355	#ifndef CONFIG_DM_SERIAL
550e3dc0	356	#define CONFIG_SYS_NS16550_REG_SIZE 1
d83b47b7	357	#endif
550e3dc0	358	#define CONFIG_SYS_NS16550_CLK get_serial_clock()
8fc2121a	359	#endif
550e3dc0	360
550e3dc0 WH	361	/*
	362	* I2C
	363	*/
550e3dc0 WH	364	#define CONFIG_SYS_I2C
550e3dc0 WH	365	#define CONFIG_SYS_I2C_MXC
03544c66 AA	366	#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
03544c66 AA	367	#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
f8cb101e	368	#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
550e3dc0 WH	369
	370	/*
	371	* I2C bus multiplexer
	372	*/
	373	#define I2C_MUX_PCA_ADDR_PRI 0x77
	374	#define I2C_MUX_CH_DEFAULT 0x8
dd04832d	375	#define I2C_MUX_CH_CH7301 0xC
550e3dc0 WH	376
	377	/*
	378	* MMC
	379	*/
550e3dc0	380	#define CONFIG_FSL_ESDHC
550e3dc0	381
e5493d4e	382	/* SPI */
70097027	383	#if defined(CONFIG_QSPI_BOOT) \|\| defined(CONFIG_SD_BOOT_QSPI)
e5493d4e	384	/* QSPI */
d612f0ab AW	385	#define QSPI0_AMBA_BASE 0x40000000
	386	#define FSL_QSPI_FLASH_SIZE (1 << 24)
	387	#define FSL_QSPI_FLASH_NUM 2
	388
e5493d4e	389	/* DSPI */
e5493d4e HW	390
	391	/* DM SPI */
	392	#if defined(CONFIG_FSL_DSPI) \|\| defined(CONFIG_FSL_QSPI)
e5493d4e	393	#define CONFIG_DM_SPI_FLASH
6812484a	394	#define CONFIG_SPI_FLASH_DATAFLASH
e5493d4e	395	#endif
d612f0ab AW	396	#endif
d612f0ab AW	397
8776cb20 NB	398	/*
	399	* USB
	400	*/
081a1b73 RM	401	/* EHCI Support - disbaled by default */
081a1b73 RM	402	/#define CONFIG_HAS_FSL_DR_USB/
8776cb20 NB	403
8776cb20 NB	404	#ifdef CONFIG_HAS_FSL_DR_USB
081a1b73 RM	405	#define CONFIG_USB_EHCI_FSL
	406	#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
	407	#endif
8776cb20	408
081a1b73 RM	409	/XHCI Support - enabled by default/
	410	#define CONFIG_HAS_FSL_XHCI_USB
	411
	412	#ifdef CONFIG_HAS_FSL_XHCI_USB
	413	#define CONFIG_USB_XHCI_FSL
081a1b73 RM	414	#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
	415	#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
	416	#endif
	417
dd04832d XL	418	/*
	419	* Video
	420	*/
b215fb3f	421	#ifdef CONFIG_VIDEO_FSL_DCU_FB
dd04832d XL	422	#define CONFIG_VIDEO_LOGO
	423	#define CONFIG_VIDEO_BMP_LOGO
	424
	425	#define CONFIG_FSL_DIU_CH7301
	426	#define CONFIG_SYS_I2C_DVI_BUS_NUM 0
	427	#define CONFIG_SYS_I2C_QIXIS_ADDR 0x66
	428	#define CONFIG_SYS_I2C_DVI_ADDR 0x75
	429	#endif
	430
550e3dc0 WH	431	/*
	432	* eTSEC
	433	*/
	434	#define CONFIG_TSEC_ENET
	435
	436	#ifdef CONFIG_TSEC_ENET
	437	#define CONFIG_MII
	438	#define CONFIG_MII_DEFAULT_TSEC 3
	439	#define CONFIG_TSEC1 1
	440	#define CONFIG_TSEC1_NAME "eTSEC1"
	441	#define CONFIG_TSEC2 1
	442	#define CONFIG_TSEC2_NAME "eTSEC2"
	443	#define CONFIG_TSEC3 1
	444	#define CONFIG_TSEC3_NAME "eTSEC3"
	445
	446	#define TSEC1_PHY_ADDR 1
	447	#define TSEC2_PHY_ADDR 2
	448	#define TSEC3_PHY_ADDR 3
	449
	450	#define TSEC1_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	451	#define TSEC2_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	452	#define TSEC3_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	453
	454	#define TSEC1_PHYIDX 0
	455	#define TSEC2_PHYIDX 0
	456	#define TSEC3_PHYIDX 0
	457
	458	#define CONFIG_ETHPRIME "eTSEC1"
	459
	460	#define CONFIG_PHY_GIGE
	461	#define CONFIG_PHYLIB
	462	#define CONFIG_PHY_REALTEK
	463
	464	#define CONFIG_HAS_ETH0
	465	#define CONFIG_HAS_ETH1
	466	#define CONFIG_HAS_ETH2
	467
	468	#define CONFIG_FSL_SGMII_RISER 1
	469	#define SGMII_RISER_PHY_OFFSET 0x1b
	470
	471	#ifdef CONFIG_FSL_SGMII_RISER
	472	#define CONFIG_SYS_TBIPA_VALUE 8
	473	#endif
	474
	475	#endif
da419027 ML	476
da419027 ML	477	/* PCIe */
b38eaec5 RD	478	#define CONFIG_PCIE1 /* PCIE controller 1 */
b38eaec5 RD	479	#define CONFIG_PCIE2 /* PCIE controller 2 */
da419027	480
180b8688	481	#ifdef CONFIG_PCI
180b8688 ML	482	#define CONFIG_PCI_SCAN_SHOW
180b8688 ML	483	#define CONFIG_CMD_PCI
180b8688 ML	484	#endif
180b8688 ML	485
550e3dc0 WH	486	#define CONFIG_CMDLINE_TAG
550e3dc0 WH	487	#define CONFIG_CMDLINE_EDITING
86949c2b	488
1a2826f6	489	#define CONFIG_PEN_ADDR_BIG_ENDIAN
435acd83	490	#define CONFIG_LAYERSCAPE_NS_ACCESS
1a2826f6	491	#define CONFIG_SMP_PEN_ADDR 0x01ee0200
e4916e85	492	#define COUNTER_FREQUENCY 12500000
1a2826f6	493
550e3dc0	494	#define CONFIG_HWCONFIG
03c22449 ZZ	495	#define HWCONFIG_BUFFER_SIZE 256
	496
	497	#define CONFIG_FSL_DEVICE_DISABLE
550e3dc0	498
550e3dc0	499
713bf94f	500	#define CONFIG_SYS_QE_FW_ADDR 0x600c0000
63e75fd7	501
8fc2121a AW	502	#ifdef CONFIG_LPUART
	503	#define CONFIG_EXTRA_ENV_SETTINGS \
	504	"bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
99fe4541 AW	505	"fdt_high=0xffffffff\0" \
99fe4541 AW	506	"initrd_high=0xffffffff\0" \
8fc2121a AW	507	"hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
8fc2121a AW	508	#else
550e3dc0 WH	509	#define CONFIG_EXTRA_ENV_SETTINGS \
550e3dc0 WH	510	"bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
99fe4541 AW	511	"fdt_high=0xffffffff\0" \
99fe4541 AW	512	"initrd_high=0xffffffff\0" \
550e3dc0	513	"hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
8fc2121a	514	#endif
550e3dc0 WH	515
	516	/*
	517	* Miscellaneous configurable options
	518	*/
	519	#define CONFIG_SYS_LONGHELP /* undef to save memory */
550e3dc0 WH	520	#define CONFIG_AUTO_COMPLETE
	521	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	522	#define CONFIG_SYS_PBSIZE \
	523	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
	524	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	525	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	526
550e3dc0 WH	527	#define CONFIG_SYS_MEMTEST_START 0x80000000
	528	#define CONFIG_SYS_MEMTEST_END 0x9fffffff
	529
	530	#define CONFIG_SYS_LOAD_ADDR 0x82000000
550e3dc0	531
660673af XL	532	#define CONFIG_LS102XA_STREAM_ID
660673af XL	533
550e3dc0 WH	534	#define CONFIG_SYS_INIT_SP_OFFSET \
	535	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
	536	#define CONFIG_SYS_INIT_SP_ADDR \
	537	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
	538
86949c2b AW	539	#ifdef CONFIG_SPL_BUILD
	540	#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
	541	#else
550e3dc0	542	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
86949c2b	543	#endif
550e3dc0 WH	544
	545	/*
	546	* Environment
	547	*/
	548	#define CONFIG_ENV_OVERWRITE
	549
86949c2b AW	550	#if defined(CONFIG_SD_BOOT)
	551	#define CONFIG_ENV_OFFSET 0x100000
	552	#define CONFIG_ENV_IS_IN_MMC
	553	#define CONFIG_SYS_MMC_ENV_DEV 0
	554	#define CONFIG_ENV_SIZE 0x2000
d612f0ab AW	555	#elif defined(CONFIG_QSPI_BOOT)
	556	#define CONFIG_ENV_IS_IN_SPI_FLASH
	557	#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
	558	#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
	559	#define CONFIG_ENV_SECT_SIZE 0x10000
8ab967b6 AW	560	#elif defined(CONFIG_NAND_BOOT)
	561	#define CONFIG_ENV_IS_IN_NAND
	562	#define CONFIG_ENV_SIZE 0x2000
	563	#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
86949c2b	564	#else
550e3dc0 WH	565	#define CONFIG_ENV_IS_IN_FLASH
	566	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
	567	#define CONFIG_ENV_SIZE 0x2000
	568	#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
86949c2b	569	#endif
550e3dc0	570
4ba4a095 RG	571	#define CONFIG_MISC_INIT_R
	572
	573	/* Hash command with SHA acceleration supported in hardware */
ef6c55a2	574	#ifdef CONFIG_FSL_CAAM
4ba4a095 RG	575	#define CONFIG_CMD_HASH
4ba4a095 RG	576	#define CONFIG_SHA_HW_ACCEL
ef6c55a2 AB	577	#endif
	578
	579	#include <asm/fsl_secure_boot.h>
cc7b8b9a	580	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
4ba4a095	581
550e3dc0	582	#endif