projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 550e3dc0 WH |
1 | /* |
| 2 | * Copyright 2014 Freescale Semiconductor, Inc. | |
| 3 | * | |
| 4 | * SPDX-License-Identifier: GPL-2.0+ | |
| 5 | */ | |
| 6 | ||
| 7 | #ifndef __CONFIG_H | |
| 8 | #define __CONFIG_H | |
| 9 | ||
| 550e3dc0 WH |
10 | #define CONFIG_LS102XA |
| 11 | ||
| aeb901f2 | 12 | #define CONFIG_ARMV7_PSCI_1_0 |
| 340848b1 | 13 | |
| 3288628a HZ |
14 | #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR |
| 15 | ||
| 18fb0e3c | 16 | #define CONFIG_SYS_FSL_CLK |
| 550e3dc0 WH |
17 | |
| 18 | #define CONFIG_DISPLAY_CPUINFO | |
| 19 | #define CONFIG_DISPLAY_BOARDINFO | |
| 20 | ||
| 21 | #define CONFIG_SKIP_LOWLEVEL_INIT | |
| 22 | #define CONFIG_BOARD_EARLY_INIT_F | |
| 23 | ||
| 41ba57d0 | 24 | #define CONFIG_DEEP_SLEEP |
| 25 | #if defined(CONFIG_DEEP_SLEEP) | |
| 26 | #define CONFIG_SILENT_CONSOLE | |
| 27 | #endif | |
| 28 | ||
| 550e3dc0 WH |
29 | /* |
| 30 | * Size of malloc() pool | |
| 31 | */ | |
| 32 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) | |
| 33 | ||
| 34 | #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR | |
| 35 | #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE | |
| 36 | ||
| 37 | /* | |
| 38 | * Generic Timer Definitions | |
| 39 | */ | |
| 40 | #define GENERIC_TIMER_CLK 12500000 | |
| 41 | ||
| 42 | #ifndef __ASSEMBLY__ | |
| 43 | unsigned long get_board_sys_clk(void); | |
| 44 | unsigned long get_board_ddr_clk(void); | |
| 45 | #endif | |
| 46 | ||
| 70097027 | 47 | #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) |
| d612f0ab AW |
48 | #define CONFIG_SYS_CLK_FREQ 100000000 |
| 49 | #define CONFIG_DDR_CLK_FREQ 100000000 | |
| 50 | #define CONFIG_QIXIS_I2C_ACCESS | |
| 51 | #else | |
| 550e3dc0 WH |
52 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() |
| 53 | #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() | |
| d612f0ab | 54 | #endif |
| 550e3dc0 | 55 | |
| 86949c2b AW |
56 | #ifdef CONFIG_RAMBOOT_PBL |
| 57 | #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021aqds/ls102xa_pbi.cfg | |
| 58 | #endif | |
| 59 | ||
| 60 | #ifdef CONFIG_SD_BOOT | |
| 70097027 AW |
61 | #ifdef CONFIG_SD_BOOT_QSPI |
| 62 | #define CONFIG_SYS_FSL_PBL_RCW \ | |
| 63 | board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg | |
| 64 | #else | |
| 65 | #define CONFIG_SYS_FSL_PBL_RCW \ | |
| 66 | board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg | |
| 67 | #endif | |
| 86949c2b AW |
68 | #define CONFIG_SPL_FRAMEWORK |
| 69 | #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" | |
| 70 | #define CONFIG_SPL_LIBCOMMON_SUPPORT | |
| 71 | #define CONFIG_SPL_LIBGENERIC_SUPPORT | |
| 86949c2b | 72 | #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT |
| 86949c2b AW |
73 | #define CONFIG_SPL_WATCHDOG_SUPPORT |
| 74 | #define CONFIG_SPL_SERIAL_SUPPORT | |
| 86949c2b AW |
75 | #define CONFIG_SPL_MMC_SUPPORT |
| 76 | #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 | |
| 7ee52af4 | 77 | #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x600 |
| 86949c2b AW |
78 | |
| 79 | #define CONFIG_SPL_TEXT_BASE 0x10000000 | |
| 80 | #define CONFIG_SPL_MAX_SIZE 0x1a000 | |
| 81 | #define CONFIG_SPL_STACK 0x1001d000 | |
| 82 | #define CONFIG_SPL_PAD_TO 0x1c000 | |
| 83 | #define CONFIG_SYS_TEXT_BASE 0x82000000 | |
| 84 | ||
| 41ba57d0 | 85 | #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ |
| 86 | CONFIG_SYS_MONITOR_LEN) | |
| 86949c2b AW |
87 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 |
| 88 | #define CONFIG_SPL_BSS_START_ADDR 0x80100000 | |
| 89 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 | |
| 7ee52af4 | 90 | #define CONFIG_SYS_MONITOR_LEN 0xc0000 |
| 86949c2b AW |
91 | #endif |
| 92 | ||
| d612f0ab AW |
93 | #ifdef CONFIG_QSPI_BOOT |
| 94 | #define CONFIG_SYS_TEXT_BASE 0x40010000 | |
| 70097027 AW |
95 | #endif |
| 96 | ||
| 97 | #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) | |
| d612f0ab AW |
98 | #define CONFIG_SYS_NO_FLASH |
| 99 | #endif | |
| 100 | ||
| 8ab967b6 AW |
101 | #ifdef CONFIG_NAND_BOOT |
| 102 | #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg | |
| 103 | #define CONFIG_SPL_FRAMEWORK | |
| 104 | #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" | |
| 105 | #define CONFIG_SPL_LIBCOMMON_SUPPORT | |
| 106 | #define CONFIG_SPL_LIBGENERIC_SUPPORT | |
| 8ab967b6 | 107 | #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT |
| 8ab967b6 AW |
108 | #define CONFIG_SPL_WATCHDOG_SUPPORT |
| 109 | #define CONFIG_SPL_SERIAL_SUPPORT | |
| 110 | #define CONFIG_SPL_NAND_SUPPORT | |
| 8ab967b6 AW |
111 | |
| 112 | #define CONFIG_SPL_TEXT_BASE 0x10000000 | |
| 113 | #define CONFIG_SPL_MAX_SIZE 0x1a000 | |
| 114 | #define CONFIG_SPL_STACK 0x1001d000 | |
| 115 | #define CONFIG_SPL_PAD_TO 0x1c000 | |
| 116 | #define CONFIG_SYS_TEXT_BASE 0x82000000 | |
| 117 | ||
| 118 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10) | |
| 119 | #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO | |
| 120 | #define CONFIG_SYS_NAND_PAGE_SIZE 2048 | |
| 121 | #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE | |
| 122 | #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE | |
| 123 | ||
| 124 | #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 | |
| 125 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 | |
| 126 | #define CONFIG_SPL_BSS_START_ADDR 0x80100000 | |
| 127 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 | |
| 128 | #define CONFIG_SYS_MONITOR_LEN 0x80000 | |
| 129 | #endif | |
| 130 | ||
| 550e3dc0 | 131 | #ifndef CONFIG_SYS_TEXT_BASE |
| 1c69a51c | 132 | #define CONFIG_SYS_TEXT_BASE 0x60100000 |
| 550e3dc0 WH |
133 | #endif |
| 134 | ||
| 135 | #define CONFIG_NR_DRAM_BANKS 1 | |
| 136 | ||
| 137 | #define CONFIG_DDR_SPD | |
| 138 | #define SPD_EEPROM_ADDRESS 0x51 | |
| 139 | #define CONFIG_SYS_SPD_BUS_NUM 0 | |
| 550e3dc0 WH |
140 | |
| 141 | #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ | |
| c7eae7fc | 142 | #ifndef CONFIG_SYS_FSL_DDR4 |
| 550e3dc0 | 143 | #define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */ |
| c7eae7fc YS |
144 | #define CONFIG_SYS_DDR_RAW_TIMING |
| 145 | #endif | |
| 550e3dc0 WH |
146 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
| 147 | #define CONFIG_CHIP_SELECTS_PER_CTRL 4 | |
| 148 | ||
| 149 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL | |
| 150 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
| 151 | ||
| 152 | #define CONFIG_DDR_ECC | |
| 153 | #ifdef CONFIG_DDR_ECC | |
| 154 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER | |
| 155 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef | |
| 156 | #endif | |
| 157 | ||
| 158 | #define CONFIG_SYS_HAS_SERDES | |
| 159 | ||
| 4ba4a095 | 160 | #define CONFIG_FSL_CAAM /* Enable CAAM */ |
| 63e75fd7 | 161 | |
| 4c59ab9c AW |
162 | #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ |
| 163 | !defined(CONFIG_QSPI_BOOT) | |
| 63e75fd7 ZQ |
164 | #define CONFIG_U_QE |
| 165 | #endif | |
| 166 | ||
| 550e3dc0 WH |
167 | /* |
| 168 | * IFC Definitions | |
| 169 | */ | |
| 70097027 | 170 | #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) |
| 550e3dc0 WH |
171 | #define CONFIG_FSL_IFC |
| 172 | #define CONFIG_SYS_FLASH_BASE 0x60000000 | |
| 173 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE | |
| 174 | ||
| 175 | #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) | |
| 176 | #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ | |
| 177 | CSPR_PORT_SIZE_16 | \ | |
| 178 | CSPR_MSEL_NOR | \ | |
| 179 | CSPR_V) | |
| 180 | #define CONFIG_SYS_NOR1_CSPR_EXT (0x0) | |
| 181 | #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ | |
| 182 | + 0x8000000) | \ | |
| 183 | CSPR_PORT_SIZE_16 | \ | |
| 184 | CSPR_MSEL_NOR | \ | |
| 185 | CSPR_V) | |
| 186 | #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) | |
| 187 | ||
| 188 | #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ | |
| 189 | CSOR_NOR_TRHZ_80) | |
| 190 | #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ | |
| 191 | FTIM0_NOR_TEADC(0x5) | \ | |
| 192 | FTIM0_NOR_TEAHC(0x5)) | |
| 193 | #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ | |
| 194 | FTIM1_NOR_TRAD_NOR(0x1a) | \ | |
| 195 | FTIM1_NOR_TSEQRAD_NOR(0x13)) | |
| 196 | #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ | |
| 197 | FTIM2_NOR_TCH(0x4) | \ | |
| 198 | FTIM2_NOR_TWPH(0xe) | \ | |
| 199 | FTIM2_NOR_TWP(0x1c)) | |
| 200 | #define CONFIG_SYS_NOR_FTIM3 0 | |
| 201 | ||
| 202 | #define CONFIG_FLASH_CFI_DRIVER | |
| 203 | #define CONFIG_SYS_FLASH_CFI | |
| 204 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
| 205 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
| 206 | #define CONFIG_FLASH_SHOW_PROGRESS 45 | |
| 207 | #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS | |
| 272c5265 | 208 | #define CONFIG_SYS_WRITE_SWAPPED_DATA |
| 550e3dc0 WH |
209 | |
| 210 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ | |
| 211 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
| 212 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
| 213 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
| 214 | ||
| 215 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
| 216 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ | |
| 217 | CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} | |
| 218 | ||
| 219 | /* | |
| 220 | * NAND Flash Definitions | |
| 221 | */ | |
| 222 | #define CONFIG_NAND_FSL_IFC | |
| 223 | ||
| 224 | #define CONFIG_SYS_NAND_BASE 0x7e800000 | |
| 225 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE | |
| 226 | ||
| 227 | #define CONFIG_SYS_NAND_CSPR_EXT (0x0) | |
| 228 | ||
| 229 | #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | |
| 230 | | CSPR_PORT_SIZE_8 \ | |
| 231 | | CSPR_MSEL_NAND \ | |
| 232 | | CSPR_V) | |
| 233 | #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) | |
| 234 | #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | |
| 235 | | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | |
| 236 | | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | |
| 237 | | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ | |
| 238 | | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ | |
| 239 | | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ | |
| 240 | | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ | |
| 241 | ||
| 242 | #define CONFIG_SYS_NAND_ONFI_DETECTION | |
| 243 | ||
| 244 | #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ | |
| 245 | FTIM0_NAND_TWP(0x18) | \ | |
| 246 | FTIM0_NAND_TWCHT(0x7) | \ | |
| 247 | FTIM0_NAND_TWH(0xa)) | |
| 248 | #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ | |
| 249 | FTIM1_NAND_TWBE(0x39) | \ | |
| 250 | FTIM1_NAND_TRR(0xe) | \ | |
| 251 | FTIM1_NAND_TRP(0x18)) | |
| 252 | #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ | |
| 253 | FTIM2_NAND_TREH(0xa) | \ | |
| 254 | FTIM2_NAND_TWHRE(0x1e)) | |
| 255 | #define CONFIG_SYS_NAND_FTIM3 0x0 | |
| 256 | ||
| 257 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } | |
| 258 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
| 550e3dc0 WH |
259 | #define CONFIG_CMD_NAND |
| 260 | ||
| 261 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) | |
| d612f0ab | 262 | #endif |
| 550e3dc0 WH |
263 | |
| 264 | /* | |
| 265 | * QIXIS Definitions | |
| 266 | */ | |
| 267 | #define CONFIG_FSL_QIXIS | |
| 268 | ||
| 269 | #ifdef CONFIG_FSL_QIXIS | |
| 270 | #define QIXIS_BASE 0x7fb00000 | |
| 271 | #define QIXIS_BASE_PHYS QIXIS_BASE | |
| 272 | #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 | |
| 273 | #define QIXIS_LBMAP_SWITCH 6 | |
| 274 | #define QIXIS_LBMAP_MASK 0x0f | |
| 275 | #define QIXIS_LBMAP_SHIFT 0 | |
| 276 | #define QIXIS_LBMAP_DFLTBANK 0x00 | |
| 277 | #define QIXIS_LBMAP_ALTBANK 0x04 | |
| aeb901f2 HZ |
278 | #define QIXIS_PWR_CTL 0x21 |
| 279 | #define QIXIS_PWR_CTL_POWEROFF 0x80 | |
| 550e3dc0 WH |
280 | #define QIXIS_RST_CTL_RESET 0x44 |
| 281 | #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 | |
| 282 | #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 | |
| 283 | #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 | |
| 284 | ||
| 285 | #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) | |
| 286 | #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ | |
| 287 | CSPR_PORT_SIZE_8 | \ | |
| 288 | CSPR_MSEL_GPCM | \ | |
| 289 | CSPR_V) | |
| 290 | #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) | |
| 291 | #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ | |
| 292 | CSOR_NOR_NOR_MODE_AVD_NOR | \ | |
| 293 | CSOR_NOR_TRHZ_80) | |
| 294 | ||
| 295 | /* | |
| 296 | * QIXIS Timing parameters for IFC GPCM | |
| 297 | */ | |
| 298 | #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \ | |
| 299 | FTIM0_GPCM_TEADC(0xe) | \ | |
| 300 | FTIM0_GPCM_TEAHC(0xe)) | |
| 301 | #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \ | |
| 302 | FTIM1_GPCM_TRAD(0x1f)) | |
| 303 | #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \ | |
| 304 | FTIM2_GPCM_TCH(0xe) | \ | |
| 305 | FTIM2_GPCM_TWP(0xf0)) | |
| 306 | #define CONFIG_SYS_FPGA_FTIM3 0x0 | |
| 307 | #endif | |
| 308 | ||
| 8ab967b6 AW |
309 | #if defined(CONFIG_NAND_BOOT) |
| 310 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT | |
| 311 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR | |
| 312 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK | |
| 313 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR | |
| 314 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
| 315 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
| 316 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
| 317 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
| 318 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT | |
| 319 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR | |
| 320 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK | |
| 321 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR | |
| 322 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
| 323 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
| 324 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
| 325 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
| 326 | #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT | |
| 327 | #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR | |
| 328 | #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK | |
| 329 | #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR | |
| 330 | #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
| 331 | #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
| 332 | #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
| 333 | #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
| 334 | #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT | |
| 335 | #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR | |
| 336 | #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK | |
| 337 | #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR | |
| 338 | #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 | |
| 339 | #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 | |
| 340 | #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 | |
| 341 | #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 | |
| 342 | #else | |
| 550e3dc0 WH |
343 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT |
| 344 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR | |
| 345 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK | |
| 346 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR | |
| 347 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
| 348 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
| 349 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
| 350 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
| 351 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT | |
| 352 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR | |
| 353 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK | |
| 354 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR | |
| 355 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
| 356 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
| 357 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
| 358 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
| 359 | #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT | |
| 360 | #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR | |
| 361 | #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK | |
| 362 | #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR | |
| 363 | #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
| 364 | #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
| 365 | #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
| 366 | #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
| 367 | #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT | |
| 368 | #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR | |
| 369 | #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK | |
| 370 | #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR | |
| 371 | #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 | |
| 372 | #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 | |
| 373 | #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 | |
| 374 | #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 | |
| 8ab967b6 | 375 | #endif |
| 550e3dc0 WH |
376 | |
| 377 | /* | |
| 378 | * Serial Port | |
| 379 | */ | |
| 8fc2121a | 380 | #ifdef CONFIG_LPUART |
| 8fc2121a AW |
381 | #define CONFIG_LPUART_32B_REG |
| 382 | #else | |
| 550e3dc0 | 383 | #define CONFIG_CONS_INDEX 1 |
| 550e3dc0 | 384 | #define CONFIG_SYS_NS16550_SERIAL |
| d83b47b7 | 385 | #ifndef CONFIG_DM_SERIAL |
| 550e3dc0 | 386 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
| d83b47b7 | 387 | #endif |
| 550e3dc0 | 388 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() |
| 8fc2121a | 389 | #endif |
| 550e3dc0 WH |
390 | |
| 391 | #define CONFIG_BAUDRATE 115200 | |
| 392 | ||
| 393 | /* | |
| 394 | * I2C | |
| 395 | */ | |
| 550e3dc0 WH |
396 | #define CONFIG_SYS_I2C |
| 397 | #define CONFIG_SYS_I2C_MXC | |
| 03544c66 AA |
398 | #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ |
| 399 | #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ | |
| f8cb101e | 400 | #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ |
| 550e3dc0 WH |
401 | |
| 402 | /* | |
| 403 | * I2C bus multiplexer | |
| 404 | */ | |
| 405 | #define I2C_MUX_PCA_ADDR_PRI 0x77 | |
| 406 | #define I2C_MUX_CH_DEFAULT 0x8 | |
| dd04832d | 407 | #define I2C_MUX_CH_CH7301 0xC |
| 550e3dc0 WH |
408 | |
| 409 | /* | |
| 410 | * MMC | |
| 411 | */ | |
| 412 | #define CONFIG_MMC | |
| 550e3dc0 WH |
413 | #define CONFIG_FSL_ESDHC |
| 414 | #define CONFIG_GENERIC_MMC | |
| 415 | ||
| 8251ed23 AW |
416 | #define CONFIG_DOS_PARTITION |
| 417 | ||
| e5493d4e | 418 | /* SPI */ |
| 70097027 | 419 | #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) |
| e5493d4e | 420 | /* QSPI */ |
| d612f0ab AW |
421 | #define QSPI0_AMBA_BASE 0x40000000 |
| 422 | #define FSL_QSPI_FLASH_SIZE (1 << 24) | |
| 423 | #define FSL_QSPI_FLASH_NUM 2 | |
| 424 | ||
| e5493d4e | 425 | /* DSPI */ |
| e5493d4e HW |
426 | |
| 427 | /* DM SPI */ | |
| 428 | #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) | |
| e5493d4e | 429 | #define CONFIG_DM_SPI_FLASH |
| 6812484a | 430 | #define CONFIG_SPI_FLASH_DATAFLASH |
| e5493d4e | 431 | #endif |
| d612f0ab AW |
432 | #endif |
| 433 | ||
| 8776cb20 NB |
434 | /* |
| 435 | * USB | |
| 436 | */ | |
| 081a1b73 RM |
437 | /* EHCI Support - disbaled by default */ |
| 438 | /*#define CONFIG_HAS_FSL_DR_USB*/ | |
| 8776cb20 NB |
439 | |
| 440 | #ifdef CONFIG_HAS_FSL_DR_USB | |
| 441 | #define CONFIG_USB_EHCI | |
| 081a1b73 RM |
442 | #define CONFIG_USB_EHCI_FSL |
| 443 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
| 444 | #endif | |
| 8776cb20 | 445 | |
| 081a1b73 RM |
446 | /*XHCI Support - enabled by default*/ |
| 447 | #define CONFIG_HAS_FSL_XHCI_USB | |
| 448 | ||
| 449 | #ifdef CONFIG_HAS_FSL_XHCI_USB | |
| 450 | #define CONFIG_USB_XHCI_FSL | |
| 081a1b73 RM |
451 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
| 452 | #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 | |
| 453 | #endif | |
| 454 | ||
| dd04832d XL |
455 | /* |
| 456 | * Video | |
| 457 | */ | |
| 458 | #define CONFIG_FSL_DCU_FB | |
| 459 | ||
| 460 | #ifdef CONFIG_FSL_DCU_FB | |
| 461 | #define CONFIG_VIDEO | |
| 462 | #define CONFIG_CMD_BMP | |
| 463 | #define CONFIG_CFB_CONSOLE | |
| 464 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
| 465 | #define CONFIG_VIDEO_LOGO | |
| 466 | #define CONFIG_VIDEO_BMP_LOGO | |
| f8008f14 | 467 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV |
| dd04832d XL |
468 | |
| 469 | #define CONFIG_FSL_DIU_CH7301 | |
| 470 | #define CONFIG_SYS_I2C_DVI_BUS_NUM 0 | |
| 471 | #define CONFIG_SYS_I2C_QIXIS_ADDR 0x66 | |
| 472 | #define CONFIG_SYS_I2C_DVI_ADDR 0x75 | |
| 473 | #endif | |
| 474 | ||
| 550e3dc0 WH |
475 | /* |
| 476 | * eTSEC | |
| 477 | */ | |
| 478 | #define CONFIG_TSEC_ENET | |
| 479 | ||
| 480 | #ifdef CONFIG_TSEC_ENET | |
| 481 | #define CONFIG_MII | |
| 482 | #define CONFIG_MII_DEFAULT_TSEC 3 | |
| 483 | #define CONFIG_TSEC1 1 | |
| 484 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
| 485 | #define CONFIG_TSEC2 1 | |
| 486 | #define CONFIG_TSEC2_NAME "eTSEC2" | |
| 487 | #define CONFIG_TSEC3 1 | |
| 488 | #define CONFIG_TSEC3_NAME "eTSEC3" | |
| 489 | ||
| 490 | #define TSEC1_PHY_ADDR 1 | |
| 491 | #define TSEC2_PHY_ADDR 2 | |
| 492 | #define TSEC3_PHY_ADDR 3 | |
| 493 | ||
| 494 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 495 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 496 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 497 | ||
| 498 | #define TSEC1_PHYIDX 0 | |
| 499 | #define TSEC2_PHYIDX 0 | |
| 500 | #define TSEC3_PHYIDX 0 | |
| 501 | ||
| 502 | #define CONFIG_ETHPRIME "eTSEC1" | |
| 503 | ||
| 504 | #define CONFIG_PHY_GIGE | |
| 505 | #define CONFIG_PHYLIB | |
| 506 | #define CONFIG_PHY_REALTEK | |
| 507 | ||
| 508 | #define CONFIG_HAS_ETH0 | |
| 509 | #define CONFIG_HAS_ETH1 | |
| 510 | #define CONFIG_HAS_ETH2 | |
| 511 | ||
| 512 | #define CONFIG_FSL_SGMII_RISER 1 | |
| 513 | #define SGMII_RISER_PHY_OFFSET 0x1b | |
| 514 | ||
| 515 | #ifdef CONFIG_FSL_SGMII_RISER | |
| 516 | #define CONFIG_SYS_TBIPA_VALUE 8 | |
| 517 | #endif | |
| 518 | ||
| 519 | #endif | |
| da419027 ML |
520 | |
| 521 | /* PCIe */ | |
| 522 | #define CONFIG_PCI /* Enable PCI/PCIE */ | |
| b38eaec5 RD |
523 | #define CONFIG_PCIE1 /* PCIE controller 1 */ |
| 524 | #define CONFIG_PCIE2 /* PCIE controller 2 */ | |
| da419027 ML |
525 | #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ |
| 526 | #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" | |
| 527 | ||
| 180b8688 ML |
528 | #define CONFIG_SYS_PCI_64BIT |
| 529 | ||
| 530 | #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 | |
| 531 | #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ | |
| 532 | #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 | |
| 533 | #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ | |
| 534 | ||
| 535 | #define CONFIG_SYS_PCIE_IO_BUS 0x00000000 | |
| 536 | #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 | |
| 537 | #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ | |
| 538 | ||
| 539 | #define CONFIG_SYS_PCIE_MEM_BUS 0x08000000 | |
| 540 | #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000 | |
| 541 | #define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */ | |
| 542 | ||
| 543 | #ifdef CONFIG_PCI | |
| 180b8688 | 544 | #define CONFIG_PCI_PNP |
| 180b8688 ML |
545 | #define CONFIG_PCI_SCAN_SHOW |
| 546 | #define CONFIG_CMD_PCI | |
| 180b8688 ML |
547 | #endif |
| 548 | ||
| 550e3dc0 WH |
549 | #define CONFIG_CMDLINE_TAG |
| 550 | #define CONFIG_CMDLINE_EDITING | |
| 86949c2b | 551 | |
| 1a2826f6 XL |
552 | #define CONFIG_ARMV7_NONSEC |
| 553 | #define CONFIG_ARMV7_VIRT | |
| 554 | #define CONFIG_PEN_ADDR_BIG_ENDIAN | |
| 435acd83 | 555 | #define CONFIG_LAYERSCAPE_NS_ACCESS |
| 1a2826f6 XL |
556 | #define CONFIG_SMP_PEN_ADDR 0x01ee0200 |
| 557 | #define CONFIG_TIMER_CLK_FREQ 12500000 | |
| 1a2826f6 | 558 | |
| 550e3dc0 | 559 | #define CONFIG_HWCONFIG |
| 03c22449 ZZ |
560 | #define HWCONFIG_BUFFER_SIZE 256 |
| 561 | ||
| 562 | #define CONFIG_FSL_DEVICE_DISABLE | |
| 550e3dc0 | 563 | |
| 550e3dc0 | 564 | |
| 713bf94f | 565 | #define CONFIG_SYS_QE_FW_ADDR 0x600c0000 |
| 63e75fd7 | 566 | |
| 8fc2121a AW |
567 | #ifdef CONFIG_LPUART |
| 568 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 569 | "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ | |
| 99fe4541 AW |
570 | "fdt_high=0xffffffff\0" \ |
| 571 | "initrd_high=0xffffffff\0" \ | |
| 8fc2121a AW |
572 | "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" |
| 573 | #else | |
| 550e3dc0 WH |
574 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 575 | "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ | |
| 99fe4541 AW |
576 | "fdt_high=0xffffffff\0" \ |
| 577 | "initrd_high=0xffffffff\0" \ | |
| 550e3dc0 | 578 | "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" |
| 8fc2121a | 579 | #endif |
| 550e3dc0 WH |
580 | |
| 581 | /* | |
| 582 | * Miscellaneous configurable options | |
| 583 | */ | |
| 584 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
| 550e3dc0 WH |
585 | #define CONFIG_AUTO_COMPLETE |
| 586 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
| 587 | #define CONFIG_SYS_PBSIZE \ | |
| 588 | (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
| 589 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
| 590 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
| 591 | ||
| 550e3dc0 WH |
592 | #define CONFIG_SYS_MEMTEST_START 0x80000000 |
| 593 | #define CONFIG_SYS_MEMTEST_END 0x9fffffff | |
| 594 | ||
| 595 | #define CONFIG_SYS_LOAD_ADDR 0x82000000 | |
| 550e3dc0 | 596 | |
| 660673af XL |
597 | #define CONFIG_LS102XA_STREAM_ID |
| 598 | ||
| 550e3dc0 WH |
599 | /* |
| 600 | * Stack sizes | |
| 601 | * The stack sizes are set up in start.S using the settings below | |
| 602 | */ | |
| 603 | #define CONFIG_STACKSIZE (30 * 1024) | |
| 604 | ||
| 605 | #define CONFIG_SYS_INIT_SP_OFFSET \ | |
| 606 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
| 607 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
| 608 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) | |
| 609 | ||
| 86949c2b AW |
610 | #ifdef CONFIG_SPL_BUILD |
| 611 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE | |
| 612 | #else | |
| 550e3dc0 | 613 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
| 86949c2b | 614 | #endif |
| 550e3dc0 WH |
615 | |
| 616 | /* | |
| 617 | * Environment | |
| 618 | */ | |
| 619 | #define CONFIG_ENV_OVERWRITE | |
| 620 | ||
| 86949c2b AW |
621 | #if defined(CONFIG_SD_BOOT) |
| 622 | #define CONFIG_ENV_OFFSET 0x100000 | |
| 623 | #define CONFIG_ENV_IS_IN_MMC | |
| 624 | #define CONFIG_SYS_MMC_ENV_DEV 0 | |
| 625 | #define CONFIG_ENV_SIZE 0x2000 | |
| d612f0ab AW |
626 | #elif defined(CONFIG_QSPI_BOOT) |
| 627 | #define CONFIG_ENV_IS_IN_SPI_FLASH | |
| 628 | #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ | |
| 629 | #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ | |
| 630 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
| 8ab967b6 AW |
631 | #elif defined(CONFIG_NAND_BOOT) |
| 632 | #define CONFIG_ENV_IS_IN_NAND | |
| 633 | #define CONFIG_ENV_SIZE 0x2000 | |
| 634 | #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) | |
| 86949c2b | 635 | #else |
| 550e3dc0 WH |
636 | #define CONFIG_ENV_IS_IN_FLASH |
| 637 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) | |
| 638 | #define CONFIG_ENV_SIZE 0x2000 | |
| 639 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ | |
| 86949c2b | 640 | #endif |
| 550e3dc0 | 641 | |
| 4ba4a095 RG |
642 | #define CONFIG_MISC_INIT_R |
| 643 | ||
| 644 | /* Hash command with SHA acceleration supported in hardware */ | |
| ef6c55a2 | 645 | #ifdef CONFIG_FSL_CAAM |
| 4ba4a095 RG |
646 | #define CONFIG_CMD_HASH |
| 647 | #define CONFIG_SHA_HW_ACCEL | |
| ef6c55a2 AB |
648 | #endif |
| 649 | ||
| 650 | #include <asm/fsl_secure_boot.h> | |
| cc7b8b9a | 651 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ |
| 4ba4a095 | 652 | |
| 550e3dc0 | 653 | #endif |