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02b5d2ed SX |
1 | /* |
2 | * Copyright 2015 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
6 | ||
7 | #ifndef __LS1043AQDS_H__ | |
8 | #define __LS1043AQDS_H__ | |
9 | ||
10 | #include "ls1043a_common.h" | |
11 | ||
02b5d2ed SX |
12 | #if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT) |
13 | #define CONFIG_SYS_TEXT_BASE 0x82000000 | |
b0f20caf QG |
14 | #elif defined(CONFIG_QSPI_BOOT) |
15 | #define CONFIG_SYS_TEXT_BASE 0x40010000 | |
02b5d2ed SX |
16 | #else |
17 | #define CONFIG_SYS_TEXT_BASE 0x60100000 | |
18 | #endif | |
19 | ||
20 | #ifndef __ASSEMBLY__ | |
21 | unsigned long get_board_sys_clk(void); | |
22 | unsigned long get_board_ddr_clk(void); | |
23 | #endif | |
24 | ||
581ff00b QG |
25 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() |
26 | #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() | |
02b5d2ed SX |
27 | |
28 | #define CONFIG_SKIP_LOWLEVEL_INIT | |
29 | ||
30 | #define CONFIG_LAYERSCAPE_NS_ACCESS | |
31 | ||
32 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
33 | /* Physical Memory Map */ | |
34 | #define CONFIG_CHIP_SELECTS_PER_CTRL 4 | |
58e4ad1d | 35 | #define CONFIG_NR_DRAM_BANKS 2 |
02b5d2ed SX |
36 | |
37 | #define CONFIG_DDR_SPD | |
38 | #define SPD_EEPROM_ADDRESS 0x51 | |
39 | #define CONFIG_SYS_SPD_BUS_NUM 0 | |
40 | ||
41 | #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ | |
02b5d2ed SX |
42 | |
43 | #define CONFIG_DDR_ECC | |
44 | #ifdef CONFIG_DDR_ECC | |
45 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER | |
46 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef | |
47 | #endif | |
48 | ||
02b5d2ed SX |
49 | #ifdef CONFIG_SYS_DPAA_FMAN |
50 | #define CONFIG_FMAN_ENET | |
51 | #define CONFIG_PHYLIB | |
52 | #define CONFIG_PHY_VITESSE | |
53 | #define CONFIG_PHY_REALTEK | |
54 | #define CONFIG_PHYLIB_10G | |
55 | #define RGMII_PHY1_ADDR 0x1 | |
56 | #define RGMII_PHY2_ADDR 0x2 | |
57 | #define SGMII_CARD_PORT1_PHY_ADDR 0x1C | |
58 | #define SGMII_CARD_PORT2_PHY_ADDR 0x1D | |
59 | #define SGMII_CARD_PORT3_PHY_ADDR 0x1E | |
60 | #define SGMII_CARD_PORT4_PHY_ADDR 0x1F | |
61 | /* PHY address on QSGMII riser card on slot 1 */ | |
62 | #define QSGMII_CARD_PORT1_PHY_ADDR_S1 0x4 | |
63 | #define QSGMII_CARD_PORT2_PHY_ADDR_S1 0x5 | |
64 | #define QSGMII_CARD_PORT3_PHY_ADDR_S1 0x6 | |
65 | #define QSGMII_CARD_PORT4_PHY_ADDR_S1 0x7 | |
66 | /* PHY address on QSGMII riser card on slot 2 */ | |
67 | #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8 | |
68 | #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9 | |
69 | #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA | |
70 | #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB | |
71 | #endif | |
72 | ||
73 | #ifdef CONFIG_RAMBOOT_PBL | |
74 | #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043aqds/ls1043aqds_pbi.cfg | |
75 | #endif | |
76 | ||
77 | #ifdef CONFIG_NAND_BOOT | |
78 | #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg | |
79 | #endif | |
80 | ||
81 | #ifdef CONFIG_SD_BOOT | |
166ef1e9 GQ |
82 | #ifdef CONFIG_SD_BOOT_QSPI |
83 | #define CONFIG_SYS_FSL_PBL_RCW \ | |
84 | board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg | |
85 | #else | |
02b5d2ed SX |
86 | #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg |
87 | #endif | |
166ef1e9 | 88 | #endif |
02b5d2ed | 89 | |
2970e14f WS |
90 | /* LPUART */ |
91 | #ifdef CONFIG_LPUART | |
92 | #define CONFIG_LPUART_32B_REG | |
93 | #endif | |
94 | ||
989c5f0a TY |
95 | /* SATA */ |
96 | #define CONFIG_LIBATA | |
97 | #define CONFIG_SCSI_AHCI | |
98 | #define CONFIG_SCSI_AHCI_PLAT | |
c649e3c9 | 99 | #define CONFIG_SCSI |
989c5f0a | 100 | |
ceded371 WS |
101 | /* EEPROM */ |
102 | #define CONFIG_ID_EEPROM | |
103 | #define CONFIG_SYS_I2C_EEPROM_NXID | |
104 | #define CONFIG_SYS_EEPROM_BUS_NUM 0 | |
105 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 | |
106 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
107 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
108 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 | |
109 | ||
989c5f0a TY |
110 | #define CONFIG_SYS_SATA AHCI_BASE_ADDR |
111 | ||
112 | #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 | |
113 | #define CONFIG_SYS_SCSI_MAX_LUN 1 | |
114 | #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ | |
115 | CONFIG_SYS_SCSI_MAX_LUN) | |
116 | ||
02b5d2ed SX |
117 | /* |
118 | * IFC Definitions | |
119 | */ | |
b0f20caf | 120 | #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) |
02b5d2ed SX |
121 | #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) |
122 | #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ | |
123 | CSPR_PORT_SIZE_16 | \ | |
124 | CSPR_MSEL_NOR | \ | |
125 | CSPR_V) | |
126 | #define CONFIG_SYS_NOR1_CSPR_EXT (0x0) | |
127 | #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ | |
128 | + 0x8000000) | \ | |
129 | CSPR_PORT_SIZE_16 | \ | |
130 | CSPR_MSEL_NOR | \ | |
131 | CSPR_V) | |
132 | #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) | |
133 | ||
134 | #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ | |
135 | CSOR_NOR_TRHZ_80) | |
136 | #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ | |
137 | FTIM0_NOR_TEADC(0x5) | \ | |
138 | FTIM0_NOR_TEAHC(0x5)) | |
139 | #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ | |
140 | FTIM1_NOR_TRAD_NOR(0x1a) | \ | |
141 | FTIM1_NOR_TSEQRAD_NOR(0x13)) | |
142 | #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ | |
143 | FTIM2_NOR_TCH(0x4) | \ | |
144 | FTIM2_NOR_TWPH(0xe) | \ | |
145 | FTIM2_NOR_TWP(0x1c)) | |
146 | #define CONFIG_SYS_NOR_FTIM3 0 | |
147 | ||
1b245d9a | 148 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
02b5d2ed SX |
149 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ |
150 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
151 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
152 | ||
153 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
154 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ | |
155 | CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} | |
156 | ||
157 | #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS | |
158 | #define CONFIG_SYS_WRITE_SWAPPED_DATA | |
159 | ||
160 | /* | |
161 | * NAND Flash Definitions | |
162 | */ | |
163 | #define CONFIG_NAND_FSL_IFC | |
164 | ||
165 | #define CONFIG_SYS_NAND_BASE 0x7e800000 | |
166 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE | |
167 | ||
168 | #define CONFIG_SYS_NAND_CSPR_EXT (0x0) | |
169 | ||
170 | #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | |
171 | | CSPR_PORT_SIZE_8 \ | |
172 | | CSPR_MSEL_NAND \ | |
173 | | CSPR_V) | |
174 | #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) | |
175 | #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | |
176 | | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | |
177 | | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | |
178 | | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ | |
179 | | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ | |
180 | | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ | |
181 | | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ | |
182 | ||
183 | #define CONFIG_SYS_NAND_ONFI_DETECTION | |
184 | ||
185 | #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ | |
186 | FTIM0_NAND_TWP(0x18) | \ | |
187 | FTIM0_NAND_TWCHT(0x7) | \ | |
188 | FTIM0_NAND_TWH(0xa)) | |
189 | #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ | |
190 | FTIM1_NAND_TWBE(0x39) | \ | |
191 | FTIM1_NAND_TRR(0xe) | \ | |
192 | FTIM1_NAND_TRP(0x18)) | |
193 | #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ | |
194 | FTIM2_NAND_TREH(0xa) | \ | |
195 | FTIM2_NAND_TWHRE(0x1e)) | |
196 | #define CONFIG_SYS_NAND_FTIM3 0x0 | |
197 | ||
198 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } | |
199 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
200 | #define CONFIG_MTD_NAND_VERIFY_WRITE | |
201 | #define CONFIG_CMD_NAND | |
202 | ||
203 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) | |
166ef1e9 | 204 | #endif |
02b5d2ed SX |
205 | |
206 | #ifdef CONFIG_NAND_BOOT | |
207 | #define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */ | |
208 | #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO | |
209 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10) | |
210 | #endif | |
211 | ||
b0f20caf | 212 | #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) |
166ef1e9 | 213 | #define CONFIG_QIXIS_I2C_ACCESS |
581ff00b | 214 | #define CONFIG_SYS_I2C_EARLY_INIT |
166ef1e9 GQ |
215 | #endif |
216 | ||
02b5d2ed SX |
217 | /* |
218 | * QIXIS Definitions | |
219 | */ | |
220 | #define CONFIG_FSL_QIXIS | |
221 | ||
222 | #ifdef CONFIG_FSL_QIXIS | |
223 | #define QIXIS_BASE 0x7fb00000 | |
224 | #define QIXIS_BASE_PHYS QIXIS_BASE | |
225 | #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 | |
226 | #define QIXIS_LBMAP_SWITCH 6 | |
227 | #define QIXIS_LBMAP_MASK 0x0f | |
228 | #define QIXIS_LBMAP_SHIFT 0 | |
229 | #define QIXIS_LBMAP_DFLTBANK 0x00 | |
230 | #define QIXIS_LBMAP_ALTBANK 0x04 | |
ee2a4eee GQ |
231 | #define QIXIS_LBMAP_NAND 0x09 |
232 | #define QIXIS_LBMAP_SD 0x00 | |
166ef1e9 | 233 | #define QIXIS_LBMAP_SD_QSPI 0xff |
b0f20caf | 234 | #define QIXIS_LBMAP_QSPI 0xff |
ee2a4eee GQ |
235 | #define QIXIS_RCW_SRC_NAND 0x106 |
236 | #define QIXIS_RCW_SRC_SD 0x040 | |
b0f20caf | 237 | #define QIXIS_RCW_SRC_QSPI 0x045 |
a4b7d68c | 238 | #define QIXIS_RST_CTL_RESET 0x41 |
02b5d2ed SX |
239 | #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 |
240 | #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 | |
241 | #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 | |
242 | ||
243 | #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) | |
244 | #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ | |
245 | CSPR_PORT_SIZE_8 | \ | |
246 | CSPR_MSEL_GPCM | \ | |
247 | CSPR_V) | |
248 | #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) | |
249 | #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ | |
250 | CSOR_NOR_NOR_MODE_AVD_NOR | \ | |
251 | CSOR_NOR_TRHZ_80) | |
252 | ||
253 | /* | |
254 | * QIXIS Timing parameters for IFC GPCM | |
255 | */ | |
256 | #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \ | |
257 | FTIM0_GPCM_TEADC(0x20) | \ | |
258 | FTIM0_GPCM_TEAHC(0x10)) | |
259 | #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \ | |
260 | FTIM1_GPCM_TRAD(0x1f)) | |
261 | #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \ | |
262 | FTIM2_GPCM_TCH(0x8) | \ | |
263 | FTIM2_GPCM_TWP(0xf0)) | |
264 | #define CONFIG_SYS_FPGA_FTIM3 0x0 | |
265 | #endif | |
266 | ||
267 | #ifdef CONFIG_NAND_BOOT | |
268 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT | |
269 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR | |
270 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK | |
271 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR | |
272 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
273 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
274 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
275 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
276 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT | |
277 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR | |
278 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK | |
279 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR | |
280 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
281 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
282 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
283 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
284 | #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT | |
285 | #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR | |
286 | #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK | |
287 | #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR | |
288 | #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
289 | #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
290 | #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
291 | #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
292 | #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT | |
293 | #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR | |
294 | #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK | |
295 | #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR | |
296 | #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 | |
297 | #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 | |
298 | #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 | |
299 | #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 | |
300 | #else | |
301 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT | |
302 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR | |
303 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK | |
304 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR | |
305 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
306 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
307 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
308 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
309 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT | |
310 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR | |
311 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK | |
312 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR | |
313 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
314 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
315 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
316 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
317 | #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT | |
318 | #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR | |
319 | #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK | |
320 | #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR | |
321 | #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
322 | #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
323 | #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
324 | #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
325 | #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT | |
326 | #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR | |
327 | #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK | |
328 | #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR | |
329 | #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 | |
330 | #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 | |
331 | #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 | |
332 | #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 | |
333 | #endif | |
334 | ||
335 | /* | |
336 | * I2C bus multiplexer | |
337 | */ | |
338 | #define I2C_MUX_PCA_ADDR_PRI 0x77 | |
339 | #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ | |
340 | #define I2C_RETIMER_ADDR 0x18 | |
341 | #define I2C_MUX_CH_DEFAULT 0x8 | |
342 | #define I2C_MUX_CH_CH7301 0xC | |
343 | #define I2C_MUX_CH5 0xD | |
344 | #define I2C_MUX_CH7 0xF | |
345 | ||
346 | #define I2C_MUX_CH_VOL_MONITOR 0xa | |
347 | ||
348 | /* Voltage monitor on channel 2*/ | |
349 | #define I2C_VOL_MONITOR_ADDR 0x40 | |
350 | #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 | |
351 | #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 | |
352 | #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 | |
353 | ||
354 | #define CONFIG_VID_FLS_ENV "ls1043aqds_vdd_mv" | |
355 | #ifndef CONFIG_SPL_BUILD | |
356 | #define CONFIG_VID | |
357 | #endif | |
358 | #define CONFIG_VOL_MONITOR_IR36021_SET | |
359 | #define CONFIG_VOL_MONITOR_INA220 | |
360 | /* The lowest and highest voltage allowed for LS1043AQDS */ | |
361 | #define VDD_MV_MIN 819 | |
362 | #define VDD_MV_MAX 1212 | |
363 | ||
166ef1e9 | 364 | /* QSPI device */ |
b0f20caf | 365 | #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) |
166ef1e9 GQ |
366 | #define CONFIG_FSL_QSPI |
367 | #ifdef CONFIG_FSL_QSPI | |
368 | #define CONFIG_SPI_FLASH_SPANSION | |
369 | #define FSL_QSPI_FLASH_SIZE (1 << 24) | |
370 | #define FSL_QSPI_FLASH_NUM 2 | |
371 | #endif | |
372 | #endif | |
373 | ||
5a7c40be QG |
374 | /* USB */ |
375 | #define CONFIG_HAS_FSL_XHCI_USB | |
376 | #ifdef CONFIG_HAS_FSL_XHCI_USB | |
5a7c40be | 377 | #define CONFIG_USB_XHCI_FSL |
5a7c40be QG |
378 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 |
379 | #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 | |
5a7c40be QG |
380 | #endif |
381 | ||
02b5d2ed SX |
382 | /* |
383 | * Miscellaneous configurable options | |
384 | */ | |
385 | #define CONFIG_MISC_INIT_R | |
386 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
02b5d2ed SX |
387 | #define CONFIG_AUTO_COMPLETE |
388 | #define CONFIG_SYS_PBSIZE \ | |
389 | (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
390 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
391 | ||
02b5d2ed SX |
392 | #define CONFIG_SYS_MEMTEST_START 0x80000000 |
393 | #define CONFIG_SYS_MEMTEST_END 0x9fffffff | |
394 | ||
395 | #define CONFIG_SYS_HZ 1000 | |
396 | ||
397 | /* | |
398 | * Stack sizes | |
399 | * The stack sizes are set up in start.S using the settings below | |
400 | */ | |
401 | #define CONFIG_STACKSIZE (30 * 1024) | |
402 | ||
403 | #define CONFIG_SYS_INIT_SP_OFFSET \ | |
404 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
405 | ||
406 | #ifdef CONFIG_SPL_BUILD | |
407 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE | |
408 | #else | |
409 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ | |
410 | #endif | |
411 | ||
412 | /* | |
413 | * Environment | |
414 | */ | |
415 | #define CONFIG_ENV_OVERWRITE | |
416 | ||
417 | #ifdef CONFIG_NAND_BOOT | |
418 | #define CONFIG_ENV_IS_IN_NAND | |
419 | #define CONFIG_ENV_SIZE 0x2000 | |
420 | #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) | |
421 | #elif defined(CONFIG_SD_BOOT) | |
422 | #define CONFIG_ENV_OFFSET (1024 * 1024) | |
423 | #define CONFIG_ENV_IS_IN_MMC | |
424 | #define CONFIG_SYS_MMC_ENV_DEV 0 | |
425 | #define CONFIG_ENV_SIZE 0x2000 | |
b0f20caf QG |
426 | #elif defined(CONFIG_QSPI_BOOT) |
427 | #define CONFIG_ENV_IS_IN_SPI_FLASH | |
428 | #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ | |
429 | #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ | |
430 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
02b5d2ed SX |
431 | #else |
432 | #define CONFIG_ENV_IS_IN_FLASH | |
433 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000) | |
434 | #define CONFIG_ENV_SECT_SIZE 0x20000 | |
435 | #define CONFIG_ENV_SIZE 0x20000 | |
436 | #endif | |
437 | ||
02b5d2ed SX |
438 | #define CONFIG_CMDLINE_TAG |
439 | ||
ef6c55a2 AB |
440 | #include <asm/fsl_secure_boot.h> |
441 | ||
02b5d2ed | 442 | #endif /* __LS1043AQDS_H__ */ |