[people/ms/u-boot.git] / include / configs / ls1043ardb.h

/*
 * Copyright 2015 Freescale Semiconductor
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __LS1043ARDB_H__
#define __LS1043ARDB_H__

#include "ls1043a_common.h"

#if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT)
#define CONFIG_SYS_TEXT_BASE		0x82000000
#else
#define CONFIG_SYS_TEXT_BASE		0x60100000
#endif

#define CONFIG_SYS_CLK_FREQ		100000000
#define CONFIG_DDR_CLK_FREQ		100000000

#define CONFIG_LAYERSCAPE_NS_ACCESS
#define CONFIG_MISC_INIT_R

#define CONFIG_DIMM_SLOTS_PER_CTLR	1
/* Physical Memory Map */
#define CONFIG_CHIP_SELECTS_PER_CTRL	4
#define CONFIG_NR_DRAM_BANKS		2

#define CONFIG_SYS_SPD_BUS_NUM		0

#define CONFIG_FSL_DDR_BIST
#define CONFIG_FSL_DDR_INTERACTIVE	/* Interactive debugging */
#define CONFIG_SYS_DDR_RAW_TIMING
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE           0xdeadbeef

#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043ardb/ls1043ardb_pbi.cfg
#endif

#ifdef CONFIG_NAND_BOOT
#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg
#endif

#ifdef CONFIG_SD_BOOT
#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg
#endif

/*
 * NOR Flash Definitions
 */
#define CONFIG_SYS_NOR_CSPR_EXT		(0x0)
#define CONFIG_SYS_NOR_AMASK		IFC_AMASK(128*1024*1024)
#define CONFIG_SYS_NOR_CSPR					\
	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)		| \
	CSPR_PORT_SIZE_16					| \
	CSPR_MSEL_NOR						| \
	CSPR_V)

/* NOR Flash Timing Params */
#define CONFIG_SYS_NOR_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
					CSOR_NOR_TRHZ_80)
#define CONFIG_SYS_NOR_FTIM0		(FTIM0_NOR_TACSE(0x1) | \
					FTIM0_NOR_TEADC(0x1) | \
					FTIM0_NOR_TAVDS(0x0) | \
					FTIM0_NOR_TEAHC(0xc))
#define CONFIG_SYS_NOR_FTIM1		(FTIM1_NOR_TACO(0x1c) | \
					FTIM1_NOR_TRAD_NOR(0xb) | \
					FTIM1_NOR_TSEQRAD_NOR(0x9))
#define CONFIG_SYS_NOR_FTIM2		(FTIM2_NOR_TCS(0x1) | \
					FTIM2_NOR_TCH(0x4) | \
					FTIM2_NOR_TWPH(0x8) | \
					FTIM2_NOR_TWP(0x10))
#define CONFIG_SYS_NOR_FTIM3		0
#define CONFIG_SYS_IFC_CCR		0x01000000

#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */

#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE_PHYS }

#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
#define CONFIG_SYS_WRITE_SWAPPED_DATA

/*
 * NAND Flash Definitions
 */
#define CONFIG_NAND_FSL_IFC

#define CONFIG_SYS_NAND_BASE		0x7e800000
#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE

#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
				| CSPR_PORT_SIZE_8	\
				| CSPR_MSEL_NAND	\
				| CSPR_V)
#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
				| CSOR_NAND_ECC_MODE_4	/* 4-bit ECC */ \
				| CSOR_NAND_RAL_3	/* RAL = 3 Bytes */ \
				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
				| CSOR_NAND_SPRZ_64	/* Spare size = 64 */ \
				| CSOR_NAND_PB(64))	/* 64 Pages Per Block */

#define CONFIG_SYS_NAND_ONFI_DETECTION

#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x7) | \
					FTIM0_NAND_TWP(0x18)   | \
					FTIM0_NAND_TWCHT(0x7) | \
					FTIM0_NAND_TWH(0xa))
#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
					FTIM1_NAND_TWBE(0x39)  | \
					FTIM1_NAND_TRR(0xe)   | \
					FTIM1_NAND_TRP(0x18))
#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0xf) | \
					FTIM2_NAND_TREH(0xa) | \
					FTIM2_NAND_TWHRE(0x1e))
#define CONFIG_SYS_NAND_FTIM3		0x0

#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND

#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)

#ifdef CONFIG_NAND_BOOT
#define CONFIG_SPL_PAD_TO		0x20000		/* block aligned */
#define CONFIG_SYS_NAND_U_BOOT_OFFS	CONFIG_SPL_PAD_TO
#define CONFIG_SYS_NAND_U_BOOT_SIZE	(640 << 10)
#endif

/*
 * CPLD
 */
#define CONFIG_SYS_CPLD_BASE		0x7fb00000
#define CPLD_BASE_PHYS			CONFIG_SYS_CPLD_BASE

#define CONFIG_SYS_CPLD_CSPR_EXT	(0x0)
#define CONFIG_SYS_CPLD_CSPR		(CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
					CSPR_PORT_SIZE_8 | \
					CSPR_MSEL_GPCM | \
					CSPR_V)
#define CONFIG_SYS_CPLD_AMASK		IFC_AMASK(64 * 1024)
#define CONFIG_SYS_CPLD_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
					CSOR_NOR_NOR_MODE_AVD_NOR | \
					CSOR_NOR_TRHZ_80)

/* CPLD Timing parameters for IFC GPCM */
#define CONFIG_SYS_CPLD_FTIM0		(FTIM0_GPCM_TACSE(0xf) | \
					FTIM0_GPCM_TEADC(0xf) | \
					FTIM0_GPCM_TEAHC(0xf))
#define CONFIG_SYS_CPLD_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
					FTIM1_GPCM_TRAD(0x3f))
#define CONFIG_SYS_CPLD_FTIM2		(FTIM2_GPCM_TCS(0xf) | \
					FTIM2_GPCM_TCH(0xf) | \
					FTIM2_GPCM_TWP(0xff))
#define CONFIG_SYS_CPLD_FTIM3		0x0

/* IFC Timing Params */
#ifdef CONFIG_NAND_BOOT
#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3

#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR_CSPR_EXT
#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR_CSPR
#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
#else
#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR_CSPR_EXT
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3

#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR1		CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK1		CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR1		CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
#endif

#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_CPLD_CSPR_EXT
#define CONFIG_SYS_CSPR2		CONFIG_SYS_CPLD_CSPR
#define CONFIG_SYS_AMASK2		CONFIG_SYS_CPLD_AMASK
#define CONFIG_SYS_CSOR2		CONFIG_SYS_CPLD_CSOR
#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_CPLD_FTIM0
#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_CPLD_FTIM1
#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_CPLD_FTIM2
#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_CPLD_FTIM3

/* EEPROM */
#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM		0
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x53
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5

/*
 * Environment
 */
#define CONFIG_ENV_OVERWRITE

#if defined(CONFIG_NAND_BOOT)
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SIZE			0x2000
#define CONFIG_ENV_OFFSET		(10 * CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_SD_BOOT)
#define CONFIG_ENV_OFFSET		(1024 * 1024)
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV		0
#define CONFIG_ENV_SIZE			0x2000
#else
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x200000)
#define CONFIG_ENV_SECT_SIZE		0x20000
#define CONFIG_ENV_SIZE			0x20000
#endif

/* FMan */
#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_FMAN_ENET
#define CONFIG_PHYLIB
#define CONFIG_PHYLIB_10G
#define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */

#define CONFIG_PHY_VITESSE
#define CONFIG_PHY_REALTEK
#define CONFIG_PHY_AQUANTIA
#define AQR105_IRQ_MASK			0x40000000

#define RGMII_PHY1_ADDR			0x1
#define RGMII_PHY2_ADDR			0x2

#define QSGMII_PORT1_PHY_ADDR		0x4
#define QSGMII_PORT2_PHY_ADDR		0x5
#define QSGMII_PORT3_PHY_ADDR		0x6
#define QSGMII_PORT4_PHY_ADDR		0x7

#define FM1_10GEC1_PHY_ADDR		0x1

#define CONFIG_ETHPRIME			"FM1@DTSEC3"
#endif

/* QE */
#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
	!defined(CONFIG_QSPI_BOOT)
#define CONFIG_U_QE
#endif
#define CONFIG_SYS_QE_FW_ADDR     0x60600000

/* USB */
#define CONFIG_HAS_FSL_XHCI_USB
#ifdef CONFIG_HAS_FSL_XHCI_USB
#define CONFIG_USB_XHCI_FSL
#define CONFIG_USB_MAX_CONTROLLER_COUNT		3
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS	2
#endif

/* SATA */
#define CONFIG_LIBATA
#define CONFIG_SCSI_AHCI
#define CONFIG_CMD_SCSI
#ifndef CONFIG_CMD_FAT
#define CONFIG_CMD_FAT
#endif
#ifndef CONFIG_CMD_EXT2
#define CONFIG_CMD_EXT2
#endif
#define CONFIG_SYS_SCSI_MAX_SCSI_ID		2
#define CONFIG_SYS_SCSI_MAX_LUN			2
#define CONFIG_SYS_SCSI_MAX_DEVICE		(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
						CONFIG_SYS_SCSI_MAX_LUN)
#define SCSI_VEND_ID 0x1b4b
#define SCSI_DEV_ID  0x9170
#define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID}

#include <asm/fsl_secure_boot.h>

#endif /* __LS1043ARDB_H__ */
Commit	Line	Data
f3a8e2b7 MH	1	/*
	2	* Copyright 2015 Freescale Semiconductor
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#ifndef __LS1043ARDB_H__
	8	#define __LS1043ARDB_H__
	9
	10	#include "ls1043a_common.h"
	11
c7ca8b07	12	#if defined(CONFIG_NAND_BOOT) \|\| defined(CONFIG_SD_BOOT)
3ad44729 GQ	13	#define CONFIG_SYS_TEXT_BASE 0x82000000
3ad44729 GQ	14	#else
f3a8e2b7	15	#define CONFIG_SYS_TEXT_BASE 0x60100000
3ad44729	16	#endif
f3a8e2b7 MH	17
	18	#define CONFIG_SYS_CLK_FREQ 100000000
	19	#define CONFIG_DDR_CLK_FREQ 100000000
	20
	21	#define CONFIG_LAYERSCAPE_NS_ACCESS
	22	#define CONFIG_MISC_INIT_R
	23
	24	#define CONFIG_DIMM_SLOTS_PER_CTLR 1
	25	/* Physical Memory Map */
	26	#define CONFIG_CHIP_SELECTS_PER_CTRL 4
e994dddb	27	#define CONFIG_NR_DRAM_BANKS 2
f3a8e2b7 MH	28
	29	#define CONFIG_SYS_SPD_BUS_NUM 0
	30
	31	#define CONFIG_FSL_DDR_BIST
	32	#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
	33	#define CONFIG_SYS_DDR_RAW_TIMING
	34	#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
	35	#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
	36
3ad44729 GQ	37	#ifdef CONFIG_RAMBOOT_PBL
	38	#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043ardb/ls1043ardb_pbi.cfg
	39	#endif
	40
	41	#ifdef CONFIG_NAND_BOOT
	42	#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg
	43	#endif
	44
c7ca8b07 GQ	45	#ifdef CONFIG_SD_BOOT
	46	#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg
	47	#endif
	48
f3a8e2b7 MH	49	/*
	50	* NOR Flash Definitions
	51	*/
	52	#define CONFIG_SYS_NOR_CSPR_EXT (0x0)
	53	#define CONFIG_SYS_NOR_AMASK IFC_AMASK(12810241024)
	54	#define CONFIG_SYS_NOR_CSPR \
	55	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \| \
	56	CSPR_PORT_SIZE_16 \| \
	57	CSPR_MSEL_NOR \| \
	58	CSPR_V)
	59
	60	/* NOR Flash Timing Params */
	61	#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) \| \
	62	CSOR_NOR_TRHZ_80)
	63	#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) \| \
	64	FTIM0_NOR_TEADC(0x1) \| \
	65	FTIM0_NOR_TAVDS(0x0) \| \
	66	FTIM0_NOR_TEAHC(0xc))
	67	#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1c) \| \
	68	FTIM1_NOR_TRAD_NOR(0xb) \| \
	69	FTIM1_NOR_TSEQRAD_NOR(0x9))
	70	#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) \| \
	71	FTIM2_NOR_TCH(0x4) \| \
	72	FTIM2_NOR_TWPH(0x8) \| \
	73	FTIM2_NOR_TWP(0x10))
	74	#define CONFIG_SYS_NOR_FTIM3 0
	75	#define CONFIG_SYS_IFC_CCR 0x01000000
	76
	77	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
	78	#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
	79	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	80	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
	81
	82	#define CONFIG_SYS_FLASH_EMPTY_INFO
	83	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
	84
	85	#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
	86	#define CONFIG_SYS_WRITE_SWAPPED_DATA
	87
	88	/*
	89	* NAND Flash Definitions
	90	*/
	91	#define CONFIG_NAND_FSL_IFC
	92
	93	#define CONFIG_SYS_NAND_BASE 0x7e800000
	94	#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
	95
	96	#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
	97	#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
	98	\| CSPR_PORT_SIZE_8 \
	99	\| CSPR_MSEL_NAND \
	100	\| CSPR_V)
	101	#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
	102	#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
	103	\| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
	104	\| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
	105	\| CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
	106	\| CSOR_NAND_PGS_2K /* Page Size = 2K */ \
	107	\| CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
	108	\| CSOR_NAND_PB(64)) /* 64 Pages Per Block */
	109
	110	#define CONFIG_SYS_NAND_ONFI_DETECTION
	111
	112	#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) \| \
113	FTIM0_NAND_TWP(0x18) \| \
114	FTIM0_NAND_TWCHT(0x7) \| \
115	FTIM0_NAND_TWH(0xa))
116	#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) \| \
117	FTIM1_NAND_TWBE(0x39) \| \
118	FTIM1_NAND_TRR(0xe) \| \
119	FTIM1_NAND_TRP(0x18))
120	#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) \| \
121	FTIM2_NAND_TREH(0xa) \| \
122	FTIM2_NAND_TWHRE(0x1e))
123	#define CONFIG_SYS_NAND_FTIM3 0x0
124
125	#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
126	#define CONFIG_SYS_MAX_NAND_DEVICE 1
127	#define CONFIG_MTD_NAND_VERIFY_WRITE
128	#define CONFIG_CMD_NAND
129
130	#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
131
3ad44729 GQ	132	#ifdef CONFIG_NAND_BOOT
	133	#define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */
	134	#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
	135	#define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10)
	136	#endif
	137
f3a8e2b7 MH	138	/*
	139	* CPLD
	140	*/
	141	#define CONFIG_SYS_CPLD_BASE 0x7fb00000
	142	#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
	143
	144	#define CONFIG_SYS_CPLD_CSPR_EXT (0x0)
	145	#define CONFIG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) \| \
	146	CSPR_PORT_SIZE_8 \| \
	147	CSPR_MSEL_GPCM \| \
	148	CSPR_V)
	149	#define CONFIG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024)
	150	#define CONFIG_SYS_CPLD_CSOR (CSOR_NOR_ADM_SHIFT(4) \| \
	151	CSOR_NOR_NOR_MODE_AVD_NOR \| \
	152	CSOR_NOR_TRHZ_80)
	153
	154	/* CPLD Timing parameters for IFC GPCM */
	155	#define CONFIG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0xf) \| \
	156	FTIM0_GPCM_TEADC(0xf) \| \
	157	FTIM0_GPCM_TEAHC(0xf))
	158	#define CONFIG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) \| \
	159	FTIM1_GPCM_TRAD(0x3f))
	160	#define CONFIG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) \| \
	161	FTIM2_GPCM_TCH(0xf) \| \
	162	FTIM2_GPCM_TWP(0xff))
	163	#define CONFIG_SYS_CPLD_FTIM3 0x0
	164
	165	/* IFC Timing Params */
3ad44729 GQ	166	#ifdef CONFIG_NAND_BOOT
	167	#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
	168	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
	169	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
	170	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
	171	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
	172	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
	173	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
	174	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
	175
	176	#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT
	177	#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
	178	#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
	179	#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
	180	#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
	181	#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
	182	#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
	183	#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
	184	#else
f3a8e2b7 MH	185	#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
	186	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
	187	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
	188	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
	189	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
	190	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
	191	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
	192	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
	193
	194	#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
	195	#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
	196	#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
	197	#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
	198	#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
	199	#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
	200	#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
	201	#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
3ad44729	202	#endif
f3a8e2b7 MH	203
	204	#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT
	205	#define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR
	206	#define CONFIG_SYS_AMASK2 CONFIG_SYS_CPLD_AMASK
	207	#define CONFIG_SYS_CSOR2 CONFIG_SYS_CPLD_CSOR
	208	#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_CPLD_FTIM0
	209	#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_CPLD_FTIM1
	210	#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2
	211	#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3
	212
	213	/* EEPROM */
	214	#define CONFIG_ID_EEPROM
	215	#define CONFIG_SYS_I2C_EEPROM_NXID
	216	#define CONFIG_SYS_EEPROM_BUS_NUM 0
	217	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
	218	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	219	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
	220	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
	221
	222	/*
	223	* Environment
	224	*/
3ad44729 GQ	225	#define CONFIG_ENV_OVERWRITE
	226
	227	#if defined(CONFIG_NAND_BOOT)
	228	#define CONFIG_ENV_IS_IN_NAND
	229	#define CONFIG_ENV_SIZE 0x2000
	230	#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
c7ca8b07 GQ	231	#elif defined(CONFIG_SD_BOOT)
	232	#define CONFIG_ENV_OFFSET (1024 * 1024)
	233	#define CONFIG_ENV_IS_IN_MMC
	234	#define CONFIG_SYS_MMC_ENV_DEV 0
	235	#define CONFIG_ENV_SIZE 0x2000
3ad44729	236	#else
f3a8e2b7 MH	237	#define CONFIG_ENV_IS_IN_FLASH
	238	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000)
	239	#define CONFIG_ENV_SECT_SIZE 0x20000
	240	#define CONFIG_ENV_SIZE 0x20000
3ad44729	241	#endif
f3a8e2b7	242
e8297341 SX	243	/* FMan */
	244	#ifdef CONFIG_SYS_DPAA_FMAN
	245	#define CONFIG_FMAN_ENET
e8297341 SX	246	#define CONFIG_PHYLIB
	247	#define CONFIG_PHYLIB_10G
	248	#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
	249
	250	#define CONFIG_PHY_VITESSE
	251	#define CONFIG_PHY_REALTEK
	252	#define CONFIG_PHY_AQUANTIA
7942550a	253	#define AQR105_IRQ_MASK 0x40000000
e8297341 SX	254
	255	#define RGMII_PHY1_ADDR 0x1
	256	#define RGMII_PHY2_ADDR 0x2
	257
	258	#define QSGMII_PORT1_PHY_ADDR 0x4
	259	#define QSGMII_PORT2_PHY_ADDR 0x5
	260	#define QSGMII_PORT3_PHY_ADDR 0x6
	261	#define QSGMII_PORT4_PHY_ADDR 0x7
	262
	263	#define FM1_10GEC1_PHY_ADDR 0x1
	264
	265	#define CONFIG_ETHPRIME "FM1@DTSEC3"
	266	#endif
	267
d3e6d30c ZQ	268	/* QE */
	269	#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
	270	!defined(CONFIG_QSPI_BOOT)
	271	#define CONFIG_U_QE
	272	#endif
	273	#define CONFIG_SYS_QE_FW_ADDR 0x60600000
	274
70231009 GQ	275	/* USB */
	276	#define CONFIG_HAS_FSL_XHCI_USB
	277	#ifdef CONFIG_HAS_FSL_XHCI_USB
70231009	278	#define CONFIG_USB_XHCI_FSL
70231009 GQ	279	#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
70231009 GQ	280	#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
70231009 GQ	281	#endif
70231009 GQ	282
bc323b3f PL	283	/* SATA */
	284	#define CONFIG_LIBATA
	285	#define CONFIG_SCSI_AHCI
	286	#define CONFIG_CMD_SCSI
	287	#ifndef CONFIG_CMD_FAT
	288	#define CONFIG_CMD_FAT
	289	#endif
	290	#ifndef CONFIG_CMD_EXT2
	291	#define CONFIG_CMD_EXT2
	292	#endif
bc323b3f PL	293	#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2
	294	#define CONFIG_SYS_SCSI_MAX_LUN 2
	295	#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
	296	CONFIG_SYS_SCSI_MAX_LUN)
	297	#define SCSI_VEND_ID 0x1b4b
	298	#define SCSI_DEV_ID 0x9170
	299	#define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID}
bc323b3f	300
9711f528 AB	301	#include <asm/fsl_secure_boot.h>
9711f528 AB	302
f3a8e2b7	303	#endif /* __LS1043ARDB_H__ */