[people/ms/u-boot.git] / include / configs / ls1046ardb.h

/*
 * Copyright 2016 Freescale Semiconductor
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __LS1046ARDB_H__
#define __LS1046ARDB_H__

#include "ls1046a_common.h"

#ifdef CONFIG_SD_BOOT
#define CONFIG_SYS_TEXT_BASE		0x82000000
#else
#define CONFIG_SYS_TEXT_BASE		0x40100000
#endif

#define CONFIG_SYS_CLK_FREQ		100000000
#define CONFIG_DDR_CLK_FREQ		100000000

#define CONFIG_LAYERSCAPE_NS_ACCESS
#define CONFIG_MISC_INIT_R

#define CONFIG_DIMM_SLOTS_PER_CTLR	1
/* Physical Memory Map */
#define CONFIG_CHIP_SELECTS_PER_CTRL	4
#define CONFIG_NR_DRAM_BANKS		2

#define CONFIG_DDR_SPD
#define SPD_EEPROM_ADDRESS		0x51
#define CONFIG_SYS_SPD_BUS_NUM		0

#define CONFIG_DDR_ECC
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE           0xdeadbeef
#define CONFIG_FSL_DDR_BIST	/* enable built-in memory test */
#ifndef CONFIG_SPL
#define CONFIG_FSL_DDR_INTERACTIVE	/* Interactive debugging */
#endif

#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1046ardb/ls1046ardb_pbi.cfg
#endif

#ifdef CONFIG_SD_BOOT
#ifdef CONFIG_EMMC_BOOT
#define CONFIG_SYS_FSL_PBL_RCW \
	board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg
#else
#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg
#endif
#endif

#ifndef SPL_NO_IFC
/* IFC */
#define CONFIG_FSL_IFC
/*
 * NAND Flash Definitions
 */
#define CONFIG_NAND_FSL_IFC
#endif

#define CONFIG_SYS_NAND_BASE		0x7e800000
#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE

#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
				| CSPR_PORT_SIZE_8	\
				| CSPR_MSEL_NAND	\
				| CSPR_V)
#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)
#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
				| CSOR_NAND_ECC_MODE_8	/* 8-bit ECC */ \
				| CSOR_NAND_RAL_3	/* RAL = 3 Bytes */ \
				| CSOR_NAND_PGS_4K	/* Page Size = 4K */ \
				| CSOR_NAND_SPRZ_224	/* Spare size = 224 */ \
				| CSOR_NAND_PB(64))	/* 64 Pages Per Block */

#define CONFIG_SYS_NAND_ONFI_DETECTION

#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x7) | \
					FTIM0_NAND_TWP(0x18)   | \
					FTIM0_NAND_TWCHT(0x7) | \
					FTIM0_NAND_TWH(0xa))
#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
					FTIM1_NAND_TWBE(0x39)  | \
					FTIM1_NAND_TRR(0xe)   | \
					FTIM1_NAND_TRP(0x18))
#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0xf) | \
					FTIM2_NAND_TREH(0xa) | \
					FTIM2_NAND_TWHRE(0x1e))
#define CONFIG_SYS_NAND_FTIM3		0x0

#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_MTD_NAND_VERIFY_WRITE

#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)

/*
 * CPLD
 */
#define CONFIG_SYS_CPLD_BASE		0x7fb00000
#define CPLD_BASE_PHYS			CONFIG_SYS_CPLD_BASE

#define CONFIG_SYS_CPLD_CSPR_EXT	(0x0)
#define CONFIG_SYS_CPLD_CSPR		(CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
					CSPR_PORT_SIZE_8 | \
					CSPR_MSEL_GPCM | \
					CSPR_V)
#define CONFIG_SYS_CPLD_AMASK		IFC_AMASK(64 * 1024)
#define CONFIG_SYS_CPLD_CSOR		CSOR_NOR_ADM_SHIFT(16)

/* CPLD Timing parameters for IFC GPCM */
#define CONFIG_SYS_CPLD_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
					FTIM0_GPCM_TEADC(0x0e) | \
					FTIM0_GPCM_TEAHC(0x0e))
#define CONFIG_SYS_CPLD_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
					FTIM1_GPCM_TRAD(0x3f))
#define CONFIG_SYS_CPLD_FTIM2		(FTIM2_GPCM_TCS(0xf) | \
					FTIM2_GPCM_TCH(0xf) | \
					FTIM2_GPCM_TWP(0x3E))
#define CONFIG_SYS_CPLD_FTIM3		0x0

/* IFC Timing Params */
#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3

#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_CPLD_CSPR_EXT
#define CONFIG_SYS_CSPR2		CONFIG_SYS_CPLD_CSPR
#define CONFIG_SYS_AMASK2		CONFIG_SYS_CPLD_AMASK
#define CONFIG_SYS_CSOR2		CONFIG_SYS_CPLD_CSOR
#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_CPLD_FTIM0
#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_CPLD_FTIM1
#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_CPLD_FTIM2
#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_CPLD_FTIM3

/* EEPROM */
#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM		0
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x53
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
#define I2C_RETIMER_ADDR			0x18

/* PMIC */
#define CONFIG_POWER
#ifdef CONFIG_POWER
#define CONFIG_POWER_I2C
#endif

/*
 * Environment
 */
#ifndef SPL_NO_ENV
#define CONFIG_ENV_OVERWRITE
#endif

#if defined(CONFIG_SD_BOOT)
#define CONFIG_SYS_MMC_ENV_DEV		0
#define CONFIG_ENV_OFFSET		(3 * 1024 * 1024)
#define CONFIG_ENV_SIZE			0x2000
#else
#define CONFIG_ENV_SIZE			0x2000		/* 8KB */
#define CONFIG_ENV_OFFSET		0x300000	/* 3MB */
#define CONFIG_ENV_SECT_SIZE		0x40000		/* 256KB */
#endif

#define AQR105_IRQ_MASK			0x80000000
/* FMan */
#ifndef SPL_NO_FMAN

#ifdef CONFIG_NET
#define CONFIG_PHY_REALTEK
#endif

#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_FMAN_ENET
#define CONFIG_PHY_AQUANTIA
#define CONFIG_PHYLIB_10G
#define RGMII_PHY1_ADDR			0x1
#define RGMII_PHY2_ADDR			0x2

#define SGMII_PHY1_ADDR			0x3
#define SGMII_PHY2_ADDR			0x4

#define FM1_10GEC1_PHY_ADDR		0x0

#define FDT_SEQ_MACADDR_FROM_ENV

#define CONFIG_ETHPRIME			"FM1@DTSEC3"
#endif

#endif

/* QSPI device */
#ifndef SPL_NO_QSPI
#ifdef CONFIG_FSL_QSPI
#define CONFIG_SPI_FLASH_SPANSION
#define FSL_QSPI_FLASH_SIZE		(1 << 26)
#define FSL_QSPI_FLASH_NUM		2
#endif
#endif

#ifndef SPL_NO_MISC
#undef CONFIG_BOOTCOMMAND
#if defined(CONFIG_QSPI_BOOT)
#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "	\
			   "env exists secureboot && esbc_halt;;"
#elif defined(CONFIG_SD_BOOT)
#define CONFIG_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; "	\
			   "env exists secureboot && esbc_halt;"
#endif
#endif

#include <asm/fsl_secure_boot.h>

#endif /* __LS1046ARDB_H__ */
Commit	Line	Data
dd02936f MH	1	/*
	2	* Copyright 2016 Freescale Semiconductor
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#ifndef __LS1046ARDB_H__
	8	#define __LS1046ARDB_H__
	9
	10	#include "ls1046a_common.h"
	11
dd02936f MH	12	#ifdef CONFIG_SD_BOOT
	13	#define CONFIG_SYS_TEXT_BASE 0x82000000
	14	#else
	15	#define CONFIG_SYS_TEXT_BASE 0x40100000
	16	#endif
	17
	18	#define CONFIG_SYS_CLK_FREQ 100000000
	19	#define CONFIG_DDR_CLK_FREQ 100000000
	20
	21	#define CONFIG_LAYERSCAPE_NS_ACCESS
	22	#define CONFIG_MISC_INIT_R
	23
	24	#define CONFIG_DIMM_SLOTS_PER_CTLR 1
	25	/* Physical Memory Map */
	26	#define CONFIG_CHIP_SELECTS_PER_CTRL 4
	27	#define CONFIG_NR_DRAM_BANKS 2
	28
	29	#define CONFIG_DDR_SPD
	30	#define SPD_EEPROM_ADDRESS 0x51
	31	#define CONFIG_SYS_SPD_BUS_NUM 0
	32
	33	#define CONFIG_DDR_ECC
	34	#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
	35	#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
	36	#define CONFIG_FSL_DDR_BIST /* enable built-in memory test */
dc760aed	37	#ifndef CONFIG_SPL
dd02936f	38	#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
dc760aed	39	#endif
dd02936f MH	40
	41	#ifdef CONFIG_RAMBOOT_PBL
	42	#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1046ardb/ls1046ardb_pbi.cfg
	43	#endif
	44
	45	#ifdef CONFIG_SD_BOOT
	46	#ifdef CONFIG_EMMC_BOOT
	47	#define CONFIG_SYS_FSL_PBL_RCW \
	48	board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg
	49	#else
	50	#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg
	51	#endif
	52	#endif
	53
a52ff334	54	#ifndef SPL_NO_IFC
dd02936f MH	55	/* IFC */
dd02936f MH	56	#define CONFIG_FSL_IFC
dd02936f MH	57	/*
	58	* NAND Flash Definitions
	59	*/
	60	#define CONFIG_NAND_FSL_IFC
a52ff334	61	#endif
dd02936f MH	62
	63	#define CONFIG_SYS_NAND_BASE 0x7e800000
	64	#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
	65
	66	#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
	67	#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
	68	\| CSPR_PORT_SIZE_8 \
	69	\| CSPR_MSEL_NAND \
	70	\| CSPR_V)
	71	#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
	72	#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
	73	\| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
	74	\| CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \
	75	\| CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
	76	\| CSOR_NAND_PGS_4K /* Page Size = 4K */ \
	77	\| CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
	78	\| CSOR_NAND_PB(64)) /* 64 Pages Per Block */
	79
	80	#define CONFIG_SYS_NAND_ONFI_DETECTION
	81
	82	#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) \| \
	83	FTIM0_NAND_TWP(0x18) \| \
	84	FTIM0_NAND_TWCHT(0x7) \| \
	85	FTIM0_NAND_TWH(0xa))
	86	#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) \| \
	87	FTIM1_NAND_TWBE(0x39) \| \
	88	FTIM1_NAND_TRR(0xe) \| \
	89	FTIM1_NAND_TRP(0x18))
	90	#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) \| \
	91	FTIM2_NAND_TREH(0xa) \| \
	92	FTIM2_NAND_TWHRE(0x1e))
	93	#define CONFIG_SYS_NAND_FTIM3 0x0
	94
	95	#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
	96	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	97	#define CONFIG_MTD_NAND_VERIFY_WRITE
dd02936f MH	98
	99	#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
	100
	101	/*
	102	* CPLD
	103	*/
	104	#define CONFIG_SYS_CPLD_BASE 0x7fb00000
	105	#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
	106
	107	#define CONFIG_SYS_CPLD_CSPR_EXT (0x0)
	108	#define CONFIG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) \| \
	109	CSPR_PORT_SIZE_8 \| \
	110	CSPR_MSEL_GPCM \| \
	111	CSPR_V)
	112	#define CONFIG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024)
	113	#define CONFIG_SYS_CPLD_CSOR CSOR_NOR_ADM_SHIFT(16)
	114
	115	/* CPLD Timing parameters for IFC GPCM */
	116	#define CONFIG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0x0e) \| \
	117	FTIM0_GPCM_TEADC(0x0e) \| \
	118	FTIM0_GPCM_TEAHC(0x0e))
	119	#define CONFIG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) \| \
	120	FTIM1_GPCM_TRAD(0x3f))
	121	#define CONFIG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) \| \
	122	FTIM2_GPCM_TCH(0xf) \| \
	123	FTIM2_GPCM_TWP(0x3E))
	124	#define CONFIG_SYS_CPLD_FTIM3 0x0
	125
	126	/* IFC Timing Params */
	127	#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
	128	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
	129	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
	130	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
	131	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
	132	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
	133	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
	134	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
	135
	136	#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT
	137	#define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR
	138	#define CONFIG_SYS_AMASK2 CONFIG_SYS_CPLD_AMASK
	139	#define CONFIG_SYS_CSOR2 CONFIG_SYS_CPLD_CSOR
	140	#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_CPLD_FTIM0
	141	#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_CPLD_FTIM1
	142	#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2
	143	#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3
	144
	145	/* EEPROM */
	146	#define CONFIG_ID_EEPROM
	147	#define CONFIG_SYS_I2C_EEPROM_NXID
	148	#define CONFIG_SYS_EEPROM_BUS_NUM 0
	149	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
	150	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	151	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
	152	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
	153	#define I2C_RETIMER_ADDR 0x18
	154
dccef2ec HZ	155	/* PMIC */
	156	#define CONFIG_POWER
	157	#ifdef CONFIG_POWER
	158	#define CONFIG_POWER_I2C
	159	#endif
	160
dd02936f MH	161	/*
	162	* Environment
	163	*/
a52ff334	164	#ifndef SPL_NO_ENV
dd02936f	165	#define CONFIG_ENV_OVERWRITE
a52ff334	166	#endif
dd02936f MH	167
dd02936f MH	168	#if defined(CONFIG_SD_BOOT)
dd02936f	169	#define CONFIG_SYS_MMC_ENV_DEV 0
8104deb2	170	#define CONFIG_ENV_OFFSET (3 * 1024 * 1024)
dd02936f MH	171	#define CONFIG_ENV_SIZE 0x2000
dd02936f MH	172	#else
dd02936f	173	#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
8104deb2	174	#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
dd02936f MH	175	#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256KB */
	176	#endif
	177
99b47c25	178	#define AQR105_IRQ_MASK 0x80000000
dd02936f	179	/* FMan */
a52ff334	180	#ifndef SPL_NO_FMAN
99b47c25 YS	181
99b47c25 YS	182	#ifdef CONFIG_NET
dd02936f	183	#define CONFIG_PHY_REALTEK
99b47c25	184	#endif
dd02936f	185
99b47c25 YS	186	#ifdef CONFIG_SYS_DPAA_FMAN
	187	#define CONFIG_FMAN_ENET
	188	#define CONFIG_PHY_AQUANTIA
	189	#define CONFIG_PHYLIB_10G
dd02936f MH	190	#define RGMII_PHY1_ADDR 0x1
	191	#define RGMII_PHY2_ADDR 0x2
	192
	193	#define SGMII_PHY1_ADDR 0x3
	194	#define SGMII_PHY2_ADDR 0x4
	195
	196	#define FM1_10GEC1_PHY_ADDR 0x0
	197
4ace3040 PK	198	#define FDT_SEQ_MACADDR_FROM_ENV
4ace3040 PK	199
dd02936f MH	200	#define CONFIG_ETHPRIME "FM1@DTSEC3"
dd02936f MH	201	#endif
99b47c25	202
a52ff334	203	#endif
dd02936f MH	204
dd02936f MH	205	/* QSPI device */
a52ff334	206	#ifndef SPL_NO_QSPI
dd02936f MH	207	#ifdef CONFIG_FSL_QSPI
	208	#define CONFIG_SPI_FLASH_SPANSION
	209	#define FSL_QSPI_FLASH_SIZE (1 << 26)
	210	#define FSL_QSPI_FLASH_NUM 2
dd02936f	211	#endif
a52ff334	212	#endif
dd02936f	213
a52ff334	214	#ifndef SPL_NO_MISC
8de227ee	215	#undef CONFIG_BOOTCOMMAND
aab2ef9a	216	#if defined(CONFIG_QSPI_BOOT)
9b457cc6 VPB	217	#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
9b457cc6 VPB	218	"env exists secureboot && esbc_halt;;"
aab2ef9a	219	#elif defined(CONFIG_SD_BOOT)
9b457cc6 VPB	220	#define CONFIG_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; " \
9b457cc6 VPB	221	"env exists secureboot && esbc_halt;"
aab2ef9a	222	#endif
a52ff334	223	#endif
dd02936f	224
f7244f2c VPB	225	#include <asm/fsl_secure_boot.h>
f7244f2c VPB	226
dd02936f	227	#endif /* __LS1046ARDB_H__ */