[people/ms/u-boot.git] / include / configs / ls1046ardb.h

/*
 * Copyright 2016 Freescale Semiconductor
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __LS1046ARDB_H__
#define __LS1046ARDB_H__

#include "ls1046a_common.h"

#define CONFIG_SYS_CLK_FREQ		100000000
#define CONFIG_DDR_CLK_FREQ		100000000

#define CONFIG_LAYERSCAPE_NS_ACCESS
#define CONFIG_MISC_INIT_R

#define CONFIG_DIMM_SLOTS_PER_CTLR	1
/* Physical Memory Map */
#define CONFIG_CHIP_SELECTS_PER_CTRL	4
#define CONFIG_NR_DRAM_BANKS		2

#define CONFIG_DDR_SPD
#define SPD_EEPROM_ADDRESS		0x51
#define CONFIG_SYS_SPD_BUS_NUM		0

#define CONFIG_DDR_ECC
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE           0xdeadbeef
#define CONFIG_FSL_DDR_BIST	/* enable built-in memory test */
#ifndef CONFIG_SPL
#define CONFIG_FSL_DDR_INTERACTIVE	/* Interactive debugging */
#endif

#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1046ardb/ls1046ardb_pbi.cfg
#endif

#ifdef CONFIG_SD_BOOT
#ifdef CONFIG_EMMC_BOOT
#define CONFIG_SYS_FSL_PBL_RCW \
	board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg
#else
#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg
#endif
#endif

#ifndef SPL_NO_IFC
/* IFC */
#define CONFIG_FSL_IFC
/*
 * NAND Flash Definitions
 */
#define CONFIG_NAND_FSL_IFC
#endif

#define CONFIG_SYS_NAND_BASE		0x7e800000
#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE

#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
				| CSPR_PORT_SIZE_8	\
				| CSPR_MSEL_NAND	\
				| CSPR_V)
#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)
#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
				| CSOR_NAND_ECC_MODE_8	/* 8-bit ECC */ \
				| CSOR_NAND_RAL_3	/* RAL = 3 Bytes */ \
				| CSOR_NAND_PGS_4K	/* Page Size = 4K */ \
				| CSOR_NAND_SPRZ_224	/* Spare size = 224 */ \
				| CSOR_NAND_PB(64))	/* 64 Pages Per Block */

#define CONFIG_SYS_NAND_ONFI_DETECTION

#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x7) | \
					FTIM0_NAND_TWP(0x18)   | \
					FTIM0_NAND_TWCHT(0x7) | \
					FTIM0_NAND_TWH(0xa))
#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
					FTIM1_NAND_TWBE(0x39)  | \
					FTIM1_NAND_TRR(0xe)   | \
					FTIM1_NAND_TRP(0x18))
#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0xf) | \
					FTIM2_NAND_TREH(0xa) | \
					FTIM2_NAND_TWHRE(0x1e))
#define CONFIG_SYS_NAND_FTIM3		0x0

#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_MTD_NAND_VERIFY_WRITE

#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)

/*
 * CPLD
 */
#define CONFIG_SYS_CPLD_BASE		0x7fb00000
#define CPLD_BASE_PHYS			CONFIG_SYS_CPLD_BASE

#define CONFIG_SYS_CPLD_CSPR_EXT	(0x0)
#define CONFIG_SYS_CPLD_CSPR		(CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
					CSPR_PORT_SIZE_8 | \
					CSPR_MSEL_GPCM | \
					CSPR_V)
#define CONFIG_SYS_CPLD_AMASK		IFC_AMASK(64 * 1024)
#define CONFIG_SYS_CPLD_CSOR		CSOR_NOR_ADM_SHIFT(16)

/* CPLD Timing parameters for IFC GPCM */
#define CONFIG_SYS_CPLD_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
					FTIM0_GPCM_TEADC(0x0e) | \
					FTIM0_GPCM_TEAHC(0x0e))
#define CONFIG_SYS_CPLD_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
					FTIM1_GPCM_TRAD(0x3f))
#define CONFIG_SYS_CPLD_FTIM2		(FTIM2_GPCM_TCS(0xf) | \
					FTIM2_GPCM_TCH(0xf) | \
					FTIM2_GPCM_TWP(0x3E))
#define CONFIG_SYS_CPLD_FTIM3		0x0

/* IFC Timing Params */
#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3

#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_CPLD_CSPR_EXT
#define CONFIG_SYS_CSPR2		CONFIG_SYS_CPLD_CSPR
#define CONFIG_SYS_AMASK2		CONFIG_SYS_CPLD_AMASK
#define CONFIG_SYS_CSOR2		CONFIG_SYS_CPLD_CSOR
#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_CPLD_FTIM0
#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_CPLD_FTIM1
#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_CPLD_FTIM2
#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_CPLD_FTIM3

/* EEPROM */
#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM		0
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x53
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
#define I2C_RETIMER_ADDR			0x18

/* PMIC */
#define CONFIG_POWER
#ifdef CONFIG_POWER
#define CONFIG_POWER_I2C
#endif

/*
 * Environment
 */
#ifndef SPL_NO_ENV
#define CONFIG_ENV_OVERWRITE
#endif

#if defined(CONFIG_SD_BOOT)
#define CONFIG_SYS_MMC_ENV_DEV		0
#define CONFIG_ENV_OFFSET		(3 * 1024 * 1024)
#define CONFIG_ENV_SIZE			0x2000
#else
#define CONFIG_ENV_SIZE			0x2000		/* 8KB */
#define CONFIG_ENV_OFFSET		0x300000	/* 3MB */
#define CONFIG_ENV_SECT_SIZE		0x40000		/* 256KB */
#endif

#define AQR105_IRQ_MASK			0x80000000
/* FMan */
#ifndef SPL_NO_FMAN

#ifdef CONFIG_NET
#define CONFIG_PHY_REALTEK
#endif

#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_FMAN_ENET
#define CONFIG_PHY_AQUANTIA
#define CONFIG_PHYLIB_10G
#define RGMII_PHY1_ADDR			0x1
#define RGMII_PHY2_ADDR			0x2

#define SGMII_PHY1_ADDR			0x3
#define SGMII_PHY2_ADDR			0x4

#define FM1_10GEC1_PHY_ADDR		0x0

#define FDT_SEQ_MACADDR_FROM_ENV

#define CONFIG_ETHPRIME			"FM1@DTSEC3"
#endif

#endif

/* QSPI device */
#ifndef SPL_NO_QSPI
#ifdef CONFIG_FSL_QSPI
#define CONFIG_SPI_FLASH_SPANSION
#define FSL_QSPI_FLASH_SIZE		(1 << 26)
#define FSL_QSPI_FLASH_NUM		2
#endif
#endif

#ifndef SPL_NO_MISC
#undef CONFIG_BOOTCOMMAND
#if defined(CONFIG_QSPI_BOOT)
#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "	\
			   "env exists secureboot && esbc_halt;;"
#elif defined(CONFIG_SD_BOOT)
#define CONFIG_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; "	\
			   "env exists secureboot && esbc_halt;"
#endif
#endif

#include <asm/fsl_secure_boot.h>

#endif /* __LS1046ARDB_H__ */
Commit	Line	Data
dd02936f MH	1	/*
	2	* Copyright 2016 Freescale Semiconductor
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#ifndef __LS1046ARDB_H__
	8	#define __LS1046ARDB_H__
	9
	10	#include "ls1046a_common.h"
	11
dd02936f MH	12	#define CONFIG_SYS_CLK_FREQ 100000000
	13	#define CONFIG_DDR_CLK_FREQ 100000000
	14
	15	#define CONFIG_LAYERSCAPE_NS_ACCESS
	16	#define CONFIG_MISC_INIT_R
	17
	18	#define CONFIG_DIMM_SLOTS_PER_CTLR 1
	19	/* Physical Memory Map */
	20	#define CONFIG_CHIP_SELECTS_PER_CTRL 4
	21	#define CONFIG_NR_DRAM_BANKS 2
	22
	23	#define CONFIG_DDR_SPD
	24	#define SPD_EEPROM_ADDRESS 0x51
	25	#define CONFIG_SYS_SPD_BUS_NUM 0
	26
	27	#define CONFIG_DDR_ECC
	28	#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
	29	#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
	30	#define CONFIG_FSL_DDR_BIST /* enable built-in memory test */
dc760aed	31	#ifndef CONFIG_SPL
dd02936f	32	#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
dc760aed	33	#endif
dd02936f MH	34
	35	#ifdef CONFIG_RAMBOOT_PBL
	36	#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1046ardb/ls1046ardb_pbi.cfg
	37	#endif
	38
	39	#ifdef CONFIG_SD_BOOT
	40	#ifdef CONFIG_EMMC_BOOT
	41	#define CONFIG_SYS_FSL_PBL_RCW \
	42	board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg
	43	#else
	44	#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg
	45	#endif
	46	#endif
	47
a52ff334	48	#ifndef SPL_NO_IFC
dd02936f MH	49	/* IFC */
dd02936f MH	50	#define CONFIG_FSL_IFC
dd02936f MH	51	/*
	52	* NAND Flash Definitions
	53	*/
	54	#define CONFIG_NAND_FSL_IFC
a52ff334	55	#endif
dd02936f MH	56
	57	#define CONFIG_SYS_NAND_BASE 0x7e800000
	58	#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
	59
	60	#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
	61	#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
	62	\| CSPR_PORT_SIZE_8 \
	63	\| CSPR_MSEL_NAND \
	64	\| CSPR_V)
	65	#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
	66	#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
	67	\| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
	68	\| CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \
	69	\| CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
	70	\| CSOR_NAND_PGS_4K /* Page Size = 4K */ \
	71	\| CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
	72	\| CSOR_NAND_PB(64)) /* 64 Pages Per Block */
	73
	74	#define CONFIG_SYS_NAND_ONFI_DETECTION
	75
	76	#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) \| \
	77	FTIM0_NAND_TWP(0x18) \| \
	78	FTIM0_NAND_TWCHT(0x7) \| \
	79	FTIM0_NAND_TWH(0xa))
	80	#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) \| \
	81	FTIM1_NAND_TWBE(0x39) \| \
	82	FTIM1_NAND_TRR(0xe) \| \
	83	FTIM1_NAND_TRP(0x18))
	84	#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) \| \
	85	FTIM2_NAND_TREH(0xa) \| \
	86	FTIM2_NAND_TWHRE(0x1e))
	87	#define CONFIG_SYS_NAND_FTIM3 0x0
	88
	89	#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
	90	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	91	#define CONFIG_MTD_NAND_VERIFY_WRITE
dd02936f MH	92
	93	#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
	94
	95	/*
	96	* CPLD
	97	*/
	98	#define CONFIG_SYS_CPLD_BASE 0x7fb00000
	99	#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
	100
	101	#define CONFIG_SYS_CPLD_CSPR_EXT (0x0)
	102	#define CONFIG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) \| \
	103	CSPR_PORT_SIZE_8 \| \
	104	CSPR_MSEL_GPCM \| \
	105	CSPR_V)
	106	#define CONFIG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024)
	107	#define CONFIG_SYS_CPLD_CSOR CSOR_NOR_ADM_SHIFT(16)
	108
	109	/* CPLD Timing parameters for IFC GPCM */
	110	#define CONFIG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0x0e) \| \
	111	FTIM0_GPCM_TEADC(0x0e) \| \
	112	FTIM0_GPCM_TEAHC(0x0e))
	113	#define CONFIG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) \| \
	114	FTIM1_GPCM_TRAD(0x3f))
	115	#define CONFIG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) \| \
	116	FTIM2_GPCM_TCH(0xf) \| \
	117	FTIM2_GPCM_TWP(0x3E))
	118	#define CONFIG_SYS_CPLD_FTIM3 0x0
	119
	120	/* IFC Timing Params */
	121	#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
	122	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
	123	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
	124	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
	125	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
	126	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
	127	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
	128	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
	129
	130	#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT
	131	#define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR
	132	#define CONFIG_SYS_AMASK2 CONFIG_SYS_CPLD_AMASK
	133	#define CONFIG_SYS_CSOR2 CONFIG_SYS_CPLD_CSOR
	134	#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_CPLD_FTIM0
	135	#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_CPLD_FTIM1
	136	#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2
	137	#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3
	138
	139	/* EEPROM */
	140	#define CONFIG_ID_EEPROM
	141	#define CONFIG_SYS_I2C_EEPROM_NXID
	142	#define CONFIG_SYS_EEPROM_BUS_NUM 0
	143	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
	144	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	145	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
	146	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
	147	#define I2C_RETIMER_ADDR 0x18
	148
dccef2ec HZ	149	/* PMIC */
	150	#define CONFIG_POWER
	151	#ifdef CONFIG_POWER
	152	#define CONFIG_POWER_I2C
	153	#endif
	154
dd02936f MH	155	/*
	156	* Environment
	157	*/
a52ff334	158	#ifndef SPL_NO_ENV
dd02936f	159	#define CONFIG_ENV_OVERWRITE
a52ff334	160	#endif
dd02936f MH	161
dd02936f MH	162	#if defined(CONFIG_SD_BOOT)
dd02936f	163	#define CONFIG_SYS_MMC_ENV_DEV 0
8104deb2	164	#define CONFIG_ENV_OFFSET (3 * 1024 * 1024)
dd02936f MH	165	#define CONFIG_ENV_SIZE 0x2000
dd02936f MH	166	#else
dd02936f	167	#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
8104deb2	168	#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
dd02936f MH	169	#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256KB */
	170	#endif
	171
99b47c25	172	#define AQR105_IRQ_MASK 0x80000000
dd02936f	173	/* FMan */
a52ff334	174	#ifndef SPL_NO_FMAN
99b47c25 YS	175
99b47c25 YS	176	#ifdef CONFIG_NET
dd02936f	177	#define CONFIG_PHY_REALTEK
99b47c25	178	#endif
dd02936f	179
99b47c25 YS	180	#ifdef CONFIG_SYS_DPAA_FMAN
	181	#define CONFIG_FMAN_ENET
	182	#define CONFIG_PHY_AQUANTIA
	183	#define CONFIG_PHYLIB_10G
dd02936f MH	184	#define RGMII_PHY1_ADDR 0x1
	185	#define RGMII_PHY2_ADDR 0x2
	186
	187	#define SGMII_PHY1_ADDR 0x3
	188	#define SGMII_PHY2_ADDR 0x4
	189
	190	#define FM1_10GEC1_PHY_ADDR 0x0
	191
4ace3040 PK	192	#define FDT_SEQ_MACADDR_FROM_ENV
4ace3040 PK	193
dd02936f MH	194	#define CONFIG_ETHPRIME "FM1@DTSEC3"
dd02936f MH	195	#endif
99b47c25	196
a52ff334	197	#endif
dd02936f MH	198
dd02936f MH	199	/* QSPI device */
a52ff334	200	#ifndef SPL_NO_QSPI
dd02936f MH	201	#ifdef CONFIG_FSL_QSPI
	202	#define CONFIG_SPI_FLASH_SPANSION
	203	#define FSL_QSPI_FLASH_SIZE (1 << 26)
	204	#define FSL_QSPI_FLASH_NUM 2
dd02936f	205	#endif
a52ff334	206	#endif
dd02936f	207
a52ff334	208	#ifndef SPL_NO_MISC
8de227ee	209	#undef CONFIG_BOOTCOMMAND
aab2ef9a	210	#if defined(CONFIG_QSPI_BOOT)
9b457cc6 VPB	211	#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
9b457cc6 VPB	212	"env exists secureboot && esbc_halt;;"
aab2ef9a	213	#elif defined(CONFIG_SD_BOOT)
9b457cc6 VPB	214	#define CONFIG_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; " \
9b457cc6 VPB	215	"env exists secureboot && esbc_halt;"
aab2ef9a	216	#endif
a52ff334	217	#endif
dd02936f	218
f7244f2c VPB	219	#include <asm/fsl_secure_boot.h>
f7244f2c VPB	220
dd02936f	221	#endif /* __LS1046ARDB_H__ */