[people/ms/u-boot.git] / include / configs / ls1046ardb.h

/*
 * Copyright 2016 Freescale Semiconductor
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __LS1046ARDB_H__
#define __LS1046ARDB_H__

#include "ls1046a_common.h"

#ifdef CONFIG_SD_BOOT
#define CONFIG_SYS_TEXT_BASE		0x82000000
#else
#define CONFIG_SYS_TEXT_BASE		0x40100000
#endif

#define CONFIG_SYS_CLK_FREQ		100000000
#define CONFIG_DDR_CLK_FREQ		100000000

#define CONFIG_LAYERSCAPE_NS_ACCESS
#define CONFIG_MISC_INIT_R

#define CONFIG_DIMM_SLOTS_PER_CTLR	1
/* Physical Memory Map */
#define CONFIG_CHIP_SELECTS_PER_CTRL	4
#define CONFIG_NR_DRAM_BANKS		2

#define CONFIG_DDR_SPD
#define SPD_EEPROM_ADDRESS		0x51
#define CONFIG_SYS_SPD_BUS_NUM		0

#define CONFIG_DDR_ECC
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE           0xdeadbeef
#define CONFIG_FSL_DDR_BIST	/* enable built-in memory test */
#define CONFIG_FSL_DDR_INTERACTIVE	/* Interactive debugging */

#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1046ardb/ls1046ardb_pbi.cfg
#endif

#ifdef CONFIG_SD_BOOT
#ifdef CONFIG_EMMC_BOOT
#define CONFIG_SYS_FSL_PBL_RCW \
	board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg
#else
#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg
#endif
#endif

/* IFC */
#define CONFIG_FSL_IFC

/*
 * NAND Flash Definitions
 */
#define CONFIG_NAND_FSL_IFC

#define CONFIG_SYS_NAND_BASE		0x7e800000
#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE

#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
				| CSPR_PORT_SIZE_8	\
				| CSPR_MSEL_NAND	\
				| CSPR_V)
#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)
#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
				| CSOR_NAND_ECC_MODE_8	/* 8-bit ECC */ \
				| CSOR_NAND_RAL_3	/* RAL = 3 Bytes */ \
				| CSOR_NAND_PGS_4K	/* Page Size = 4K */ \
				| CSOR_NAND_SPRZ_224	/* Spare size = 224 */ \
				| CSOR_NAND_PB(64))	/* 64 Pages Per Block */

#define CONFIG_SYS_NAND_ONFI_DETECTION

#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x7) | \
					FTIM0_NAND_TWP(0x18)   | \
					FTIM0_NAND_TWCHT(0x7) | \
					FTIM0_NAND_TWH(0xa))
#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
					FTIM1_NAND_TWBE(0x39)  | \
					FTIM1_NAND_TRR(0xe)   | \
					FTIM1_NAND_TRP(0x18))
#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0xf) | \
					FTIM2_NAND_TREH(0xa) | \
					FTIM2_NAND_TWHRE(0x1e))
#define CONFIG_SYS_NAND_FTIM3		0x0

#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND

#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)

/*
 * CPLD
 */
#define CONFIG_SYS_CPLD_BASE		0x7fb00000
#define CPLD_BASE_PHYS			CONFIG_SYS_CPLD_BASE

#define CONFIG_SYS_CPLD_CSPR_EXT	(0x0)
#define CONFIG_SYS_CPLD_CSPR		(CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
					CSPR_PORT_SIZE_8 | \
					CSPR_MSEL_GPCM | \
					CSPR_V)
#define CONFIG_SYS_CPLD_AMASK		IFC_AMASK(64 * 1024)
#define CONFIG_SYS_CPLD_CSOR		CSOR_NOR_ADM_SHIFT(16)

/* CPLD Timing parameters for IFC GPCM */
#define CONFIG_SYS_CPLD_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
					FTIM0_GPCM_TEADC(0x0e) | \
					FTIM0_GPCM_TEAHC(0x0e))
#define CONFIG_SYS_CPLD_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
					FTIM1_GPCM_TRAD(0x3f))
#define CONFIG_SYS_CPLD_FTIM2		(FTIM2_GPCM_TCS(0xf) | \
					FTIM2_GPCM_TCH(0xf) | \
					FTIM2_GPCM_TWP(0x3E))
#define CONFIG_SYS_CPLD_FTIM3		0x0

/* IFC Timing Params */
#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3

#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_CPLD_CSPR_EXT
#define CONFIG_SYS_CSPR2		CONFIG_SYS_CPLD_CSPR
#define CONFIG_SYS_AMASK2		CONFIG_SYS_CPLD_AMASK
#define CONFIG_SYS_CSOR2		CONFIG_SYS_CPLD_CSOR
#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_CPLD_FTIM0
#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_CPLD_FTIM1
#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_CPLD_FTIM2
#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_CPLD_FTIM3

/* EEPROM */
#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM		0
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x53
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
#define I2C_RETIMER_ADDR			0x18

/* PMIC */
#define CONFIG_POWER
#ifdef CONFIG_POWER
#define CONFIG_POWER_I2C
#endif

/*
 * Environment
 */
#define CONFIG_ENV_OVERWRITE

#if defined(CONFIG_SD_BOOT)
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV		0
#define CONFIG_ENV_OFFSET		(1024 * 1024)
#define CONFIG_ENV_SIZE			0x2000
#else
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SIZE			0x2000		/* 8KB */
#define CONFIG_ENV_OFFSET		0x200000	/* 2MB */
#define CONFIG_ENV_SECT_SIZE		0x40000		/* 256KB */
#endif

/* FMan */
#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_FMAN_ENET
#define CONFIG_PHYLIB
#define CONFIG_PHYLIB_10G
#define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */

#define CONFIG_PHY_REALTEK
#define CONFIG_PHY_AQUANTIA
#define AQR105_IRQ_MASK			0x80000000

#define RGMII_PHY1_ADDR			0x1
#define RGMII_PHY2_ADDR			0x2

#define SGMII_PHY1_ADDR			0x3
#define SGMII_PHY2_ADDR			0x4

#define FM1_10GEC1_PHY_ADDR		0x0

#define CONFIG_ETHPRIME			"FM1@DTSEC3"
#endif

/* QSPI device */
#ifdef CONFIG_FSL_QSPI
#define CONFIG_SPI_FLASH_SPANSION
#define FSL_QSPI_FLASH_SIZE		(1 << 26)
#define FSL_QSPI_FLASH_NUM		2
#define CONFIG_SPI_FLASH_BAR
#endif

/* USB */
#define CONFIG_HAS_FSL_XHCI_USB
#ifdef CONFIG_HAS_FSL_XHCI_USB
#define CONFIG_USB_XHCI_HCD
#define CONFIG_USB_XHCI_FSL
#define CONFIG_USB_XHCI_DWC3
#define CONFIG_USB_MAX_CONTROLLER_COUNT         3
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS      2
#define CONFIG_CMD_USB
#define CONFIG_USB_STORAGE
#endif

/* SATA */
#define CONFIG_LIBATA
#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SCSI

#define CONFIG_SYS_SATA				AHCI_BASE_ADDR

#define CONFIG_SYS_SCSI_MAX_SCSI_ID		1
#define CONFIG_SYS_SCSI_MAX_LUN			1
#define CONFIG_SYS_SCSI_MAX_DEVICE		(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
						CONFIG_SYS_SCSI_MAX_LUN)

#define CONFIG_BOOTCOMMAND		"sf probe 0:0;sf read $kernel_load" \
					"$kernel_start $kernel_size;" \
					"bootm $kernel_load"

#define MTDPARTS_DEFAULT "mtdparts=1550000.quadspi:1m(rcw)," \
			"15m(u-boot),48m(kernel.itb);" \
			"7e800000.flash:16m(nand_uboot)," \
			"48m(nand_kernel),448m(nand_free)"

#endif /* __LS1046ARDB_H__ */
Commit	Line	Data
dd02936f MH	1	/*
	2	* Copyright 2016 Freescale Semiconductor
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#ifndef __LS1046ARDB_H__
	8	#define __LS1046ARDB_H__
	9
	10	#include "ls1046a_common.h"
	11
dd02936f MH	12	#ifdef CONFIG_SD_BOOT
	13	#define CONFIG_SYS_TEXT_BASE 0x82000000
	14	#else
	15	#define CONFIG_SYS_TEXT_BASE 0x40100000
	16	#endif
	17
	18	#define CONFIG_SYS_CLK_FREQ 100000000
	19	#define CONFIG_DDR_CLK_FREQ 100000000
	20
	21	#define CONFIG_LAYERSCAPE_NS_ACCESS
	22	#define CONFIG_MISC_INIT_R
	23
	24	#define CONFIG_DIMM_SLOTS_PER_CTLR 1
	25	/* Physical Memory Map */
	26	#define CONFIG_CHIP_SELECTS_PER_CTRL 4
	27	#define CONFIG_NR_DRAM_BANKS 2
	28
	29	#define CONFIG_DDR_SPD
	30	#define SPD_EEPROM_ADDRESS 0x51
	31	#define CONFIG_SYS_SPD_BUS_NUM 0
	32
	33	#define CONFIG_DDR_ECC
	34	#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
	35	#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
	36	#define CONFIG_FSL_DDR_BIST /* enable built-in memory test */
	37	#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
	38
	39	#ifdef CONFIG_RAMBOOT_PBL
	40	#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1046ardb/ls1046ardb_pbi.cfg
	41	#endif
	42
	43	#ifdef CONFIG_SD_BOOT
	44	#ifdef CONFIG_EMMC_BOOT
	45	#define CONFIG_SYS_FSL_PBL_RCW \
	46	board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg
	47	#else
	48	#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg
	49	#endif
	50	#endif
	51
dd02936f MH	52	/* IFC */
	53	#define CONFIG_FSL_IFC
	54
	55	/*
	56	* NAND Flash Definitions
	57	*/
	58	#define CONFIG_NAND_FSL_IFC
	59
	60	#define CONFIG_SYS_NAND_BASE 0x7e800000
	61	#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
	62
	63	#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
	64	#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
	65	\| CSPR_PORT_SIZE_8 \
	66	\| CSPR_MSEL_NAND \
	67	\| CSPR_V)
	68	#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
	69	#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
	70	\| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
	71	\| CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \
	72	\| CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
	73	\| CSOR_NAND_PGS_4K /* Page Size = 4K */ \
	74	\| CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
	75	\| CSOR_NAND_PB(64)) /* 64 Pages Per Block */
	76
	77	#define CONFIG_SYS_NAND_ONFI_DETECTION
	78
	79	#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) \| \
	80	FTIM0_NAND_TWP(0x18) \| \
	81	FTIM0_NAND_TWCHT(0x7) \| \
	82	FTIM0_NAND_TWH(0xa))
	83	#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) \| \
	84	FTIM1_NAND_TWBE(0x39) \| \
	85	FTIM1_NAND_TRR(0xe) \| \
	86	FTIM1_NAND_TRP(0x18))
	87	#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) \| \
	88	FTIM2_NAND_TREH(0xa) \| \
	89	FTIM2_NAND_TWHRE(0x1e))
	90	#define CONFIG_SYS_NAND_FTIM3 0x0
	91
	92	#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
	93	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	94	#define CONFIG_MTD_NAND_VERIFY_WRITE
	95	#define CONFIG_CMD_NAND
	96
	97	#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
	98
	99	/*
	100	* CPLD
	101	*/
	102	#define CONFIG_SYS_CPLD_BASE 0x7fb00000
	103	#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
	104
	105	#define CONFIG_SYS_CPLD_CSPR_EXT (0x0)
	106	#define CONFIG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) \| \
	107	CSPR_PORT_SIZE_8 \| \
	108	CSPR_MSEL_GPCM \| \
	109	CSPR_V)
	110	#define CONFIG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024)
	111	#define CONFIG_SYS_CPLD_CSOR CSOR_NOR_ADM_SHIFT(16)
	112
	113	/* CPLD Timing parameters for IFC GPCM */
	114	#define CONFIG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0x0e) \| \
	115	FTIM0_GPCM_TEADC(0x0e) \| \
116	FTIM0_GPCM_TEAHC(0x0e))
117	#define CONFIG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) \| \
118	FTIM1_GPCM_TRAD(0x3f))
119	#define CONFIG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) \| \
120	FTIM2_GPCM_TCH(0xf) \| \
121	FTIM2_GPCM_TWP(0x3E))
122	#define CONFIG_SYS_CPLD_FTIM3 0x0
123
124	/* IFC Timing Params */
125	#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
126	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
127	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
128	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
129	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
130	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
131	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
132	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
133
134	#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT
135	#define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR
136	#define CONFIG_SYS_AMASK2 CONFIG_SYS_CPLD_AMASK
137	#define CONFIG_SYS_CSOR2 CONFIG_SYS_CPLD_CSOR
138	#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_CPLD_FTIM0
139	#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_CPLD_FTIM1
140	#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2
141	#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3
142
143	/* EEPROM */
144	#define CONFIG_ID_EEPROM
145	#define CONFIG_SYS_I2C_EEPROM_NXID
146	#define CONFIG_SYS_EEPROM_BUS_NUM 0
147	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
148	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
149	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
150	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
151	#define I2C_RETIMER_ADDR 0x18
152
dccef2ec HZ	153	/* PMIC */
	154	#define CONFIG_POWER
	155	#ifdef CONFIG_POWER
	156	#define CONFIG_POWER_I2C
	157	#endif
	158
dd02936f MH	159	/*
	160	* Environment
	161	*/
	162	#define CONFIG_ENV_OVERWRITE
	163
	164	#if defined(CONFIG_SD_BOOT)
	165	#define CONFIG_ENV_IS_IN_MMC
	166	#define CONFIG_SYS_MMC_ENV_DEV 0
	167	#define CONFIG_ENV_OFFSET (1024 * 1024)
	168	#define CONFIG_ENV_SIZE 0x2000
	169	#else
	170	#define CONFIG_ENV_IS_IN_SPI_FLASH
	171	#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
	172	#define CONFIG_ENV_OFFSET 0x200000 /* 2MB */
	173	#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256KB */
	174	#endif
	175
	176	/* FMan */
	177	#ifdef CONFIG_SYS_DPAA_FMAN
	178	#define CONFIG_FMAN_ENET
	179	#define CONFIG_PHYLIB
	180	#define CONFIG_PHYLIB_10G
	181	#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
	182
	183	#define CONFIG_PHY_REALTEK
	184	#define CONFIG_PHY_AQUANTIA
	185	#define AQR105_IRQ_MASK 0x80000000
	186
	187	#define RGMII_PHY1_ADDR 0x1
	188	#define RGMII_PHY2_ADDR 0x2
	189
	190	#define SGMII_PHY1_ADDR 0x3
	191	#define SGMII_PHY2_ADDR 0x4
	192
	193	#define FM1_10GEC1_PHY_ADDR 0x0
	194
	195	#define CONFIG_ETHPRIME "FM1@DTSEC3"
	196	#endif
	197
	198	/* QSPI device */
	199	#ifdef CONFIG_FSL_QSPI
	200	#define CONFIG_SPI_FLASH_SPANSION
	201	#define FSL_QSPI_FLASH_SIZE (1 << 26)
	202	#define FSL_QSPI_FLASH_NUM 2
	203	#define CONFIG_SPI_FLASH_BAR
	204	#endif
	205
97205eea	206	/* USB */
	207	#define CONFIG_HAS_FSL_XHCI_USB
	208	#ifdef CONFIG_HAS_FSL_XHCI_USB
	209	#define CONFIG_USB_XHCI_HCD
	210	#define CONFIG_USB_XHCI_FSL
	211	#define CONFIG_USB_XHCI_DWC3
	212	#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
	213	#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
	214	#define CONFIG_CMD_USB
	215	#define CONFIG_USB_STORAGE
	216	#endif
	217
dd02936f MH	218	/* SATA */
	219	#define CONFIG_LIBATA
	220	#define CONFIG_SCSI_AHCI
	221	#define CONFIG_SCSI_AHCI_PLAT
	222	#define CONFIG_SCSI
dd02936f MH	223
	224	#define CONFIG_SYS_SATA AHCI_BASE_ADDR
	225
	226	#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
	227	#define CONFIG_SYS_SCSI_MAX_LUN 1
	228	#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
	229	CONFIG_SYS_SCSI_MAX_LUN)
9e0bb4c1	230
dd02936f MH	231	#define CONFIG_BOOTCOMMAND "sf probe 0:0;sf read $kernel_load" \
	232	"$kernel_start $kernel_size;" \
	233	"bootm $kernel_load"
	234
	235	#define MTDPARTS_DEFAULT "mtdparts=1550000.quadspi:1m(rcw)," \
	236	"15m(u-boot),48m(kernel.itb);" \
	237	"7e800000.flash:16m(nand_uboot)," \
	238	"48m(nand_kernel),448m(nand_free)"
	239
	240	#endif /* __LS1046ARDB_H__ */