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7769776a AK |
1 | /* |
2 | * Copyright 2017 NXP | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
6 | ||
7 | #ifndef __LS1088A_QDS_H | |
8 | #define __LS1088A_QDS_H | |
9 | ||
10 | #include "ls1088a_common.h" | |
11 | ||
12 | ||
13 | #define CONFIG_DISPLAY_BOARDINFO_LATE | |
14 | ||
15 | ||
16 | #ifndef __ASSEMBLY__ | |
17 | unsigned long get_board_sys_clk(void); | |
18 | unsigned long get_board_ddr_clk(void); | |
19 | #endif | |
20 | ||
21 | ||
22 | #if defined(CONFIG_QSPI_BOOT) | |
7769776a | 23 | #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ |
7769776a | 24 | #define CONFIG_ENV_SECT_SIZE 0x40000 |
91fded62 AK |
25 | #elif defined(CONFIG_SD_BOOT) |
26 | #define CONFIG_ENV_OFFSET (3 * 1024 * 1024) | |
27 | #define CONFIG_SYS_MMC_ENV_DEV 0 | |
28 | #define CONFIG_ENV_SIZE 0x2000 | |
7769776a AK |
29 | #else |
30 | #define CONFIG_ENV_IS_IN_FLASH | |
31 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) | |
32 | #define CONFIG_ENV_SECT_SIZE 0x20000 | |
33 | #define CONFIG_ENV_SIZE 0x20000 | |
34 | #endif | |
35 | ||
91fded62 | 36 | #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) |
7769776a AK |
37 | #define CONFIG_QIXIS_I2C_ACCESS |
38 | #define SYS_NO_FLASH | |
39 | ||
91fded62 | 40 | #undef CONFIG_CMD_IMLS |
7769776a AK |
41 | #define CONFIG_SYS_CLK_FREQ 100000000 |
42 | #define CONFIG_DDR_CLK_FREQ 100000000 | |
43 | #else | |
44 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() | |
45 | #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() | |
46 | #endif | |
47 | ||
48 | #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) | |
49 | #define COUNTER_FREQUENCY 25000000 /* 25MHz */ | |
50 | ||
51 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
52 | ||
53 | #define CONFIG_DDR_SPD | |
54 | #define CONFIG_DDR_ECC | |
55 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER | |
56 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef | |
57 | #define SPD_EEPROM_ADDRESS 0x51 | |
58 | #define CONFIG_SYS_SPD_BUS_NUM 0 | |
59 | ||
60 | ||
61 | /* | |
62 | * IFC Definitions | |
63 | */ | |
64 | #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) | |
65 | #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) | |
66 | #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) | |
67 | #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) | |
68 | ||
69 | #define CONFIG_SYS_NOR0_CSPR \ | |
70 | (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ | |
71 | CSPR_PORT_SIZE_16 | \ | |
72 | CSPR_MSEL_NOR | \ | |
73 | CSPR_V) | |
74 | #define CONFIG_SYS_NOR0_CSPR_EARLY \ | |
75 | (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ | |
76 | CSPR_PORT_SIZE_16 | \ | |
77 | CSPR_MSEL_NOR | \ | |
78 | CSPR_V) | |
79 | #define CONFIG_SYS_NOR1_CSPR \ | |
80 | (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \ | |
81 | CSPR_PORT_SIZE_16 | \ | |
82 | CSPR_MSEL_NOR | \ | |
83 | CSPR_V) | |
84 | #define CONFIG_SYS_NOR1_CSPR_EARLY \ | |
85 | (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \ | |
86 | CSPR_PORT_SIZE_16 | \ | |
87 | CSPR_MSEL_NOR | \ | |
88 | CSPR_V) | |
89 | #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) | |
90 | #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ | |
91 | FTIM0_NOR_TEADC(0x5) | \ | |
92 | FTIM0_NOR_TEAHC(0x5)) | |
93 | #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ | |
94 | FTIM1_NOR_TRAD_NOR(0x1a) |\ | |
95 | FTIM1_NOR_TSEQRAD_NOR(0x13)) | |
96 | #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ | |
97 | FTIM2_NOR_TCH(0x4) | \ | |
98 | FTIM2_NOR_TWPH(0x0E) | \ | |
99 | FTIM2_NOR_TWP(0x1c)) | |
100 | #define CONFIG_SYS_NOR_FTIM3 0x04000000 | |
101 | #define CONFIG_SYS_IFC_CCR 0x01000000 | |
102 | ||
103 | #ifndef SYS_NO_FLASH | |
104 | #define CONFIG_FLASH_CFI_DRIVER | |
105 | #define CONFIG_SYS_FLASH_CFI | |
106 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
107 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
108 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
109 | ||
110 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ | |
111 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
112 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
113 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
114 | ||
115 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
116 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ | |
117 | CONFIG_SYS_FLASH_BASE + 0x40000000} | |
118 | #endif | |
119 | #endif | |
120 | ||
121 | #define CONFIG_NAND_FSL_IFC | |
122 | #define CONFIG_SYS_NAND_MAX_ECCPOS 256 | |
123 | #define CONFIG_SYS_NAND_MAX_OOBFREE 2 | |
124 | ||
125 | #define CONFIG_SYS_NAND_CSPR_EXT (0x0) | |
126 | #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | |
127 | | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ | |
128 | | CSPR_MSEL_NAND /* MSEL = NAND */ \ | |
129 | | CSPR_V) | |
130 | #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) | |
131 | ||
132 | #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | |
133 | | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | |
134 | | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | |
135 | | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ | |
136 | | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ | |
137 | | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ | |
138 | | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ | |
139 | ||
140 | #define CONFIG_SYS_NAND_ONFI_DETECTION | |
141 | ||
142 | /* ONFI NAND Flash mode0 Timing Params */ | |
143 | #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ | |
144 | FTIM0_NAND_TWP(0x18) | \ | |
145 | FTIM0_NAND_TWCHT(0x07) | \ | |
146 | FTIM0_NAND_TWH(0x0a)) | |
147 | #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ | |
148 | FTIM1_NAND_TWBE(0x39) | \ | |
149 | FTIM1_NAND_TRR(0x0e) | \ | |
150 | FTIM1_NAND_TRP(0x18)) | |
151 | #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ | |
152 | FTIM2_NAND_TREH(0x0a) | \ | |
153 | FTIM2_NAND_TWHRE(0x1e)) | |
154 | #define CONFIG_SYS_NAND_FTIM3 0x0 | |
155 | ||
156 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } | |
157 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
158 | #define CONFIG_MTD_NAND_VERIFY_WRITE | |
159 | #define CONFIG_CMD_NAND | |
160 | ||
161 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) | |
162 | ||
163 | #define CONFIG_FSL_QIXIS | |
164 | #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 | |
165 | #define QIXIS_LBMAP_SWITCH 6 | |
166 | #define QIXIS_QMAP_MASK 0xe0 | |
167 | #define QIXIS_QMAP_SHIFT 5 | |
168 | #define QIXIS_LBMAP_MASK 0x0f | |
169 | #define QIXIS_LBMAP_SHIFT 0 | |
170 | #define QIXIS_LBMAP_DFLTBANK 0x0e | |
171 | #define QIXIS_LBMAP_ALTBANK 0x2e | |
172 | #define QIXIS_LBMAP_SD 0x00 | |
6c8945ec AK |
173 | #define QIXIS_LBMAP_EMMC 0x00 |
174 | #define QIXIS_LBMAP_IFC 0x00 | |
7769776a AK |
175 | #define QIXIS_LBMAP_SD_QSPI 0x0e |
176 | #define QIXIS_LBMAP_QSPI 0x0e | |
6c8945ec | 177 | #define QIXIS_RCW_SRC_IFC 0x25 |
7769776a | 178 | #define QIXIS_RCW_SRC_SD 0x40 |
6c8945ec | 179 | #define QIXIS_RCW_SRC_EMMC 0x41 |
7769776a AK |
180 | #define QIXIS_RCW_SRC_QSPI 0x62 |
181 | #define QIXIS_RST_CTL_RESET 0x41 | |
182 | #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 | |
183 | #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 | |
184 | #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 | |
185 | #define QIXIS_RST_FORCE_MEM 0x01 | |
186 | #define QIXIS_STAT_PRES1 0xb | |
187 | #define QIXIS_SDID_MASK 0x07 | |
188 | #define QIXIS_ESDHC_NO_ADAPTER 0x7 | |
189 | ||
190 | #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) | |
191 | #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ | |
192 | | CSPR_PORT_SIZE_8 \ | |
193 | | CSPR_MSEL_GPCM \ | |
194 | | CSPR_V) | |
195 | #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ | |
196 | | CSPR_PORT_SIZE_8 \ | |
197 | | CSPR_MSEL_GPCM \ | |
198 | | CSPR_V) | |
199 | ||
200 | #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64*1024) | |
91fded62 | 201 | #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) |
7769776a AK |
202 | #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0) |
203 | #else | |
204 | #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(12) | |
205 | #endif | |
206 | /* QIXIS Timing parameters*/ | |
207 | #define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ | |
208 | FTIM0_GPCM_TEADC(0x0e) | \ | |
209 | FTIM0_GPCM_TEAHC(0x0e)) | |
210 | #define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ | |
211 | FTIM1_GPCM_TRAD(0x3f)) | |
212 | #define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ | |
213 | FTIM2_GPCM_TCH(0xf) | \ | |
214 | FTIM2_GPCM_TWP(0x3E)) | |
215 | #define SYS_FPGA_CS_FTIM3 0x0 | |
216 | ||
217 | #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) | |
218 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT | |
219 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR | |
220 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK | |
221 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR | |
222 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
223 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
224 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
225 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
226 | #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT | |
227 | #define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR | |
228 | #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL | |
229 | #define CONFIG_SYS_AMASK2 CONFIG_SYS_FPGA_AMASK | |
230 | #define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR | |
231 | #define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0 | |
232 | #define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1 | |
233 | #define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2 | |
234 | #define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3 | |
235 | #else | |
236 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT | |
237 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY | |
238 | #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR | |
239 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK | |
240 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR | |
241 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
242 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
243 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
244 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
245 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT | |
246 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY | |
247 | #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR | |
248 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY | |
249 | #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK | |
250 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR | |
251 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
252 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
253 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
254 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
255 | #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT | |
256 | #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR | |
257 | #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK | |
258 | #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR | |
259 | #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
260 | #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
261 | #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
262 | #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
263 | #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT | |
264 | #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR | |
265 | #define CONFIG_SYS_CSPR3_FINAL CONFIG_SYS_FPGA_CSPR_FINAL | |
266 | #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK | |
267 | #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR | |
268 | #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_CS_FTIM0 | |
269 | #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_CS_FTIM1 | |
270 | #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_CS_FTIM2 | |
271 | #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_CS_FTIM3 | |
272 | #endif | |
273 | ||
274 | #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 | |
275 | ||
276 | /* | |
277 | * I2C bus multiplexer | |
278 | */ | |
279 | #define I2C_MUX_PCA_ADDR_PRI 0x77 | |
280 | #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ | |
281 | #define I2C_RETIMER_ADDR 0x18 | |
282 | #define I2C_RETIMER_ADDR2 0x19 | |
283 | #define I2C_MUX_CH_DEFAULT 0x8 | |
284 | #define I2C_MUX_CH5 0xD | |
285 | ||
23a12cb3 RB |
286 | #define I2C_MUX_CH_VOL_MONITOR 0xA |
287 | ||
288 | /* Voltage monitor on channel 2*/ | |
289 | #define I2C_VOL_MONITOR_ADDR 0x63 | |
290 | #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 | |
291 | #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 | |
292 | #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 | |
ef0789b7 RB |
293 | #define I2C_SVDD_MONITOR_ADDR 0x4F |
294 | ||
295 | #define CONFIG_VID_FLS_ENV "ls1088aqds_vdd_mv" | |
296 | #define CONFIG_VID | |
297 | ||
298 | /* The lowest and highest voltage allowed for LS1088AQDS */ | |
299 | #define VDD_MV_MIN 819 | |
300 | #define VDD_MV_MAX 1212 | |
301 | ||
302 | #define CONFIG_VOL_MONITOR_LTC3882_SET | |
303 | #define CONFIG_VOL_MONITOR_LTC3882_READ | |
23a12cb3 RB |
304 | |
305 | /* PM Bus commands code for LTC3882*/ | |
306 | #define PMBUS_CMD_PAGE 0x0 | |
307 | #define PMBUS_CMD_READ_VOUT 0x8B | |
308 | #define PMBUS_CMD_PAGE_PLUS_WRITE 0x05 | |
309 | #define PMBUS_CMD_VOUT_COMMAND 0x21 | |
310 | ||
311 | #define PWM_CHANNEL0 0x0 | |
312 | ||
7769776a AK |
313 | /* |
314 | * RTC configuration | |
315 | */ | |
316 | #define RTC | |
317 | #define CONFIG_RTC_PCF8563 1 | |
318 | #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ | |
319 | #define CONFIG_CMD_DATE | |
320 | ||
321 | /* EEPROM */ | |
322 | #define CONFIG_ID_EEPROM | |
323 | #define CONFIG_SYS_I2C_EEPROM_NXID | |
324 | #define CONFIG_SYS_EEPROM_BUS_NUM 0 | |
325 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 | |
326 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
327 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
328 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 | |
329 | ||
330 | /* QSPI device */ | |
91fded62 | 331 | #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) |
7769776a | 332 | #define CONFIG_FSL_QSPI |
7769776a AK |
333 | #define FSL_QSPI_FLASH_SIZE (1 << 26) |
334 | #define FSL_QSPI_FLASH_NUM 2 | |
335 | ||
336 | #endif | |
337 | ||
338 | #ifdef CONFIG_FSL_DSPI | |
339 | #define CONFIG_SPI_FLASH_STMICRO | |
340 | #define CONFIG_SPI_FLASH_SST | |
341 | #define CONFIG_SPI_FLASH_EON | |
342 | #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) | |
343 | #define CONFIG_SF_DEFAULT_BUS 1 | |
344 | #define CONFIG_SF_DEFAULT_CS 0 | |
345 | #endif | |
346 | #endif | |
347 | ||
348 | #define CONFIG_CMD_MEMINFO | |
349 | #define CONFIG_CMD_MEMTEST | |
350 | #define CONFIG_SYS_MEMTEST_START 0x80000000 | |
351 | #define CONFIG_SYS_MEMTEST_END 0x9fffffff | |
352 | ||
91fded62 AK |
353 | #ifdef CONFIG_SPL_BUILD |
354 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE | |
355 | #else | |
7769776a | 356 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
91fded62 | 357 | #endif |
7769776a AK |
358 | |
359 | #define CONFIG_FSL_MEMAC | |
360 | ||
361 | /* MMC */ | |
362 | #define CONFIG_FSL_ESDHC | |
363 | #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 | |
364 | #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \ | |
365 | QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER) | |
366 | ||
367 | /* Initial environment variables */ | |
30c41d21 UA |
368 | #ifdef CONFIG_SECURE_BOOT |
369 | #undef CONFIG_EXTRA_ENV_SETTINGS | |
370 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
371 | "hwconfig=fsl_ddr:bank_intlv=auto\0" \ | |
372 | "loadaddr=0x90100000\0" \ | |
373 | "kernel_addr=0x100000\0" \ | |
374 | "ramdisk_addr=0x800000\0" \ | |
375 | "ramdisk_size=0x2000000\0" \ | |
376 | "fdt_high=0xa0000000\0" \ | |
377 | "initrd_high=0xffffffffffffffff\0" \ | |
378 | "kernel_start=0x1000000\0" \ | |
379 | "kernel_load=0xa0000000\0" \ | |
380 | "kernel_size=0x2800000\0" \ | |
381 | "mcinitcmd=sf probe 0:0;sf read 0xa0a00000 0xa00000 0x100000;" \ | |
382 | "sf read 0xa0700000 0x700000 0x4000; esbc_validate 0xa0700000;" \ | |
383 | "sf read 0xa0e00000 0xe00000 0x100000;" \ | |
384 | "sf read 0xa0740000 0x740000 0x4000;esbc_validate 0xa0740000;" \ | |
385 | "fsl_mc start mc 0xa0a00000 0xa0e00000\0" \ | |
386 | "mcmemsize=0x70000000 \0" | |
387 | #else /* if !(CONFIG_SECURE_BOOT) */ | |
7769776a AK |
388 | #if defined(CONFIG_QSPI_BOOT) |
389 | #undef CONFIG_EXTRA_ENV_SETTINGS | |
390 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
391 | "hwconfig=fsl_ddr:bank_intlv=auto\0" \ | |
392 | "loadaddr=0x90100000\0" \ | |
393 | "kernel_addr=0x100000\0" \ | |
394 | "ramdisk_addr=0x800000\0" \ | |
395 | "ramdisk_size=0x2000000\0" \ | |
396 | "fdt_high=0xa0000000\0" \ | |
397 | "initrd_high=0xffffffffffffffff\0" \ | |
398 | "kernel_start=0x1000000\0" \ | |
399 | "kernel_load=0xa0000000\0" \ | |
400 | "kernel_size=0x2800000\0" \ | |
401 | "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \ | |
402 | "sf read 0x80100000 0xE00000 0x100000;" \ | |
403 | "fsl_mc start mc 0x80000000 0x80100000\0" \ | |
404 | "mcmemsize=0x70000000 \0" | |
91fded62 AK |
405 | #elif defined(CONFIG_SD_BOOT) |
406 | #undef CONFIG_EXTRA_ENV_SETTINGS | |
407 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
408 | "hwconfig=fsl_ddr:bank_intlv=auto\0" \ | |
409 | "loadaddr=0x90100000\0" \ | |
410 | "kernel_addr=0x800\0" \ | |
411 | "ramdisk_addr=0x800000\0" \ | |
412 | "ramdisk_size=0x2000000\0" \ | |
413 | "fdt_high=0xa0000000\0" \ | |
414 | "initrd_high=0xffffffffffffffff\0" \ | |
415 | "kernel_start=0x8000\0" \ | |
416 | "kernel_load=0xa0000000\0" \ | |
417 | "kernel_size=0x14000\0" \ | |
418 | "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ | |
419 | "mmc read 0x80100000 0x7000 0x800;" \ | |
420 | "fsl_mc start mc 0x80000000 0x80100000\0" \ | |
421 | "mcmemsize=0x70000000 \0" | |
7769776a AK |
422 | #else /* NOR BOOT */ |
423 | #undef CONFIG_EXTRA_ENV_SETTINGS | |
424 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
425 | "hwconfig=fsl_ddr:bank_intlv=auto\0" \ | |
426 | "loadaddr=0x90100000\0" \ | |
427 | "kernel_addr=0x100000\0" \ | |
428 | "ramdisk_addr=0x800000\0" \ | |
429 | "ramdisk_size=0x2000000\0" \ | |
430 | "fdt_high=0xa0000000\0" \ | |
431 | "initrd_high=0xffffffffffffffff\0" \ | |
432 | "kernel_start=0x1000000\0" \ | |
433 | "kernel_load=0xa0000000\0" \ | |
434 | "kernel_size=0x2800000\0" \ | |
435 | "mcinitcmd=fsl_mc start mc 0x580A00000 0x580E00000\0" \ | |
436 | "mcmemsize=0x70000000 \0" | |
437 | #endif | |
30c41d21 | 438 | #endif /* CONFIG_SECURE_BOOT */ |
7769776a AK |
439 | |
440 | #ifdef CONFIG_FSL_MC_ENET | |
441 | #define CONFIG_FSL_MEMAC | |
442 | #define CONFIG_PHYLIB | |
443 | #define CONFIG_PHYLIB_10G | |
444 | #define CONFIG_PHY_VITESSE | |
445 | #define CONFIG_PHY_REALTEK | |
446 | #define CONFIG_PHY_TERANETICS | |
447 | #define RGMII_PHY1_ADDR 0x1 | |
448 | #define RGMII_PHY2_ADDR 0x2 | |
449 | #define SGMII_CARD_PORT1_PHY_ADDR 0x1C | |
450 | #define SGMII_CARD_PORT2_PHY_ADDR 0x1d | |
451 | #define SGMII_CARD_PORT3_PHY_ADDR 0x1E | |
452 | #define SGMII_CARD_PORT4_PHY_ADDR 0x1F | |
453 | ||
454 | #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0 | |
455 | #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1 | |
456 | #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2 | |
457 | #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3 | |
458 | #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4 | |
459 | #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5 | |
460 | #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6 | |
461 | #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7 | |
462 | #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8 | |
463 | #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9 | |
464 | #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa | |
465 | #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb | |
466 | #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc | |
467 | #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd | |
468 | #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe | |
469 | #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf | |
470 | ||
471 | #define CONFIG_MII /* MII PHY management */ | |
472 | #define CONFIG_ETHPRIME "DPMAC1@xgmii" | |
473 | #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ | |
474 | ||
475 | #endif | |
476 | ||
477 | #undef CONFIG_CMDLINE_EDITING | |
478 | #include <config_distro_defaults.h> | |
479 | #define BOOT_TARGET_DEVICES(func) \ | |
480 | func(USB, usb, 0) \ | |
481 | func(MMC, mmc, 0) \ | |
482 | func(SCSI, scsi, 0) \ | |
483 | func(DHCP, dhcp, na) | |
484 | #include <config_distro_bootcmd.h> | |
485 | ||
486 | #include <asm/fsl_secure_boot.h> | |
487 | ||
488 | #endif /* __LS1088A_QDS_H */ |