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e84a324b AK |
1 | /* |
2 | * Copyright 2017 NXP | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
6 | ||
7 | #ifndef __LS1088A_RDB_H | |
8 | #define __LS1088A_RDB_H | |
9 | ||
10 | #include "ls1088a_common.h" | |
11 | ||
12 | #define CONFIG_DISPLAY_BOARDINFO_LATE | |
13 | ||
44cdb5b6 YL |
14 | #define CONFIG_MISC_INIT_R |
15 | ||
e84a324b | 16 | #if defined(CONFIG_QSPI_BOOT) |
e84a324b AK |
17 | #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ |
18 | #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ | |
19 | #define CONFIG_ENV_SECT_SIZE 0x40000 | |
099f4093 AK |
20 | #elif defined(CONFIG_SD_BOOT) |
21 | #define CONFIG_ENV_OFFSET (3 * 1024 * 1024) | |
22 | #define CONFIG_SYS_MMC_ENV_DEV 0 | |
23 | #define CONFIG_ENV_SIZE 0x2000 | |
e84a324b AK |
24 | #else |
25 | #define CONFIG_ENV_IS_IN_FLASH | |
26 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) | |
27 | #define CONFIG_ENV_SECT_SIZE 0x20000 | |
28 | #define CONFIG_ENV_SIZE 0x20000 | |
29 | #endif | |
30 | ||
099f4093 | 31 | #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) |
e84a324b AK |
32 | #define CONFIG_QIXIS_I2C_ACCESS |
33 | #define SYS_NO_FLASH | |
099f4093 | 34 | #undef CONFIG_CMD_IMLS |
e84a324b AK |
35 | #endif |
36 | ||
37 | #define CONFIG_SYS_CLK_FREQ 100000000 | |
38 | #define CONFIG_DDR_CLK_FREQ 100000000 | |
39 | #define COUNTER_FREQUENCY_REAL 25000000 /* 25MHz */ | |
40 | #define COUNTER_FREQUENCY 25000000 /* 25MHz */ | |
41 | ||
42 | #define CONFIG_DDR_SPD | |
43 | #ifdef CONFIG_EMU | |
44 | #define CONFIG_SYS_FSL_DDR_EMU | |
45 | #define CONFIG_SYS_MXC_I2C1_SPEED 40000000 | |
46 | #define CONFIG_SYS_MXC_I2C2_SPEED 40000000 | |
47 | #else | |
48 | #define CONFIG_DDR_ECC | |
49 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER | |
50 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef | |
51 | #endif | |
52 | #define SPD_EEPROM_ADDRESS 0x51 | |
53 | #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ | |
54 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
55 | ||
56 | ||
57 | #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) | |
58 | #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) | |
59 | #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) | |
60 | #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64 * 1024 * 1024) | |
61 | ||
62 | #define CONFIG_SYS_NOR0_CSPR \ | |
63 | (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ | |
64 | CSPR_PORT_SIZE_16 | \ | |
65 | CSPR_MSEL_NOR | \ | |
66 | CSPR_V) | |
67 | #define CONFIG_SYS_NOR0_CSPR_EARLY \ | |
68 | (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ | |
69 | CSPR_PORT_SIZE_16 | \ | |
70 | CSPR_MSEL_NOR | \ | |
71 | CSPR_V) | |
72 | #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(6) | |
73 | #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ | |
74 | FTIM0_NOR_TEADC(0x1) | \ | |
75 | FTIM0_NOR_TEAHC(0x1)) | |
76 | #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ | |
77 | FTIM1_NOR_TRAD_NOR(0x1)) | |
78 | #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \ | |
79 | FTIM2_NOR_TCH(0x0) | \ | |
80 | FTIM2_NOR_TWP(0x1)) | |
81 | #define CONFIG_SYS_NOR_FTIM3 0x04000000 | |
82 | #define CONFIG_SYS_IFC_CCR 0x01000000 | |
83 | ||
84 | #ifndef SYS_NO_FLASH | |
85 | #define CONFIG_FLASH_CFI_DRIVER | |
86 | #define CONFIG_SYS_FLASH_CFI | |
87 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
88 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
89 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
90 | ||
91 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
92 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
93 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
94 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
95 | ||
96 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
97 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } | |
98 | #endif | |
99 | #endif | |
d798a6ee | 100 | #define CONFIG_NAND_FSL_IFC |
e84a324b AK |
101 | #define CONFIG_SYS_NAND_MAX_ECCPOS 256 |
102 | #define CONFIG_SYS_NAND_MAX_OOBFREE 2 | |
103 | ||
104 | #define CONFIG_SYS_NAND_CSPR_EXT (0x0) | |
105 | #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | |
106 | | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ | |
107 | | CSPR_MSEL_NAND /* MSEL = NAND */ \ | |
108 | | CSPR_V) | |
109 | #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) | |
110 | ||
111 | #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | |
112 | | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | |
113 | | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | |
114 | | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ | |
115 | | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ | |
116 | | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ | |
117 | | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ | |
118 | ||
119 | #define CONFIG_SYS_NAND_ONFI_DETECTION | |
120 | ||
121 | /* ONFI NAND Flash mode0 Timing Params */ | |
122 | #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ | |
123 | FTIM0_NAND_TWP(0x18) | \ | |
124 | FTIM0_NAND_TWCHT(0x07) | \ | |
125 | FTIM0_NAND_TWH(0x0a)) | |
126 | #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ | |
127 | FTIM1_NAND_TWBE(0x39) | \ | |
128 | FTIM1_NAND_TRR(0x0e) | \ | |
129 | FTIM1_NAND_TRP(0x18)) | |
130 | #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ | |
131 | FTIM2_NAND_TREH(0x0a) | \ | |
132 | FTIM2_NAND_TWHRE(0x1e)) | |
133 | #define CONFIG_SYS_NAND_FTIM3 0x0 | |
134 | ||
135 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } | |
136 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
137 | #define CONFIG_MTD_NAND_VERIFY_WRITE | |
d798a6ee | 138 | #define CONFIG_CMD_NAND |
e84a324b AK |
139 | |
140 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) | |
141 | ||
142 | #define CONFIG_FSL_QIXIS | |
143 | #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 | |
144 | #define QIXIS_LBMAP_SWITCH 2 | |
145 | #define QIXIS_QMAP_MASK 0xe0 | |
146 | #define QIXIS_QMAP_SHIFT 5 | |
147 | #define QIXIS_LBMAP_MASK 0x1f | |
148 | #define QIXIS_LBMAP_SHIFT 5 | |
149 | #define QIXIS_LBMAP_DFLTBANK 0x00 | |
150 | #define QIXIS_LBMAP_ALTBANK 0x20 | |
151 | #define QIXIS_LBMAP_SD 0x00 | |
152 | #define QIXIS_LBMAP_SD_QSPI 0x00 | |
153 | #define QIXIS_LBMAP_QSPI 0x00 | |
154 | #define QIXIS_RCW_SRC_SD 0x40 | |
155 | #define QIXIS_RCW_SRC_QSPI 0x62 | |
156 | #define QIXIS_RST_CTL_RESET 0x31 | |
157 | #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 | |
158 | #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 | |
159 | #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 | |
160 | #define QIXIS_RST_FORCE_MEM 0x01 | |
161 | ||
162 | #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) | |
163 | #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ | |
164 | | CSPR_PORT_SIZE_8 \ | |
165 | | CSPR_MSEL_GPCM \ | |
166 | | CSPR_V) | |
167 | #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ | |
168 | | CSPR_PORT_SIZE_8 \ | |
169 | | CSPR_MSEL_GPCM \ | |
170 | | CSPR_V) | |
171 | ||
172 | #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64*1024) | |
173 | #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0) | |
174 | /* QIXIS Timing parameters*/ | |
175 | #define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ | |
176 | FTIM0_GPCM_TEADC(0x0e) | \ | |
177 | FTIM0_GPCM_TEAHC(0x0e)) | |
178 | #define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ | |
179 | FTIM1_GPCM_TRAD(0x3f)) | |
180 | #define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ | |
181 | FTIM2_GPCM_TCH(0xf) | \ | |
182 | FTIM2_GPCM_TWP(0x3E)) | |
183 | #define SYS_FPGA_CS_FTIM3 0x0 | |
184 | ||
185 | #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) | |
186 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT | |
187 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR | |
188 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK | |
189 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR | |
190 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
191 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
192 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
193 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
194 | #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT | |
195 | #define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR | |
196 | #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL | |
197 | #define CONFIG_SYS_AMASK2 CONFIG_SYS_FPGA_AMASK | |
198 | #define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR | |
199 | #define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0 | |
200 | #define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1 | |
201 | #define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2 | |
202 | #define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3 | |
203 | #else | |
204 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT | |
205 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY | |
206 | #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR | |
207 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK | |
208 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR | |
209 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
210 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
211 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
212 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
213 | #endif | |
214 | ||
215 | ||
216 | #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 | |
217 | ||
218 | /* | |
219 | * I2C bus multiplexer | |
220 | */ | |
221 | #define I2C_MUX_PCA_ADDR_PRI 0x77 | |
222 | #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ | |
223 | #define I2C_RETIMER_ADDR 0x18 | |
224 | #define I2C_MUX_CH_DEFAULT 0x8 | |
225 | #define I2C_MUX_CH5 0xD | |
226 | /* | |
227 | * RTC configuration | |
228 | */ | |
229 | #define RTC | |
230 | #define CONFIG_RTC_PCF8563 1 | |
231 | #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ | |
232 | #define CONFIG_CMD_DATE | |
233 | ||
234 | /* EEPROM */ | |
235 | #define CONFIG_ID_EEPROM | |
236 | #define CONFIG_SYS_I2C_EEPROM_NXID | |
237 | #define CONFIG_SYS_EEPROM_BUS_NUM 0 | |
238 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 | |
239 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
240 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
241 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 | |
242 | ||
243 | /* QSPI device */ | |
099f4093 | 244 | #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) |
e84a324b | 245 | #define CONFIG_FSL_QSPI |
e84a324b AK |
246 | #define FSL_QSPI_FLASH_SIZE (1 << 26) |
247 | #define FSL_QSPI_FLASH_NUM 2 | |
248 | #endif | |
249 | ||
250 | #define CONFIG_CMD_MEMINFO | |
251 | #define CONFIG_CMD_MEMTEST | |
252 | #define CONFIG_SYS_MEMTEST_START 0x80000000 | |
253 | #define CONFIG_SYS_MEMTEST_END 0x9fffffff | |
254 | ||
099f4093 AK |
255 | #ifdef CONFIG_SPL_BUILD |
256 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE | |
257 | #else | |
e84a324b | 258 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
099f4093 | 259 | #endif |
e84a324b AK |
260 | |
261 | #define CONFIG_FSL_MEMAC | |
262 | ||
263 | /* Initial environment variables */ | |
264 | #if defined(CONFIG_QSPI_BOOT) | |
d9195c62 | 265 | #define MC_INIT_CMD \ |
e84a324b | 266 | "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \ |
d9195c62 | 267 | "sf read 0x80100000 0xE00000 0x100000;" \ |
30c41d21 UA |
268 | "env exists secureboot && " \ |
269 | "sf read 0x80700000 0x700000 0x40000 && " \ | |
270 | "sf read 0x80740000 0x740000 0x40000 && " \ | |
271 | "esbc_validate 0x80700000 && " \ | |
272 | "esbc_validate 0x80740000 ;" \ | |
273 | "fsl_mc start mc 0x80000000 0x80100000\0" \ | |
d9195c62 | 274 | "mcmemsize=0x70000000\0" |
099f4093 | 275 | #elif defined(CONFIG_SD_BOOT) |
d9195c62 AK |
276 | #define MC_INIT_CMD \ |
277 | "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ | |
278 | "mmc read 0x80100000 0x7000 0x800;" \ | |
30c41d21 UA |
279 | "env exists secureboot && " \ |
280 | "mmc read 0x80700000 0x3800 0x10 && " \ | |
281 | "mmc read 0x80740000 0x3A00 0x10 && " \ | |
282 | "esbc_validate 0x80700000 && " \ | |
283 | "esbc_validate 0x80740000 ;" \ | |
284 | "fsl_mc start mc 0x80000000 0x80100000\0" \ | |
d9195c62 AK |
285 | "mcmemsize=0x70000000\0" |
286 | #endif | |
287 | ||
099f4093 AK |
288 | #undef CONFIG_EXTRA_ENV_SETTINGS |
289 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
d9195c62 | 290 | "BOARD=ls1088ardb\0" \ |
099f4093 | 291 | "hwconfig=fsl_ddr:bank_intlv=auto\0" \ |
099f4093 AK |
292 | "ramdisk_addr=0x800000\0" \ |
293 | "ramdisk_size=0x2000000\0" \ | |
294 | "fdt_high=0xa0000000\0" \ | |
295 | "initrd_high=0xffffffffffffffff\0" \ | |
d9195c62 AK |
296 | "fdt_addr=0x64f00000\0" \ |
297 | "kernel_addr=0x1000000\0" \ | |
298 | "kernel_addr_sd=0x8000\0" \ | |
30c41d21 | 299 | "kernelhdr_addr_sd=0x4000\0" \ |
d9195c62 AK |
300 | "kernel_start=0x580100000\0" \ |
301 | "kernelheader_start=0x580800000\0" \ | |
302 | "scriptaddr=0x80000000\0" \ | |
303 | "scripthdraddr=0x80080000\0" \ | |
304 | "fdtheader_addr_r=0x80100000\0" \ | |
305 | "kernelheader_addr=0x800000\0" \ | |
306 | "kernelheader_addr_r=0x80200000\0" \ | |
307 | "kernel_addr_r=0x81000000\0" \ | |
308 | "kernelheader_size=0x40000\0" \ | |
309 | "fdt_addr_r=0x90000000\0" \ | |
310 | "load_addr=0xa0000000\0" \ | |
311 | "kernel_size=0x2800000\0" \ | |
312 | "kernel_size_sd=0x14000\0" \ | |
30c41d21 | 313 | "kernelhdr_size_sd=0x10\0" \ |
d9195c62 AK |
314 | MC_INIT_CMD \ |
315 | BOOTENV \ | |
316 | "boot_scripts=ls1088ardb_boot.scr\0" \ | |
317 | "boot_script_hdr=hdr_ls1088ardb_bs.out\0" \ | |
318 | "scan_dev_for_boot_part=" \ | |
319 | "part list ${devtype} ${devnum} devplist; " \ | |
320 | "env exists devplist || setenv devplist 1; " \ | |
321 | "for distro_bootpart in ${devplist}; do " \ | |
322 | "if fstype ${devtype} " \ | |
323 | "${devnum}:${distro_bootpart} " \ | |
324 | "bootfstype; then " \ | |
325 | "run scan_dev_for_boot; " \ | |
326 | "fi; " \ | |
327 | "done\0" \ | |
328 | "scan_dev_for_boot=" \ | |
329 | "echo Scanning ${devtype} " \ | |
330 | "${devnum}:${distro_bootpart}...; " \ | |
331 | "for prefix in ${boot_prefixes}; do " \ | |
332 | "run scan_dev_for_scripts; " \ | |
333 | "done;\0" \ | |
334 | "boot_a_script=" \ | |
335 | "load ${devtype} ${devnum}:${distro_bootpart} " \ | |
336 | "${scriptaddr} ${prefix}${script}; " \ | |
337 | "env exists secureboot && load ${devtype} " \ | |
338 | "${devnum}:${distro_bootpart} " \ | |
339 | "${scripthdraddr} ${prefix}${boot_script_hdr} " \ | |
340 | "&& esbc_validate ${scripthdraddr};" \ | |
341 | "source ${scriptaddr}\0" \ | |
342 | "installer=load mmc 0:2 $load_addr " \ | |
343 | "/flex_installer_arm64.itb; " \ | |
344 | "env exists mcinitcmd && run mcinitcmd && " \ | |
345 | "mmc read 0x80200000 0x6800 0x800;" \ | |
346 | "fsl_mc apply dpl 0x80200000;" \ | |
347 | "bootm $load_addr#ls1088ardb\0" \ | |
348 | "qspi_bootcmd=echo Trying load from qspi..;" \ | |
349 | "sf probe && sf read $load_addr " \ | |
30c41d21 UA |
350 | "$kernel_addr $kernel_size ; env exists secureboot " \ |
351 | "&& sf read $kernelheader_addr_r $kernelheader_addr " \ | |
352 | "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ | |
d9195c62 | 353 | "bootm $load_addr#$BOARD\0" \ |
30c41d21 | 354 | "sd_bootcmd=echo Trying load from sd card..;" \ |
d9195c62 AK |
355 | "mmcinfo; mmc read $load_addr " \ |
356 | "$kernel_addr_sd $kernel_size_sd ;" \ | |
30c41d21 UA |
357 | "env exists secureboot && mmc read $kernelheader_addr_r "\ |
358 | "$kernelhdr_addr_sd $kernelhdr_size_sd " \ | |
359 | " && esbc_validate ${kernelheader_addr_r};" \ | |
d9195c62 AK |
360 | "bootm $load_addr#$BOARD\0" |
361 | ||
362 | #undef CONFIG_BOOTCOMMAND | |
363 | #if defined(CONFIG_QSPI_BOOT) | |
364 | /* Try to boot an on-QSPI kernel first, then do normal distro boot */ | |
365 | #define CONFIG_BOOTCOMMAND \ | |
30c41d21 UA |
366 | "sf read 0x80200000 0xd00000 0x100000;" \ |
367 | "env exists mcinitcmd && env exists secureboot " \ | |
368 | " && sf read 0x80780000 0x780000 0x100000 " \ | |
369 | "&& esbc_validate 0x80780000;env exists mcinitcmd " \ | |
370 | "&& fsl_mc apply dpl 0x80200000;" \ | |
371 | "run distro_bootcmd;run qspi_bootcmd;" \ | |
372 | "env exists secureboot && esbc_halt;" | |
373 | ||
d9195c62 AK |
374 | /* Try to boot an on-SD kernel first, then do normal distro boot */ |
375 | #elif defined(CONFIG_SD_BOOT) | |
376 | #define CONFIG_BOOTCOMMAND \ | |
30c41d21 UA |
377 | "env exists mcinitcmd && mmcinfo; " \ |
378 | "mmc read 0x80200000 0x6800 0x800; " \ | |
379 | "env exists mcinitcmd && env exists secureboot " \ | |
380 | " && mmc read 0x80780000 0x3800 0x10 " \ | |
381 | "&& esbc_validate 0x80780000;env exists mcinitcmd " \ | |
382 | "&& fsl_mc apply dpl 0x80200000;" \ | |
383 | "run distro_bootcmd;run sd_bootcmd;" \ | |
384 | "env exists secureboot && esbc_halt;" | |
e84a324b AK |
385 | #endif |
386 | ||
387 | /* MAC/PHY configuration */ | |
388 | #ifdef CONFIG_FSL_MC_ENET | |
389 | #define CONFIG_PHYLIB_10G | |
390 | #define CONFIG_PHY_GIGE | |
391 | #define CONFIG_PHYLIB | |
392 | ||
393 | #define CONFIG_PHY_VITESSE | |
394 | #define CONFIG_PHY_AQUANTIA | |
395 | #define AQ_PHY_ADDR1 0x00 | |
396 | #define AQR105_IRQ_MASK 0x00000004 | |
397 | ||
398 | #define QSGMII1_PORT1_PHY_ADDR 0x0c | |
399 | #define QSGMII1_PORT2_PHY_ADDR 0x0d | |
400 | #define QSGMII1_PORT3_PHY_ADDR 0x0e | |
401 | #define QSGMII1_PORT4_PHY_ADDR 0x0f | |
402 | #define QSGMII2_PORT1_PHY_ADDR 0x1c | |
403 | #define QSGMII2_PORT2_PHY_ADDR 0x1d | |
404 | #define QSGMII2_PORT3_PHY_ADDR 0x1e | |
405 | #define QSGMII2_PORT4_PHY_ADDR 0x1f | |
406 | ||
407 | #define CONFIG_MII | |
408 | #define CONFIG_ETHPRIME "DPMAC1@xgmii" | |
409 | #define CONFIG_PHY_GIGE | |
410 | #endif | |
411 | ||
412 | /* MMC */ | |
413 | #ifdef CONFIG_MMC | |
414 | #define CONFIG_FSL_ESDHC | |
415 | #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 | |
416 | #endif | |
417 | ||
418 | #undef CONFIG_CMDLINE_EDITING | |
419 | #include <config_distro_defaults.h> | |
420 | ||
421 | #define BOOT_TARGET_DEVICES(func) \ | |
e84a324b AK |
422 | func(MMC, mmc, 0) \ |
423 | func(SCSI, scsi, 0) \ | |
424 | func(DHCP, dhcp, na) | |
425 | #include <config_distro_bootcmd.h> | |
426 | ||
427 | #include <asm/fsl_secure_boot.h> | |
428 | ||
429 | #endif /* __LS1088A_RDB_H */ |