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e84a324b AK |
1 | /* |
2 | * Copyright 2017 NXP | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
6 | ||
7 | #ifndef __LS1088A_RDB_H | |
8 | #define __LS1088A_RDB_H | |
9 | ||
10 | #include "ls1088a_common.h" | |
11 | ||
10e7eaf0 | 12 | #ifndef SPL_NO_BOARDINFO |
e84a324b | 13 | #define CONFIG_DISPLAY_BOARDINFO_LATE |
10e7eaf0 | 14 | #endif |
e84a324b | 15 | |
44cdb5b6 YL |
16 | #define CONFIG_MISC_INIT_R |
17 | ||
e84a324b | 18 | #if defined(CONFIG_QSPI_BOOT) |
e84a324b | 19 | #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ |
e84a324b | 20 | #define CONFIG_ENV_SECT_SIZE 0x40000 |
099f4093 AK |
21 | #elif defined(CONFIG_SD_BOOT) |
22 | #define CONFIG_ENV_OFFSET (3 * 1024 * 1024) | |
23 | #define CONFIG_SYS_MMC_ENV_DEV 0 | |
24 | #define CONFIG_ENV_SIZE 0x2000 | |
e84a324b AK |
25 | #else |
26 | #define CONFIG_ENV_IS_IN_FLASH | |
27 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) | |
28 | #define CONFIG_ENV_SECT_SIZE 0x20000 | |
29 | #define CONFIG_ENV_SIZE 0x20000 | |
30 | #endif | |
31 | ||
099f4093 | 32 | #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) |
10e7eaf0 | 33 | #ifndef CONFIG_SPL_BUILD |
e84a324b | 34 | #define CONFIG_QIXIS_I2C_ACCESS |
10e7eaf0 | 35 | #endif |
e84a324b | 36 | #define SYS_NO_FLASH |
099f4093 | 37 | #undef CONFIG_CMD_IMLS |
e84a324b AK |
38 | #endif |
39 | ||
40 | #define CONFIG_SYS_CLK_FREQ 100000000 | |
41 | #define CONFIG_DDR_CLK_FREQ 100000000 | |
42 | #define COUNTER_FREQUENCY_REAL 25000000 /* 25MHz */ | |
43 | #define COUNTER_FREQUENCY 25000000 /* 25MHz */ | |
44 | ||
45 | #define CONFIG_DDR_SPD | |
46 | #ifdef CONFIG_EMU | |
47 | #define CONFIG_SYS_FSL_DDR_EMU | |
48 | #define CONFIG_SYS_MXC_I2C1_SPEED 40000000 | |
49 | #define CONFIG_SYS_MXC_I2C2_SPEED 40000000 | |
50 | #else | |
51 | #define CONFIG_DDR_ECC | |
52 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER | |
53 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef | |
54 | #endif | |
55 | #define SPD_EEPROM_ADDRESS 0x51 | |
56 | #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ | |
57 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
58 | ||
59 | ||
60 | #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) | |
61 | #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) | |
62 | #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) | |
63 | #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64 * 1024 * 1024) | |
64 | ||
65 | #define CONFIG_SYS_NOR0_CSPR \ | |
66 | (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ | |
67 | CSPR_PORT_SIZE_16 | \ | |
68 | CSPR_MSEL_NOR | \ | |
69 | CSPR_V) | |
70 | #define CONFIG_SYS_NOR0_CSPR_EARLY \ | |
71 | (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ | |
72 | CSPR_PORT_SIZE_16 | \ | |
73 | CSPR_MSEL_NOR | \ | |
74 | CSPR_V) | |
75 | #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(6) | |
76 | #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ | |
77 | FTIM0_NOR_TEADC(0x1) | \ | |
78 | FTIM0_NOR_TEAHC(0x1)) | |
79 | #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ | |
80 | FTIM1_NOR_TRAD_NOR(0x1)) | |
81 | #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \ | |
82 | FTIM2_NOR_TCH(0x0) | \ | |
83 | FTIM2_NOR_TWP(0x1)) | |
84 | #define CONFIG_SYS_NOR_FTIM3 0x04000000 | |
85 | #define CONFIG_SYS_IFC_CCR 0x01000000 | |
86 | ||
87 | #ifndef SYS_NO_FLASH | |
88 | #define CONFIG_FLASH_CFI_DRIVER | |
89 | #define CONFIG_SYS_FLASH_CFI | |
90 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
91 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
92 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
93 | ||
94 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
95 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
96 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
97 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
98 | ||
99 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
100 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } | |
101 | #endif | |
102 | #endif | |
10e7eaf0 SG |
103 | |
104 | #ifndef SPL_NO_IFC | |
d798a6ee | 105 | #define CONFIG_NAND_FSL_IFC |
10e7eaf0 SG |
106 | #endif |
107 | ||
e84a324b AK |
108 | #define CONFIG_SYS_NAND_MAX_ECCPOS 256 |
109 | #define CONFIG_SYS_NAND_MAX_OOBFREE 2 | |
110 | ||
111 | #define CONFIG_SYS_NAND_CSPR_EXT (0x0) | |
112 | #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | |
113 | | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ | |
114 | | CSPR_MSEL_NAND /* MSEL = NAND */ \ | |
115 | | CSPR_V) | |
116 | #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) | |
117 | ||
118 | #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | |
119 | | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | |
120 | | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | |
121 | | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ | |
122 | | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ | |
123 | | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ | |
124 | | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ | |
125 | ||
126 | #define CONFIG_SYS_NAND_ONFI_DETECTION | |
127 | ||
128 | /* ONFI NAND Flash mode0 Timing Params */ | |
129 | #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ | |
130 | FTIM0_NAND_TWP(0x18) | \ | |
131 | FTIM0_NAND_TWCHT(0x07) | \ | |
132 | FTIM0_NAND_TWH(0x0a)) | |
133 | #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ | |
134 | FTIM1_NAND_TWBE(0x39) | \ | |
135 | FTIM1_NAND_TRR(0x0e) | \ | |
136 | FTIM1_NAND_TRP(0x18)) | |
137 | #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ | |
138 | FTIM2_NAND_TREH(0x0a) | \ | |
139 | FTIM2_NAND_TWHRE(0x1e)) | |
140 | #define CONFIG_SYS_NAND_FTIM3 0x0 | |
141 | ||
142 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } | |
143 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
144 | #define CONFIG_MTD_NAND_VERIFY_WRITE | |
d798a6ee | 145 | #define CONFIG_CMD_NAND |
e84a324b AK |
146 | |
147 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) | |
148 | ||
10e7eaf0 | 149 | #ifndef SPL_NO_QIXIS |
e84a324b | 150 | #define CONFIG_FSL_QIXIS |
10e7eaf0 SG |
151 | #endif |
152 | ||
e84a324b | 153 | #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 |
ef0789b7 | 154 | #define QIXIS_BRDCFG4_OFFSET 0x54 |
e84a324b AK |
155 | #define QIXIS_LBMAP_SWITCH 2 |
156 | #define QIXIS_QMAP_MASK 0xe0 | |
157 | #define QIXIS_QMAP_SHIFT 5 | |
158 | #define QIXIS_LBMAP_MASK 0x1f | |
159 | #define QIXIS_LBMAP_SHIFT 5 | |
160 | #define QIXIS_LBMAP_DFLTBANK 0x00 | |
161 | #define QIXIS_LBMAP_ALTBANK 0x20 | |
162 | #define QIXIS_LBMAP_SD 0x00 | |
6c8945ec | 163 | #define QIXIS_LBMAP_EMMC 0x00 |
e84a324b AK |
164 | #define QIXIS_LBMAP_SD_QSPI 0x00 |
165 | #define QIXIS_LBMAP_QSPI 0x00 | |
166 | #define QIXIS_RCW_SRC_SD 0x40 | |
6c8945ec | 167 | #define QIXIS_RCW_SRC_EMMC 0x41 |
e84a324b AK |
168 | #define QIXIS_RCW_SRC_QSPI 0x62 |
169 | #define QIXIS_RST_CTL_RESET 0x31 | |
170 | #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 | |
171 | #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 | |
172 | #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 | |
173 | #define QIXIS_RST_FORCE_MEM 0x01 | |
174 | ||
175 | #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) | |
176 | #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ | |
177 | | CSPR_PORT_SIZE_8 \ | |
178 | | CSPR_MSEL_GPCM \ | |
179 | | CSPR_V) | |
180 | #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ | |
181 | | CSPR_PORT_SIZE_8 \ | |
182 | | CSPR_MSEL_GPCM \ | |
183 | | CSPR_V) | |
184 | ||
185 | #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64*1024) | |
186 | #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0) | |
187 | /* QIXIS Timing parameters*/ | |
188 | #define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ | |
189 | FTIM0_GPCM_TEADC(0x0e) | \ | |
190 | FTIM0_GPCM_TEAHC(0x0e)) | |
191 | #define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ | |
192 | FTIM1_GPCM_TRAD(0x3f)) | |
193 | #define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ | |
194 | FTIM2_GPCM_TCH(0xf) | \ | |
195 | FTIM2_GPCM_TWP(0x3E)) | |
196 | #define SYS_FPGA_CS_FTIM3 0x0 | |
197 | ||
198 | #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) | |
199 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT | |
200 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR | |
201 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK | |
202 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR | |
203 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
204 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
205 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
206 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
207 | #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT | |
208 | #define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR | |
209 | #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL | |
210 | #define CONFIG_SYS_AMASK2 CONFIG_SYS_FPGA_AMASK | |
211 | #define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR | |
212 | #define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0 | |
213 | #define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1 | |
214 | #define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2 | |
215 | #define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3 | |
216 | #else | |
217 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT | |
218 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY | |
219 | #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR | |
220 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK | |
221 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR | |
222 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
223 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
224 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
225 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
226 | #endif | |
227 | ||
228 | ||
229 | #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 | |
230 | ||
23a12cb3 RB |
231 | #define I2C_MUX_CH_VOL_MONITOR 0xA |
232 | /* Voltage monitor on channel 2*/ | |
233 | #define I2C_VOL_MONITOR_ADDR 0x63 | |
234 | #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 | |
235 | #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 | |
236 | #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 | |
ef0789b7 RB |
237 | #define I2C_SVDD_MONITOR_ADDR 0x4F |
238 | ||
239 | #define CONFIG_VID_FLS_ENV "ls1088ardb_vdd_mv" | |
240 | #define CONFIG_VID | |
241 | ||
242 | /* The lowest and highest voltage allowed for LS1088ARDB */ | |
243 | #define VDD_MV_MIN 819 | |
244 | #define VDD_MV_MAX 1212 | |
245 | ||
246 | #define CONFIG_VOL_MONITOR_LTC3882_SET | |
247 | #define CONFIG_VOL_MONITOR_LTC3882_READ | |
23a12cb3 RB |
248 | |
249 | /* PM Bus commands code for LTC3882*/ | |
250 | #define PMBUS_CMD_PAGE 0x0 | |
251 | #define PMBUS_CMD_READ_VOUT 0x8B | |
252 | #define PMBUS_CMD_PAGE_PLUS_WRITE 0x05 | |
253 | #define PMBUS_CMD_VOUT_COMMAND 0x21 | |
254 | ||
255 | #define PWM_CHANNEL0 0x0 | |
256 | ||
e84a324b AK |
257 | /* |
258 | * I2C bus multiplexer | |
259 | */ | |
260 | #define I2C_MUX_PCA_ADDR_PRI 0x77 | |
261 | #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ | |
262 | #define I2C_RETIMER_ADDR 0x18 | |
263 | #define I2C_MUX_CH_DEFAULT 0x8 | |
264 | #define I2C_MUX_CH5 0xD | |
10e7eaf0 SG |
265 | |
266 | #ifndef SPL_NO_RTC | |
e84a324b AK |
267 | /* |
268 | * RTC configuration | |
269 | */ | |
270 | #define RTC | |
271 | #define CONFIG_RTC_PCF8563 1 | |
272 | #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ | |
273 | #define CONFIG_CMD_DATE | |
10e7eaf0 | 274 | #endif |
e84a324b AK |
275 | |
276 | /* EEPROM */ | |
277 | #define CONFIG_ID_EEPROM | |
278 | #define CONFIG_SYS_I2C_EEPROM_NXID | |
279 | #define CONFIG_SYS_EEPROM_BUS_NUM 0 | |
280 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 | |
281 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
282 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
283 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 | |
284 | ||
10e7eaf0 | 285 | #ifndef SPL_NO_QSPI |
e84a324b | 286 | /* QSPI device */ |
099f4093 | 287 | #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) |
e84a324b | 288 | #define CONFIG_FSL_QSPI |
e84a324b AK |
289 | #define FSL_QSPI_FLASH_SIZE (1 << 26) |
290 | #define FSL_QSPI_FLASH_NUM 2 | |
291 | #endif | |
10e7eaf0 | 292 | #endif |
e84a324b AK |
293 | |
294 | #define CONFIG_CMD_MEMINFO | |
295 | #define CONFIG_CMD_MEMTEST | |
296 | #define CONFIG_SYS_MEMTEST_START 0x80000000 | |
297 | #define CONFIG_SYS_MEMTEST_END 0x9fffffff | |
298 | ||
099f4093 AK |
299 | #ifdef CONFIG_SPL_BUILD |
300 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE | |
301 | #else | |
e84a324b | 302 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
099f4093 | 303 | #endif |
e84a324b AK |
304 | |
305 | #define CONFIG_FSL_MEMAC | |
306 | ||
10e7eaf0 | 307 | #ifndef SPL_NO_ENV |
e84a324b AK |
308 | /* Initial environment variables */ |
309 | #if defined(CONFIG_QSPI_BOOT) | |
d9195c62 | 310 | #define MC_INIT_CMD \ |
e84a324b | 311 | "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \ |
d9195c62 | 312 | "sf read 0x80100000 0xE00000 0x100000;" \ |
30c41d21 UA |
313 | "env exists secureboot && " \ |
314 | "sf read 0x80700000 0x700000 0x40000 && " \ | |
315 | "sf read 0x80740000 0x740000 0x40000 && " \ | |
316 | "esbc_validate 0x80700000 && " \ | |
317 | "esbc_validate 0x80740000 ;" \ | |
318 | "fsl_mc start mc 0x80000000 0x80100000\0" \ | |
d9195c62 | 319 | "mcmemsize=0x70000000\0" |
099f4093 | 320 | #elif defined(CONFIG_SD_BOOT) |
d9195c62 AK |
321 | #define MC_INIT_CMD \ |
322 | "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ | |
323 | "mmc read 0x80100000 0x7000 0x800;" \ | |
30c41d21 UA |
324 | "env exists secureboot && " \ |
325 | "mmc read 0x80700000 0x3800 0x10 && " \ | |
326 | "mmc read 0x80740000 0x3A00 0x10 && " \ | |
327 | "esbc_validate 0x80700000 && " \ | |
328 | "esbc_validate 0x80740000 ;" \ | |
329 | "fsl_mc start mc 0x80000000 0x80100000\0" \ | |
d9195c62 AK |
330 | "mcmemsize=0x70000000\0" |
331 | #endif | |
332 | ||
099f4093 AK |
333 | #undef CONFIG_EXTRA_ENV_SETTINGS |
334 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
d9195c62 | 335 | "BOARD=ls1088ardb\0" \ |
099f4093 | 336 | "hwconfig=fsl_ddr:bank_intlv=auto\0" \ |
099f4093 AK |
337 | "ramdisk_addr=0x800000\0" \ |
338 | "ramdisk_size=0x2000000\0" \ | |
339 | "fdt_high=0xa0000000\0" \ | |
340 | "initrd_high=0xffffffffffffffff\0" \ | |
d9195c62 AK |
341 | "fdt_addr=0x64f00000\0" \ |
342 | "kernel_addr=0x1000000\0" \ | |
343 | "kernel_addr_sd=0x8000\0" \ | |
30c41d21 | 344 | "kernelhdr_addr_sd=0x4000\0" \ |
d9195c62 AK |
345 | "kernel_start=0x580100000\0" \ |
346 | "kernelheader_start=0x580800000\0" \ | |
347 | "scriptaddr=0x80000000\0" \ | |
348 | "scripthdraddr=0x80080000\0" \ | |
349 | "fdtheader_addr_r=0x80100000\0" \ | |
350 | "kernelheader_addr=0x800000\0" \ | |
351 | "kernelheader_addr_r=0x80200000\0" \ | |
352 | "kernel_addr_r=0x81000000\0" \ | |
353 | "kernelheader_size=0x40000\0" \ | |
354 | "fdt_addr_r=0x90000000\0" \ | |
355 | "load_addr=0xa0000000\0" \ | |
356 | "kernel_size=0x2800000\0" \ | |
357 | "kernel_size_sd=0x14000\0" \ | |
30c41d21 | 358 | "kernelhdr_size_sd=0x10\0" \ |
d9195c62 AK |
359 | MC_INIT_CMD \ |
360 | BOOTENV \ | |
361 | "boot_scripts=ls1088ardb_boot.scr\0" \ | |
362 | "boot_script_hdr=hdr_ls1088ardb_bs.out\0" \ | |
363 | "scan_dev_for_boot_part=" \ | |
364 | "part list ${devtype} ${devnum} devplist; " \ | |
365 | "env exists devplist || setenv devplist 1; " \ | |
366 | "for distro_bootpart in ${devplist}; do " \ | |
367 | "if fstype ${devtype} " \ | |
368 | "${devnum}:${distro_bootpart} " \ | |
369 | "bootfstype; then " \ | |
370 | "run scan_dev_for_boot; " \ | |
371 | "fi; " \ | |
372 | "done\0" \ | |
373 | "scan_dev_for_boot=" \ | |
374 | "echo Scanning ${devtype} " \ | |
375 | "${devnum}:${distro_bootpart}...; " \ | |
376 | "for prefix in ${boot_prefixes}; do " \ | |
377 | "run scan_dev_for_scripts; " \ | |
378 | "done;\0" \ | |
379 | "boot_a_script=" \ | |
380 | "load ${devtype} ${devnum}:${distro_bootpart} " \ | |
381 | "${scriptaddr} ${prefix}${script}; " \ | |
382 | "env exists secureboot && load ${devtype} " \ | |
383 | "${devnum}:${distro_bootpart} " \ | |
384 | "${scripthdraddr} ${prefix}${boot_script_hdr} " \ | |
385 | "&& esbc_validate ${scripthdraddr};" \ | |
386 | "source ${scriptaddr}\0" \ | |
387 | "installer=load mmc 0:2 $load_addr " \ | |
388 | "/flex_installer_arm64.itb; " \ | |
389 | "env exists mcinitcmd && run mcinitcmd && " \ | |
390 | "mmc read 0x80200000 0x6800 0x800;" \ | |
391 | "fsl_mc apply dpl 0x80200000;" \ | |
392 | "bootm $load_addr#ls1088ardb\0" \ | |
393 | "qspi_bootcmd=echo Trying load from qspi..;" \ | |
394 | "sf probe && sf read $load_addr " \ | |
30c41d21 UA |
395 | "$kernel_addr $kernel_size ; env exists secureboot " \ |
396 | "&& sf read $kernelheader_addr_r $kernelheader_addr " \ | |
397 | "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ | |
d9195c62 | 398 | "bootm $load_addr#$BOARD\0" \ |
30c41d21 | 399 | "sd_bootcmd=echo Trying load from sd card..;" \ |
d9195c62 AK |
400 | "mmcinfo; mmc read $load_addr " \ |
401 | "$kernel_addr_sd $kernel_size_sd ;" \ | |
30c41d21 UA |
402 | "env exists secureboot && mmc read $kernelheader_addr_r "\ |
403 | "$kernelhdr_addr_sd $kernelhdr_size_sd " \ | |
404 | " && esbc_validate ${kernelheader_addr_r};" \ | |
d9195c62 AK |
405 | "bootm $load_addr#$BOARD\0" |
406 | ||
407 | #undef CONFIG_BOOTCOMMAND | |
408 | #if defined(CONFIG_QSPI_BOOT) | |
409 | /* Try to boot an on-QSPI kernel first, then do normal distro boot */ | |
410 | #define CONFIG_BOOTCOMMAND \ | |
30c41d21 UA |
411 | "sf read 0x80200000 0xd00000 0x100000;" \ |
412 | "env exists mcinitcmd && env exists secureboot " \ | |
413 | " && sf read 0x80780000 0x780000 0x100000 " \ | |
414 | "&& esbc_validate 0x80780000;env exists mcinitcmd " \ | |
415 | "&& fsl_mc apply dpl 0x80200000;" \ | |
416 | "run distro_bootcmd;run qspi_bootcmd;" \ | |
417 | "env exists secureboot && esbc_halt;" | |
418 | ||
d9195c62 AK |
419 | /* Try to boot an on-SD kernel first, then do normal distro boot */ |
420 | #elif defined(CONFIG_SD_BOOT) | |
421 | #define CONFIG_BOOTCOMMAND \ | |
30c41d21 UA |
422 | "env exists mcinitcmd && mmcinfo; " \ |
423 | "mmc read 0x80200000 0x6800 0x800; " \ | |
424 | "env exists mcinitcmd && env exists secureboot " \ | |
425 | " && mmc read 0x80780000 0x3800 0x10 " \ | |
426 | "&& esbc_validate 0x80780000;env exists mcinitcmd " \ | |
427 | "&& fsl_mc apply dpl 0x80200000;" \ | |
428 | "run distro_bootcmd;run sd_bootcmd;" \ | |
429 | "env exists secureboot && esbc_halt;" | |
e84a324b AK |
430 | #endif |
431 | ||
432 | /* MAC/PHY configuration */ | |
433 | #ifdef CONFIG_FSL_MC_ENET | |
434 | #define CONFIG_PHYLIB_10G | |
435 | #define CONFIG_PHY_GIGE | |
436 | #define CONFIG_PHYLIB | |
437 | ||
438 | #define CONFIG_PHY_VITESSE | |
439 | #define CONFIG_PHY_AQUANTIA | |
440 | #define AQ_PHY_ADDR1 0x00 | |
441 | #define AQR105_IRQ_MASK 0x00000004 | |
442 | ||
443 | #define QSGMII1_PORT1_PHY_ADDR 0x0c | |
444 | #define QSGMII1_PORT2_PHY_ADDR 0x0d | |
445 | #define QSGMII1_PORT3_PHY_ADDR 0x0e | |
446 | #define QSGMII1_PORT4_PHY_ADDR 0x0f | |
447 | #define QSGMII2_PORT1_PHY_ADDR 0x1c | |
448 | #define QSGMII2_PORT2_PHY_ADDR 0x1d | |
449 | #define QSGMII2_PORT3_PHY_ADDR 0x1e | |
450 | #define QSGMII2_PORT4_PHY_ADDR 0x1f | |
451 | ||
452 | #define CONFIG_MII | |
453 | #define CONFIG_ETHPRIME "DPMAC1@xgmii" | |
454 | #define CONFIG_PHY_GIGE | |
455 | #endif | |
10e7eaf0 | 456 | #endif |
e84a324b AK |
457 | |
458 | /* MMC */ | |
459 | #ifdef CONFIG_MMC | |
460 | #define CONFIG_FSL_ESDHC | |
461 | #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 | |
462 | #endif | |
463 | ||
10e7eaf0 | 464 | #ifndef SPL_NO_ENV |
e84a324b AK |
465 | #include <config_distro_defaults.h> |
466 | ||
467 | #define BOOT_TARGET_DEVICES(func) \ | |
e84a324b AK |
468 | func(MMC, mmc, 0) \ |
469 | func(SCSI, scsi, 0) \ | |
470 | func(DHCP, dhcp, na) | |
471 | #include <config_distro_bootcmd.h> | |
10e7eaf0 | 472 | #endif |
e84a324b AK |
473 | |
474 | #include <asm/fsl_secure_boot.h> | |
475 | ||
476 | #endif /* __LS1088A_RDB_H */ |