projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| e84a324b AK |
1 | /* |
| 2 | * Copyright 2017 NXP | |
| 3 | * | |
| 4 | * SPDX-License-Identifier: GPL-2.0+ | |
| 5 | */ | |
| 6 | ||
| 7 | #ifndef __LS1088A_RDB_H | |
| 8 | #define __LS1088A_RDB_H | |
| 9 | ||
| 10 | #include "ls1088a_common.h" | |
| 11 | ||
| 12 | #define CONFIG_DISPLAY_BOARDINFO_LATE | |
| 13 | ||
| 14 | #if defined(CONFIG_QSPI_BOOT) | |
| e84a324b AK |
15 | #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ |
| 16 | #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ | |
| 17 | #define CONFIG_ENV_SECT_SIZE 0x40000 | |
| 18 | #else | |
| 19 | #define CONFIG_ENV_IS_IN_FLASH | |
| 20 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) | |
| 21 | #define CONFIG_ENV_SECT_SIZE 0x20000 | |
| 22 | #define CONFIG_ENV_SIZE 0x20000 | |
| 23 | #endif | |
| 24 | ||
| 25 | #if defined(CONFIG_QSPI_BOOT) | |
| 26 | #define CONFIG_QIXIS_I2C_ACCESS | |
| 27 | #define SYS_NO_FLASH | |
| e84a324b AK |
28 | #endif |
| 29 | ||
| 30 | #define CONFIG_SYS_CLK_FREQ 100000000 | |
| 31 | #define CONFIG_DDR_CLK_FREQ 100000000 | |
| 32 | #define COUNTER_FREQUENCY_REAL 25000000 /* 25MHz */ | |
| 33 | #define COUNTER_FREQUENCY 25000000 /* 25MHz */ | |
| 34 | ||
| 35 | #define CONFIG_DDR_SPD | |
| 36 | #ifdef CONFIG_EMU | |
| 37 | #define CONFIG_SYS_FSL_DDR_EMU | |
| 38 | #define CONFIG_SYS_MXC_I2C1_SPEED 40000000 | |
| 39 | #define CONFIG_SYS_MXC_I2C2_SPEED 40000000 | |
| 40 | #else | |
| 41 | #define CONFIG_DDR_ECC | |
| 42 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER | |
| 43 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef | |
| 44 | #endif | |
| 45 | #define SPD_EEPROM_ADDRESS 0x51 | |
| 46 | #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ | |
| 47 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
| 48 | ||
| 49 | ||
| 50 | #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) | |
| 51 | #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) | |
| 52 | #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) | |
| 53 | #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64 * 1024 * 1024) | |
| 54 | ||
| 55 | #define CONFIG_SYS_NOR0_CSPR \ | |
| 56 | (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ | |
| 57 | CSPR_PORT_SIZE_16 | \ | |
| 58 | CSPR_MSEL_NOR | \ | |
| 59 | CSPR_V) | |
| 60 | #define CONFIG_SYS_NOR0_CSPR_EARLY \ | |
| 61 | (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ | |
| 62 | CSPR_PORT_SIZE_16 | \ | |
| 63 | CSPR_MSEL_NOR | \ | |
| 64 | CSPR_V) | |
| 65 | #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(6) | |
| 66 | #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ | |
| 67 | FTIM0_NOR_TEADC(0x1) | \ | |
| 68 | FTIM0_NOR_TEAHC(0x1)) | |
| 69 | #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ | |
| 70 | FTIM1_NOR_TRAD_NOR(0x1)) | |
| 71 | #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \ | |
| 72 | FTIM2_NOR_TCH(0x0) | \ | |
| 73 | FTIM2_NOR_TWP(0x1)) | |
| 74 | #define CONFIG_SYS_NOR_FTIM3 0x04000000 | |
| 75 | #define CONFIG_SYS_IFC_CCR 0x01000000 | |
| 76 | ||
| 77 | #ifndef SYS_NO_FLASH | |
| 78 | #define CONFIG_FLASH_CFI_DRIVER | |
| 79 | #define CONFIG_SYS_FLASH_CFI | |
| 80 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
| 81 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
| 82 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
| 83 | ||
| 84 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
| 85 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
| 86 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
| 87 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
| 88 | ||
| 89 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
| 90 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } | |
| 91 | #endif | |
| 92 | #endif | |
| 93 | #define CONFIG_SYS_NAND_MAX_ECCPOS 256 | |
| 94 | #define CONFIG_SYS_NAND_MAX_OOBFREE 2 | |
| 95 | ||
| 96 | #define CONFIG_SYS_NAND_CSPR_EXT (0x0) | |
| 97 | #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | |
| 98 | | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ | |
| 99 | | CSPR_MSEL_NAND /* MSEL = NAND */ \ | |
| 100 | | CSPR_V) | |
| 101 | #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) | |
| 102 | ||
| 103 | #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | |
| 104 | | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | |
| 105 | | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | |
| 106 | | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ | |
| 107 | | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ | |
| 108 | | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ | |
| 109 | | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ | |
| 110 | ||
| 111 | #define CONFIG_SYS_NAND_ONFI_DETECTION | |
| 112 | ||
| 113 | /* ONFI NAND Flash mode0 Timing Params */ | |
| 114 | #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ | |
| 115 | FTIM0_NAND_TWP(0x18) | \ | |
| 116 | FTIM0_NAND_TWCHT(0x07) | \ | |
| 117 | FTIM0_NAND_TWH(0x0a)) | |
| 118 | #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ | |
| 119 | FTIM1_NAND_TWBE(0x39) | \ | |
| 120 | FTIM1_NAND_TRR(0x0e) | \ | |
| 121 | FTIM1_NAND_TRP(0x18)) | |
| 122 | #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ | |
| 123 | FTIM2_NAND_TREH(0x0a) | \ | |
| 124 | FTIM2_NAND_TWHRE(0x1e)) | |
| 125 | #define CONFIG_SYS_NAND_FTIM3 0x0 | |
| 126 | ||
| 127 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } | |
| 128 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
| 129 | #define CONFIG_MTD_NAND_VERIFY_WRITE | |
| 130 | ||
| 131 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) | |
| 132 | ||
| 133 | #define CONFIG_FSL_QIXIS | |
| 134 | #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 | |
| 135 | #define QIXIS_LBMAP_SWITCH 2 | |
| 136 | #define QIXIS_QMAP_MASK 0xe0 | |
| 137 | #define QIXIS_QMAP_SHIFT 5 | |
| 138 | #define QIXIS_LBMAP_MASK 0x1f | |
| 139 | #define QIXIS_LBMAP_SHIFT 5 | |
| 140 | #define QIXIS_LBMAP_DFLTBANK 0x00 | |
| 141 | #define QIXIS_LBMAP_ALTBANK 0x20 | |
| 142 | #define QIXIS_LBMAP_SD 0x00 | |
| 143 | #define QIXIS_LBMAP_SD_QSPI 0x00 | |
| 144 | #define QIXIS_LBMAP_QSPI 0x00 | |
| 145 | #define QIXIS_RCW_SRC_SD 0x40 | |
| 146 | #define QIXIS_RCW_SRC_QSPI 0x62 | |
| 147 | #define QIXIS_RST_CTL_RESET 0x31 | |
| 148 | #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 | |
| 149 | #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 | |
| 150 | #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 | |
| 151 | #define QIXIS_RST_FORCE_MEM 0x01 | |
| 152 | ||
| 153 | #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) | |
| 154 | #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ | |
| 155 | | CSPR_PORT_SIZE_8 \ | |
| 156 | | CSPR_MSEL_GPCM \ | |
| 157 | | CSPR_V) | |
| 158 | #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ | |
| 159 | | CSPR_PORT_SIZE_8 \ | |
| 160 | | CSPR_MSEL_GPCM \ | |
| 161 | | CSPR_V) | |
| 162 | ||
| 163 | #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64*1024) | |
| 164 | #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0) | |
| 165 | /* QIXIS Timing parameters*/ | |
| 166 | #define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ | |
| 167 | FTIM0_GPCM_TEADC(0x0e) | \ | |
| 168 | FTIM0_GPCM_TEAHC(0x0e)) | |
| 169 | #define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ | |
| 170 | FTIM1_GPCM_TRAD(0x3f)) | |
| 171 | #define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ | |
| 172 | FTIM2_GPCM_TCH(0xf) | \ | |
| 173 | FTIM2_GPCM_TWP(0x3E)) | |
| 174 | #define SYS_FPGA_CS_FTIM3 0x0 | |
| 175 | ||
| 176 | #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) | |
| 177 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT | |
| 178 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR | |
| 179 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK | |
| 180 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR | |
| 181 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
| 182 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
| 183 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
| 184 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
| 185 | #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT | |
| 186 | #define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR | |
| 187 | #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL | |
| 188 | #define CONFIG_SYS_AMASK2 CONFIG_SYS_FPGA_AMASK | |
| 189 | #define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR | |
| 190 | #define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0 | |
| 191 | #define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1 | |
| 192 | #define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2 | |
| 193 | #define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3 | |
| 194 | #else | |
| 195 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT | |
| 196 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY | |
| 197 | #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR | |
| 198 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK | |
| 199 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR | |
| 200 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
| 201 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
| 202 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
| 203 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
| 204 | #endif | |
| 205 | ||
| 206 | ||
| 207 | #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 | |
| 208 | ||
| 209 | /* | |
| 210 | * I2C bus multiplexer | |
| 211 | */ | |
| 212 | #define I2C_MUX_PCA_ADDR_PRI 0x77 | |
| 213 | #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ | |
| 214 | #define I2C_RETIMER_ADDR 0x18 | |
| 215 | #define I2C_MUX_CH_DEFAULT 0x8 | |
| 216 | #define I2C_MUX_CH5 0xD | |
| 217 | /* | |
| 218 | * RTC configuration | |
| 219 | */ | |
| 220 | #define RTC | |
| 221 | #define CONFIG_RTC_PCF8563 1 | |
| 222 | #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ | |
| 223 | #define CONFIG_CMD_DATE | |
| 224 | ||
| 225 | /* EEPROM */ | |
| 226 | #define CONFIG_ID_EEPROM | |
| 227 | #define CONFIG_SYS_I2C_EEPROM_NXID | |
| 228 | #define CONFIG_SYS_EEPROM_BUS_NUM 0 | |
| 229 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 | |
| 230 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
| 231 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
| 232 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 | |
| 233 | ||
| 234 | /* QSPI device */ | |
| 235 | #if defined(CONFIG_QSPI_BOOT) | |
| 236 | #define CONFIG_FSL_QSPI | |
| 237 | #define CONFIG_SPI_FLASH_SPANSION | |
| 238 | #define FSL_QSPI_FLASH_SIZE (1 << 26) | |
| 239 | #define FSL_QSPI_FLASH_NUM 2 | |
| 240 | #endif | |
| 241 | ||
| 242 | #define CONFIG_CMD_MEMINFO | |
| 243 | #define CONFIG_CMD_MEMTEST | |
| 244 | #define CONFIG_SYS_MEMTEST_START 0x80000000 | |
| 245 | #define CONFIG_SYS_MEMTEST_END 0x9fffffff | |
| 246 | ||
| 247 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE | |
| 248 | ||
| 249 | #define CONFIG_FSL_MEMAC | |
| 250 | ||
| 251 | /* Initial environment variables */ | |
| 252 | #if defined(CONFIG_QSPI_BOOT) | |
| 253 | #undef CONFIG_EXTRA_ENV_SETTINGS | |
| 254 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 255 | "hwconfig=fsl_ddr:bank_intlv=auto\0" \ | |
| 256 | "loadaddr=0x90100000\0" \ | |
| 257 | "kernel_addr=0x100000\0" \ | |
| 258 | "ramdisk_addr=0x800000\0" \ | |
| 259 | "ramdisk_size=0x2000000\0" \ | |
| 260 | "fdt_high=0xa0000000\0" \ | |
| 261 | "initrd_high=0xffffffffffffffff\0" \ | |
| 262 | "kernel_start=0x1000000\0" \ | |
| 263 | "kernel_load=0xa0000000\0" \ | |
| 264 | "kernel_size=0x2800000\0" \ | |
| 265 | "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \ | |
| 266 | "sf read 0x80100000 0xE00000 0x100000;" \ | |
| 267 | "fsl_mc start mc 0x80000000 0x80100000\0" \ | |
| 268 | "mcmemsize=0x70000000 \0" | |
| 269 | ||
| 270 | #endif | |
| 271 | ||
| 272 | /* MAC/PHY configuration */ | |
| 273 | #ifdef CONFIG_FSL_MC_ENET | |
| 274 | #define CONFIG_PHYLIB_10G | |
| 275 | #define CONFIG_PHY_GIGE | |
| 276 | #define CONFIG_PHYLIB | |
| 277 | ||
| 278 | #define CONFIG_PHY_VITESSE | |
| 279 | #define CONFIG_PHY_AQUANTIA | |
| 280 | #define AQ_PHY_ADDR1 0x00 | |
| 281 | #define AQR105_IRQ_MASK 0x00000004 | |
| 282 | ||
| 283 | #define QSGMII1_PORT1_PHY_ADDR 0x0c | |
| 284 | #define QSGMII1_PORT2_PHY_ADDR 0x0d | |
| 285 | #define QSGMII1_PORT3_PHY_ADDR 0x0e | |
| 286 | #define QSGMII1_PORT4_PHY_ADDR 0x0f | |
| 287 | #define QSGMII2_PORT1_PHY_ADDR 0x1c | |
| 288 | #define QSGMII2_PORT2_PHY_ADDR 0x1d | |
| 289 | #define QSGMII2_PORT3_PHY_ADDR 0x1e | |
| 290 | #define QSGMII2_PORT4_PHY_ADDR 0x1f | |
| 291 | ||
| 292 | #define CONFIG_MII | |
| 293 | #define CONFIG_ETHPRIME "DPMAC1@xgmii" | |
| 294 | #define CONFIG_PHY_GIGE | |
| 295 | #endif | |
| 296 | ||
| 297 | /* MMC */ | |
| 298 | #ifdef CONFIG_MMC | |
| 299 | #define CONFIG_FSL_ESDHC | |
| 300 | #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 | |
| 301 | #endif | |
| 302 | ||
| 303 | #undef CONFIG_CMDLINE_EDITING | |
| 304 | #include <config_distro_defaults.h> | |
| 305 | ||
| 306 | #define BOOT_TARGET_DEVICES(func) \ | |
| 307 | func(USB, usb, 0) \ | |
| 308 | func(MMC, mmc, 0) \ | |
| 309 | func(SCSI, scsi, 0) \ | |
| 310 | func(DHCP, dhcp, na) | |
| 311 | #include <config_distro_bootcmd.h> | |
| 312 | ||
| 313 | #include <asm/fsl_secure_boot.h> | |
| 314 | ||
| 315 | #endif /* __LS1088A_RDB_H */ |