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Commit | Line | Data |
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7288c2c2 | 1 | /* |
89a168f7 | 2 | * Copyright 2017 NXP |
7288c2c2 YS |
3 | * Copyright 2015 Freescale Semiconductor |
4 | * | |
5 | * SPDX-License-Identifier: GPL-2.0+ | |
6 | */ | |
7 | ||
8 | #ifndef __LS2_QDS_H | |
9 | #define __LS2_QDS_H | |
10 | ||
44937214 | 11 | #include "ls2080a_common.h" |
7288c2c2 | 12 | |
7288c2c2 YS |
13 | #ifndef __ASSEMBLY__ |
14 | unsigned long get_board_sys_clk(void); | |
15 | unsigned long get_board_ddr_clk(void); | |
16 | #endif | |
17 | ||
8c77ef85 | 18 | #ifdef CONFIG_FSL_QSPI |
8c77ef85 YY |
19 | #define CONFIG_QIXIS_I2C_ACCESS |
20 | #define CONFIG_SYS_I2C_EARLY_INIT | |
21 | #define CONFIG_SYS_I2C_IFDR_DIV 0x7e | |
22 | #endif | |
23 | ||
24 | #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 | |
7288c2c2 YS |
25 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() |
26 | #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() | |
27 | #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) | |
28 | ||
29 | #define CONFIG_DDR_SPD | |
30 | #define CONFIG_DDR_ECC | |
31 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER | |
32 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef | |
33 | #define SPD_EEPROM_ADDRESS1 0x51 | |
34 | #define SPD_EEPROM_ADDRESS2 0x52 | |
35 | #define SPD_EEPROM_ADDRESS3 0x53 | |
36 | #define SPD_EEPROM_ADDRESS4 0x54 | |
37 | #define SPD_EEPROM_ADDRESS5 0x55 | |
38 | #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */ | |
39 | #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 | |
40 | #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ | |
41 | #define CONFIG_DIMM_SLOTS_PER_CTLR 2 | |
42 | #define CONFIG_CHIP_SELECTS_PER_CTRL 4 | |
44937214 | 43 | #ifdef CONFIG_SYS_FSL_HAS_DP_DDR |
7288c2c2 | 44 | #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 |
44937214 | 45 | #endif |
7288c2c2 YS |
46 | #define CONFIG_FSL_DDR_BIST /* enable built-in memory test */ |
47 | ||
989c5f0a | 48 | /* SATA */ |
989c5f0a | 49 | #define CONFIG_SCSI_AHCI_PLAT |
989c5f0a TY |
50 | |
51 | #define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 | |
52 | #define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2 | |
53 | ||
54 | #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 | |
55 | #define CONFIG_SYS_SCSI_MAX_LUN 1 | |
56 | #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ | |
57 | CONFIG_SYS_SCSI_MAX_LUN) | |
58 | ||
7288c2c2 YS |
59 | /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */ |
60 | ||
61 | #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) | |
62 | #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) | |
63 | #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) | |
64 | ||
65 | #define CONFIG_SYS_NOR0_CSPR \ | |
66 | (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ | |
67 | CSPR_PORT_SIZE_16 | \ | |
68 | CSPR_MSEL_NOR | \ | |
69 | CSPR_V) | |
70 | #define CONFIG_SYS_NOR0_CSPR_EARLY \ | |
71 | (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ | |
72 | CSPR_PORT_SIZE_16 | \ | |
73 | CSPR_MSEL_NOR | \ | |
74 | CSPR_V) | |
75 | #define CONFIG_SYS_NOR1_CSPR \ | |
76 | (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \ | |
77 | CSPR_PORT_SIZE_16 | \ | |
78 | CSPR_MSEL_NOR | \ | |
79 | CSPR_V) | |
80 | #define CONFIG_SYS_NOR1_CSPR_EARLY \ | |
81 | (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \ | |
82 | CSPR_PORT_SIZE_16 | \ | |
83 | CSPR_MSEL_NOR | \ | |
84 | CSPR_V) | |
85 | #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) | |
86 | #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ | |
87 | FTIM0_NOR_TEADC(0x5) | \ | |
88 | FTIM0_NOR_TEAHC(0x5)) | |
89 | #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ | |
90 | FTIM1_NOR_TRAD_NOR(0x1a) |\ | |
91 | FTIM1_NOR_TSEQRAD_NOR(0x13)) | |
92 | #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ | |
93 | FTIM2_NOR_TCH(0x4) | \ | |
94 | FTIM2_NOR_TWPH(0x0E) | \ | |
95 | FTIM2_NOR_TWP(0x1c)) | |
96 | #define CONFIG_SYS_NOR_FTIM3 0x04000000 | |
97 | #define CONFIG_SYS_IFC_CCR 0x01000000 | |
98 | ||
e856bdcf | 99 | #ifdef CONFIG_MTD_NOR_FLASH |
7288c2c2 YS |
100 | #define CONFIG_FLASH_CFI_DRIVER |
101 | #define CONFIG_SYS_FLASH_CFI | |
102 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
103 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
104 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
105 | ||
106 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ | |
107 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
108 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
109 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
110 | ||
111 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
112 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ | |
113 | CONFIG_SYS_FLASH_BASE + 0x40000000} | |
114 | #endif | |
115 | ||
116 | #define CONFIG_NAND_FSL_IFC | |
117 | #define CONFIG_SYS_NAND_MAX_ECCPOS 256 | |
118 | #define CONFIG_SYS_NAND_MAX_OOBFREE 2 | |
119 | ||
7288c2c2 YS |
120 | #define CONFIG_SYS_NAND_CSPR_EXT (0x0) |
121 | #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | |
122 | | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ | |
123 | | CSPR_MSEL_NAND /* MSEL = NAND */ \ | |
124 | | CSPR_V) | |
125 | #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) | |
126 | ||
127 | #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | |
128 | | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | |
129 | | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | |
130 | | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ | |
131 | | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ | |
132 | | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ | |
133 | | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ | |
134 | ||
135 | #define CONFIG_SYS_NAND_ONFI_DETECTION | |
136 | ||
137 | /* ONFI NAND Flash mode0 Timing Params */ | |
138 | #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ | |
139 | FTIM0_NAND_TWP(0x18) | \ | |
140 | FTIM0_NAND_TWCHT(0x07) | \ | |
141 | FTIM0_NAND_TWH(0x0a)) | |
142 | #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ | |
143 | FTIM1_NAND_TWBE(0x39) | \ | |
144 | FTIM1_NAND_TRR(0x0e) | \ | |
145 | FTIM1_NAND_TRP(0x18)) | |
146 | #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ | |
147 | FTIM2_NAND_TREH(0x0a) | \ | |
148 | FTIM2_NAND_TWHRE(0x1e)) | |
149 | #define CONFIG_SYS_NAND_FTIM3 0x0 | |
150 | ||
151 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } | |
152 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
153 | #define CONFIG_MTD_NAND_VERIFY_WRITE | |
7288c2c2 YS |
154 | |
155 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) | |
156 | ||
157 | #define CONFIG_FSL_QIXIS /* use common QIXIS code */ | |
158 | #define QIXIS_LBMAP_SWITCH 0x06 | |
159 | #define QIXIS_LBMAP_MASK 0x0f | |
160 | #define QIXIS_LBMAP_SHIFT 0 | |
161 | #define QIXIS_LBMAP_DFLTBANK 0x00 | |
162 | #define QIXIS_LBMAP_ALTBANK 0x04 | |
b2d5ac59 | 163 | #define QIXIS_LBMAP_NAND 0x09 |
1f55a938 | 164 | #define QIXIS_LBMAP_SD 0x00 |
a646f669 | 165 | #define QIXIS_LBMAP_QSPI 0x0f |
7288c2c2 YS |
166 | #define QIXIS_RST_CTL_RESET 0x31 |
167 | #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 | |
168 | #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 | |
169 | #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 | |
b2d5ac59 | 170 | #define QIXIS_RCW_SRC_NAND 0x107 |
1f55a938 | 171 | #define QIXIS_RCW_SRC_SD 0x40 |
a646f669 | 172 | #define QIXIS_RCW_SRC_QSPI 0x62 |
7288c2c2 YS |
173 | #define QIXIS_RST_FORCE_MEM 0x01 |
174 | ||
175 | #define CONFIG_SYS_CSPR3_EXT (0x0) | |
176 | #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ | |
177 | | CSPR_PORT_SIZE_8 \ | |
178 | | CSPR_MSEL_GPCM \ | |
179 | | CSPR_V) | |
180 | #define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ | |
181 | | CSPR_PORT_SIZE_8 \ | |
182 | | CSPR_MSEL_GPCM \ | |
183 | | CSPR_V) | |
184 | ||
185 | #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) | |
186 | #define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12) | |
187 | /* QIXIS Timing parameters for IFC CS3 */ | |
188 | #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ | |
189 | FTIM0_GPCM_TEADC(0x0e) | \ | |
190 | FTIM0_GPCM_TEAHC(0x0e)) | |
191 | #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ | |
192 | FTIM1_GPCM_TRAD(0x3f)) | |
193 | #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ | |
194 | FTIM2_GPCM_TCH(0xf) | \ | |
195 | FTIM2_GPCM_TWP(0x3E)) | |
196 | #define CONFIG_SYS_CS3_FTIM3 0x0 | |
197 | ||
faed6bde SK |
198 | #if defined(CONFIG_SPL) |
199 | #if defined(CONFIG_NAND_BOOT) | |
b2d5ac59 SW |
200 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT |
201 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR_EARLY | |
202 | #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR0_CSPR | |
203 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK | |
204 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR | |
205 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
206 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
207 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
208 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
209 | #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT | |
210 | #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR_EARLY | |
211 | #define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR1_CSPR | |
212 | #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK_EARLY | |
213 | #define CONFIG_SYS_AMASK2_FINAL CONFIG_SYS_NOR_AMASK | |
214 | #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR | |
215 | #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
216 | #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
217 | #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
218 | #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
219 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT | |
220 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR | |
221 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK | |
222 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR | |
223 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
224 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
225 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
226 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
227 | ||
b2d5ac59 SW |
228 | #define CONFIG_ENV_OFFSET (896 * 1024) |
229 | #define CONFIG_ENV_SECT_SIZE 0x20000 | |
230 | #define CONFIG_ENV_SIZE 0x2000 | |
231 | #define CONFIG_SPL_PAD_TO 0x20000 | |
232 | #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 * 1024) | |
74cac00c | 233 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 * 1024) |
1f55a938 | 234 | #elif defined(CONFIG_SD_BOOT) |
0f4e1ace | 235 | #define CONFIG_ENV_OFFSET 0x300000 |
1f55a938 SK |
236 | #define CONFIG_SYS_MMC_ENV_DEV 0 |
237 | #define CONFIG_ENV_SIZE 0x20000 | |
faed6bde | 238 | #endif |
b2d5ac59 | 239 | #else |
7288c2c2 YS |
240 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT |
241 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY | |
242 | #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR | |
243 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK | |
244 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR | |
245 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
246 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
247 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
248 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
249 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT | |
250 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY | |
251 | #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR | |
252 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY | |
253 | #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK | |
254 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR | |
255 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
256 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
257 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
258 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
259 | #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT | |
260 | #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR | |
261 | #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK | |
262 | #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR | |
263 | #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
264 | #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
265 | #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
266 | #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
267 | ||
89a168f7 | 268 | #ifndef CONFIG_QSPI_BOOT |
f5bf23d8 | 269 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) |
b2d5ac59 SW |
270 | #define CONFIG_ENV_SECT_SIZE 0x20000 |
271 | #define CONFIG_ENV_SIZE 0x2000 | |
272 | #endif | |
a646f669 | 273 | #endif |
b2d5ac59 | 274 | |
7288c2c2 YS |
275 | /* Debug Server firmware */ |
276 | #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR | |
277 | #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL | |
278 | ||
7288c2c2 YS |
279 | #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 |
280 | ||
281 | /* | |
282 | * I2C | |
283 | */ | |
284 | #define I2C_MUX_PCA_ADDR 0x77 | |
285 | #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ | |
286 | ||
287 | /* I2C bus multiplexer */ | |
288 | #define I2C_MUX_CH_DEFAULT 0x8 | |
289 | ||
b7774b05 | 290 | /* SPI */ |
b718d371 | 291 | #if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI) |
b7774b05 | 292 | #define CONFIG_SPI_FLASH |
b718d371 YY |
293 | |
294 | #ifdef CONFIG_FSL_DSPI | |
295 | #define CONFIG_SPI_FLASH_STMICRO | |
296 | #define CONFIG_SPI_FLASH_SST | |
297 | #define CONFIG_SPI_FLASH_EON | |
298 | #endif | |
299 | ||
300 | #ifdef CONFIG_FSL_QSPI | |
301 | #define CONFIG_SPI_FLASH_SPANSION | |
302 | #define FSL_QSPI_FLASH_SIZE (1 << 26) /* 64MB */ | |
303 | #define FSL_QSPI_FLASH_NUM 4 | |
304 | #endif | |
453418f2 YY |
305 | /* |
306 | * Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure. | |
307 | * If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0 | |
308 | * If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1 | |
309 | */ | |
310 | #define FSL_QIXIS_BRDCFG9_QSPI 0x1 | |
b718d371 | 311 | |
b7774b05 HW |
312 | #endif |
313 | ||
8b06460e YL |
314 | /* |
315 | * MMC | |
316 | */ | |
317 | #ifdef CONFIG_MMC | |
318 | #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \ | |
319 | QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER) | |
320 | #endif | |
321 | ||
7288c2c2 YS |
322 | /* |
323 | * RTC configuration | |
324 | */ | |
325 | #define RTC | |
326 | #define CONFIG_RTC_DS3231 1 | |
327 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 | |
328 | ||
329 | /* EEPROM */ | |
330 | #define CONFIG_ID_EEPROM | |
7288c2c2 YS |
331 | #define CONFIG_SYS_I2C_EEPROM_NXID |
332 | #define CONFIG_SYS_EEPROM_BUS_NUM 0 | |
333 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 | |
334 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
335 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
336 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 | |
337 | ||
7288c2c2 | 338 | #define CONFIG_FSL_MEMAC |
7288c2c2 YS |
339 | |
340 | #ifdef CONFIG_PCI | |
7288c2c2 | 341 | #define CONFIG_PCI_SCAN_SHOW |
7288c2c2 YS |
342 | #endif |
343 | ||
8b06460e | 344 | /* MMC */ |
8b06460e | 345 | #ifdef CONFIG_MMC |
8b06460e YL |
346 | #define CONFIG_FSL_ESDHC |
347 | #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 | |
8b06460e | 348 | #endif |
7288c2c2 YS |
349 | |
350 | /* Initial environment variables */ | |
351 | #undef CONFIG_EXTRA_ENV_SETTINGS | |
9ed44787 | 352 | #ifdef CONFIG_SECURE_BOOT |
7288c2c2 YS |
353 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
354 | "hwconfig=fsl_ddr:bank_intlv=auto\0" \ | |
355 | "loadaddr=0x80100000\0" \ | |
356 | "kernel_addr=0x100000\0" \ | |
357 | "ramdisk_addr=0x800000\0" \ | |
358 | "ramdisk_size=0x2000000\0" \ | |
359 | "fdt_high=0xa0000000\0" \ | |
360 | "initrd_high=0xffffffffffffffff\0" \ | |
7676074a | 361 | "kernel_start=0x581000000\0" \ |
7288c2c2 | 362 | "kernel_load=0xa0000000\0" \ |
16ed8560 | 363 | "kernel_size=0x2800000\0" \ |
6d7b9e78 | 364 | "mcmemsize=0x40000000\0" \ |
7676074a UA |
365 | "mcinitcmd=esbc_validate 0x580700000;" \ |
366 | "esbc_validate 0x580740000;" \ | |
367 | "fsl_mc start mc 0x580a00000" \ | |
368 | " 0x580e00000 \0" | |
1f55a938 SK |
369 | #elif defined(CONFIG_SD_BOOT) |
370 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
371 | "hwconfig=fsl_ddr:bank_intlv=auto\0" \ | |
372 | "loadaddr=0x90100000\0" \ | |
373 | "kernel_addr=0x800\0" \ | |
374 | "ramdisk_addr=0x800000\0" \ | |
375 | "ramdisk_size=0x2000000\0" \ | |
376 | "fdt_high=0xa0000000\0" \ | |
377 | "initrd_high=0xffffffffffffffff\0" \ | |
378 | "kernel_start=0x8000\0" \ | |
379 | "kernel_load=0xa0000000\0" \ | |
380 | "kernel_size=0x14000\0" \ | |
381 | "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ | |
382 | "mmc read 0x80100000 0x7000 0x800;" \ | |
383 | "fsl_mc start mc 0x80000000 0x80100000\0" \ | |
384 | "mcmemsize=0x70000000 \0" | |
9ed44787 UA |
385 | #else |
386 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
387 | "hwconfig=fsl_ddr:bank_intlv=auto\0" \ | |
388 | "loadaddr=0x80100000\0" \ | |
389 | "kernel_addr=0x100000\0" \ | |
390 | "ramdisk_addr=0x800000\0" \ | |
391 | "ramdisk_size=0x2000000\0" \ | |
392 | "fdt_high=0xa0000000\0" \ | |
393 | "initrd_high=0xffffffffffffffff\0" \ | |
f5bf23d8 | 394 | "kernel_start=0x581000000\0" \ |
9ed44787 UA |
395 | "kernel_load=0xa0000000\0" \ |
396 | "kernel_size=0x2800000\0" \ | |
6d7b9e78 | 397 | "mcmemsize=0x40000000\0" \ |
f5bf23d8 SK |
398 | "mcinitcmd=fsl_mc start mc 0x580a00000" \ |
399 | " 0x580e00000 \0" | |
9ed44787 UA |
400 | #endif /* CONFIG_SECURE_BOOT */ |
401 | ||
7288c2c2 | 402 | |
1f55a938 | 403 | #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) |
e60476a0 | 404 | #define CONFIG_FSL_MEMAC |
e60476a0 | 405 | #define CONFIG_PHYLIB_10G |
e60476a0 PK |
406 | #define CONFIG_PHY_VITESSE |
407 | #define CONFIG_PHY_REALTEK | |
408 | #define CONFIG_PHY_TERANETICS | |
409 | #define SGMII_CARD_PORT1_PHY_ADDR 0x1C | |
410 | #define SGMII_CARD_PORT2_PHY_ADDR 0x1d | |
411 | #define SGMII_CARD_PORT3_PHY_ADDR 0x1E | |
412 | #define SGMII_CARD_PORT4_PHY_ADDR 0x1F | |
413 | ||
cf7ee6c4 PK |
414 | #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0 |
415 | #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1 | |
416 | #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2 | |
417 | #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3 | |
418 | #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4 | |
419 | #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5 | |
420 | #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6 | |
421 | #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7 | |
422 | #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8 | |
423 | #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9 | |
424 | #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa | |
425 | #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb | |
426 | #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc | |
427 | #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd | |
428 | #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe | |
429 | #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf | |
430 | ||
e60476a0 | 431 | #define CONFIG_MII /* MII PHY management */ |
7ad9cc96 | 432 | #define CONFIG_ETHPRIME "DPMAC1@xgmii" |
e60476a0 PK |
433 | |
434 | #endif | |
435 | ||
fcfdb6d5 SJ |
436 | #include <asm/fsl_secure_boot.h> |
437 | ||
7288c2c2 | 438 | #endif /* __LS2_QDS_H */ |