[people/ms/u-boot.git] / include / configs / ls2080ardb.h

/*
 * Copyright 2017 NXP
 * Copyright 2015 Freescale Semiconductor
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __LS2_RDB_H
#define __LS2_RDB_H

#include "ls2080a_common.h"

#undef CONFIG_CONS_INDEX
#define CONFIG_CONS_INDEX       2

#ifdef CONFIG_FSL_QSPI
#ifdef CONFIG_TARGET_LS2081ARDB
#define CONFIG_QIXIS_I2C_ACCESS
#endif
#define CONFIG_SYS_I2C_EARLY_INIT
#define CONFIG_DISPLAY_BOARDINFO_LATE
#endif

#define I2C_MUX_CH_VOL_MONITOR		0xa
#define I2C_VOL_MONITOR_ADDR		0x38
#define CONFIG_VOL_MONITOR_IR36021_READ
#define CONFIG_VOL_MONITOR_IR36021_SET

#define CONFIG_VID_FLS_ENV		"ls2080ardb_vdd_mv"
#ifndef CONFIG_SPL_BUILD
#define CONFIG_VID
#endif
/* step the IR regulator in 5mV increments */
#define IR_VDD_STEP_DOWN		5
#define IR_VDD_STEP_UP			5
/* The lowest and highest voltage allowed for LS2080ARDB */
#define VDD_MV_MIN			819
#define VDD_MV_MAX			1212

#ifndef __ASSEMBLY__
unsigned long get_board_sys_clk(void);
#endif

#define CONFIG_SYS_CLK_FREQ		get_board_sys_clk()
#define CONFIG_DDR_CLK_FREQ		133333333
#define COUNTER_FREQUENCY_REAL		(CONFIG_SYS_CLK_FREQ/4)

#define CONFIG_DDR_SPD
#define CONFIG_DDR_ECC
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
#define SPD_EEPROM_ADDRESS1	0x51
#define SPD_EEPROM_ADDRESS2	0x52
#define SPD_EEPROM_ADDRESS3	0x53
#define SPD_EEPROM_ADDRESS4	0x54
#define SPD_EEPROM_ADDRESS5	0x55
#define SPD_EEPROM_ADDRESS6	0x56	/* dummy address */
#define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1
#define CONFIG_SYS_SPD_BUS_NUM	0	/* SPD on I2C bus 0 */
#define CONFIG_DIMM_SLOTS_PER_CTLR		2
#define CONFIG_CHIP_SELECTS_PER_CTRL		4
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR	1
#endif
#define CONFIG_FSL_DDR_BIST	/* enable built-in memory test */

/* SATA */
#define CONFIG_LIBATA
#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT

#define CONFIG_SYS_SATA1			AHCI_BASE_ADDR1
#define CONFIG_SYS_SATA2			AHCI_BASE_ADDR2

#define CONFIG_SYS_SCSI_MAX_SCSI_ID		1
#define CONFIG_SYS_SCSI_MAX_LUN			1
#define CONFIG_SYS_SCSI_MAX_DEVICE		(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
						CONFIG_SYS_SCSI_MAX_LUN)

#ifndef CONFIG_FSL_QSPI
/* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */

#define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
#define CONFIG_SYS_NOR_AMASK		IFC_AMASK(128*1024*1024)
#define CONFIG_SYS_NOR_AMASK_EARLY	IFC_AMASK(64*1024*1024)

#define CONFIG_SYS_NOR0_CSPR					\
	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)		| \
	CSPR_PORT_SIZE_16					| \
	CSPR_MSEL_NOR						| \
	CSPR_V)
#define CONFIG_SYS_NOR0_CSPR_EARLY				\
	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)	| \
	CSPR_PORT_SIZE_16					| \
	CSPR_MSEL_NOR						| \
	CSPR_V)
#define CONFIG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(12)
#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
				FTIM0_NOR_TEADC(0x5) | \
				FTIM0_NOR_TEAHC(0x5))
#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
				FTIM1_NOR_TRAD_NOR(0x1a) |\
				FTIM1_NOR_TSEQRAD_NOR(0x13))
#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
				FTIM2_NOR_TCH(0x4) | \
				FTIM2_NOR_TWPH(0x0E) | \
				FTIM2_NOR_TWP(0x1c))
#define CONFIG_SYS_NOR_FTIM3	0x04000000
#define CONFIG_SYS_IFC_CCR	0x01000000

#ifdef CONFIG_MTD_NOR_FLASH
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */

#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */

#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE,\
					 CONFIG_SYS_FLASH_BASE + 0x40000000}
#endif

#define CONFIG_NAND_FSL_IFC
#define CONFIG_SYS_NAND_MAX_ECCPOS	256
#define CONFIG_SYS_NAND_MAX_OOBFREE	2

#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
				| CSPR_V)
#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)

#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
				| CSOR_NAND_RAL_3	/* RAL = 3Byes */ \
				| CSOR_NAND_PGS_4K	/* Page Size = 4K */ \
				| CSOR_NAND_SPRZ_224	/* Spare size = 224 */ \
				| CSOR_NAND_PB(128))	/* Pages Per Block 128*/

#define CONFIG_SYS_NAND_ONFI_DETECTION

/* ONFI NAND Flash mode0 Timing Params */
#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x0e) | \
					FTIM0_NAND_TWP(0x30)   | \
					FTIM0_NAND_TWCHT(0x0e) | \
					FTIM0_NAND_TWH(0x14))
#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x64) | \
					FTIM1_NAND_TWBE(0xab)  | \
					FTIM1_NAND_TRR(0x1c)   | \
					FTIM1_NAND_TRP(0x30))
#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x1e) | \
					FTIM2_NAND_TREH(0x14) | \
					FTIM2_NAND_TWHRE(0x3c))
#define CONFIG_SYS_NAND_FTIM3		0x0

#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND

#define CONFIG_SYS_NAND_BLOCK_SIZE	(512 * 1024)
#define CONFIG_FSL_QIXIS	/* use common QIXIS code */
#define QIXIS_LBMAP_SWITCH		0x06
#define QIXIS_LBMAP_MASK		0x0f
#define QIXIS_LBMAP_SHIFT		0
#define QIXIS_LBMAP_DFLTBANK		0x00
#define QIXIS_LBMAP_ALTBANK		0x04
#define QIXIS_LBMAP_NAND		0x09
#define QIXIS_RST_CTL_RESET		0x31
#define QIXIS_RST_CTL_RESET_EN		0x30
#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
#define QIXIS_RCW_SRC_NAND		0x119
#define	QIXIS_RST_FORCE_MEM		0x01

#define CONFIG_SYS_CSPR3_EXT	(0x0)
#define CONFIG_SYS_CSPR3	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
				| CSPR_PORT_SIZE_8 \
				| CSPR_MSEL_GPCM \
				| CSPR_V)
#define CONFIG_SYS_CSPR3_FINAL	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
				| CSPR_PORT_SIZE_8 \
				| CSPR_MSEL_GPCM \
				| CSPR_V)

#define CONFIG_SYS_AMASK3	IFC_AMASK(64*1024)
#define CONFIG_SYS_CSOR3	CSOR_GPCM_ADM_SHIFT(12)
/* QIXIS Timing parameters for IFC CS3 */
#define CONFIG_SYS_CS3_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
					FTIM0_GPCM_TEADC(0x0e) | \
					FTIM0_GPCM_TEAHC(0x0e))
#define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
					FTIM1_GPCM_TRAD(0x3f))
#define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0xf) | \
					FTIM2_GPCM_TCH(0xf) | \
					FTIM2_GPCM_TWP(0x3E))
#define CONFIG_SYS_CS3_FTIM3		0x0

#if defined(CONFIG_SPL) && defined(CONFIG_NAND)
#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR0_CSPR_EARLY
#define CONFIG_SYS_CSPR2_FINAL		CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3

#define CONFIG_ENV_OFFSET		(2048 * 1024)
#define CONFIG_ENV_SECT_SIZE		0x20000
#define CONFIG_ENV_SIZE			0x2000
#define CONFIG_SPL_PAD_TO		0x80000
#define CONFIG_SYS_NAND_U_BOOT_OFFS	(1024 * 1024)
#define CONFIG_SYS_NAND_U_BOOT_SIZE	(512 * 1024)
#else
#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR_EARLY
#define CONFIG_SYS_CSPR0_FINAL		CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3

#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x300000)
#define CONFIG_ENV_SECT_SIZE		0x20000
#define CONFIG_ENV_SIZE			0x2000
#endif

/* Debug Server firmware */
#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR	0x580D00000ULL
#endif
#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000

#ifdef CONFIG_TARGET_LS2081ARDB
#define CONFIG_FSL_QIXIS	/* use common QIXIS code */
#define QIXIS_QMAP_MASK			0x07
#define QIXIS_QMAP_SHIFT		5
#define QIXIS_LBMAP_DFLTBANK		0x00
#define QIXIS_LBMAP_QSPI		0x00
#define QIXIS_RCW_SRC_QSPI		0x62
#define QIXIS_LBMAP_ALTBANK		0x20
#define QIXIS_RST_CTL_RESET		0x31
#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
#define QIXIS_LBMAP_MASK		0x0f
#define QIXIS_RST_CTL_RESET_EN		0x30
#endif

/*
 * I2C
 */
#ifdef CONFIG_TARGET_LS2081ARDB
#define CONFIG_SYS_I2C_FPGA_ADDR	0x66
#endif
#define I2C_MUX_PCA_ADDR		0x75
#define I2C_MUX_PCA_ADDR_PRI		0x75 /* Primary Mux*/

/* I2C bus multiplexer */
#define I2C_MUX_CH_DEFAULT      0x8

/* SPI */
#if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI)
#define CONFIG_SPI_FLASH
#ifdef CONFIG_FSL_QSPI
#define CONFIG_SPI_FLASH_STMICRO
#endif
#ifdef CONFIG_FSL_QSPI
#ifdef CONFIG_TARGET_LS2081ARDB
#define CONFIG_SPI_FLASH_STMICRO
#else
#define CONFIG_SPI_FLASH_SPANSION
#endif
#define FSL_QSPI_FLASH_SIZE		SZ_64M	/* 64MB */
#define FSL_QSPI_FLASH_NUM		2
#endif
#endif

/*
 * RTC configuration
 */
#define RTC
#ifdef CONFIG_TARGET_LS2081ARDB
#define CONFIG_RTC_PCF8563		1
#define CONFIG_SYS_I2C_RTC_ADDR         0x51
#else
#define CONFIG_RTC_DS3231               1
#define CONFIG_SYS_I2C_RTC_ADDR         0x68
#endif

/* EEPROM */
#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM	0
#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5

#define CONFIG_FSL_MEMAC

#ifdef CONFIG_PCI
#define CONFIG_PCI_SCAN_SHOW
#define CONFIG_CMD_PCI
#endif

/*  MMC  */
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif

#define CONFIG_MISC_INIT_R

/*
 * USB
 */
#define CONFIG_HAS_FSL_XHCI_USB
#define CONFIG_USB_XHCI_FSL
#define CONFIG_USB_MAX_CONTROLLER_COUNT         2
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS      2

#undef CONFIG_CMDLINE_EDITING
#include <config_distro_defaults.h>

#define BOOT_TARGET_DEVICES(func) \
	func(USB, usb, 0) \
	func(MMC, mmc, 0) \
	func(SCSI, scsi, 0) \
	func(DHCP, dhcp, na)
#include <config_distro_bootcmd.h>

/* Initial environment variables */
#undef CONFIG_EXTRA_ENV_SETTINGS
#ifdef CONFIG_SECURE_BOOT
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
	"scriptaddr=0x80800000\0"		\
	"kernel_addr_r=0x81000000\0"		\
	"pxefile_addr_r=0x81000000\0"		\
	"fdt_addr_r=0x88000000\0"		\
	"ramdisk_addr_r=0x89000000\0"		\
	"loadaddr=0x80100000\0"			\
	"kernel_addr=0x100000\0"		\
	"ramdisk_addr=0x800000\0"		\
	"ramdisk_size=0x2000000\0"		\
	"fdt_high=0xa0000000\0"			\
	"initrd_high=0xffffffffffffffff\0"	\
	"kernel_start=0x581000000\0"		\
	"kernel_load=0xa0000000\0"		\
	"kernel_size=0x2800000\0"		\
	"mcmemsize=0x40000000\0"		\
	"fdtfile=fsl-ls2080a-rdb.dtb\0"		\
	"mcinitcmd=esbc_validate 0x580700000;"  \
	"esbc_validate 0x580740000;"            \
	"fsl_mc start mc 0x580a00000"           \
	" 0x580e00000 \0"                       \
	BOOTENV
#else
#ifdef CONFIG_QSPI_BOOT
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
	"scriptaddr=0x80800000\0"		\
	"kernel_addr_r=0x81000000\0"		\
	"pxefile_addr_r=0x81000000\0"		\
	"fdt_addr_r=0x88000000\0"		\
	"ramdisk_addr_r=0x89000000\0"		\
	"loadaddr=0x80100000\0"			\
	"kernel_addr=0x100000\0"		\
	"ramdisk_size=0x2000000\0"		\
	"fdt_high=0xa0000000\0"			\
	"initrd_high=0xffffffffffffffff\0"	\
	"kernel_start=0x21000000\0"		\
	"mcmemsize=0x40000000\0"		\
	"mcinitcmd=fsl_mc start mc 0x20a00000" \
	" 0x20e00000 \0"                       \
	BOOTENV
#else
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
	"scriptaddr=0x80800000\0"		\
	"kernel_addr_r=0x81000000\0"		\
	"pxefile_addr_r=0x81000000\0"		\
	"fdt_addr_r=0x88000000\0"		\
	"ramdisk_addr_r=0x89000000\0"		\
	"loadaddr=0x80100000\0"			\
	"kernel_addr=0x100000\0"		\
	"ramdisk_addr=0x800000\0"		\
	"ramdisk_size=0x2000000\0"		\
	"fdt_high=0xa0000000\0"			\
	"initrd_high=0xffffffffffffffff\0"	\
	"kernel_start=0x581000000\0"		\
	"kernel_load=0xa0000000\0"		\
	"kernel_size=0x2800000\0"		\
	"mcmemsize=0x40000000\0"		\
	"fdtfile=fsl-ls2080a-rdb.dtb\0"		\
	"mcinitcmd=fsl_mc start mc 0x580a00000" \
	" 0x580e00000 \0"                       \
	BOOTENV
#endif
#endif


#undef CONFIG_BOOTARGS
#define CONFIG_BOOTARGS		"console=ttyS1,115200 root=/dev/ram0 " \
				"earlycon=uart8250,mmio,0x21c0600 " \
				"ramdisk_size=0x2000000 default_hugepagesz=2m" \
				" hugepagesz=2m hugepages=256"

#undef CONFIG_BOOTCOMMAND
#ifdef CONFIG_QSPI_BOOT
/* Try to boot an on-QSPI kernel first, then do normal distro boot */
#define CONFIG_BOOTCOMMAND "run mcinitcmd && fsl_mc lazyapply dpl 0x20d00000" \
			   " && bootm $kernel_start" \
			   " || run distro_bootcmd"
#else
/* Try to boot an on-NOR kernel first, then do normal distro boot */
#define CONFIG_BOOTCOMMAND "run mcinitcmd && fsl_mc lazyapply dpl 0x580d00000" \
			   " && cp.b $kernel_start $kernel_load $kernel_size" \
			   " && bootm $kernel_load" \
			   " || run distro_bootcmd"
#endif

/* MAC/PHY configuration */
#ifdef CONFIG_FSL_MC_ENET
#define CONFIG_PHYLIB_10G
#define CONFIG_PHY_AQUANTIA
#define CONFIG_PHY_CORTINA
#define CONFIG_PHYLIB
#define	CONFIG_SYS_CORTINA_FW_IN_NOR
#ifdef CONFIG_QSPI_BOOT
#define CONFIG_CORTINA_FW_ADDR		0x20980000
#else
#define CONFIG_CORTINA_FW_ADDR		0x580980000
#endif
#define CONFIG_CORTINA_FW_LENGTH	0x40000

#define CORTINA_PHY_ADDR1	0x10
#define CORTINA_PHY_ADDR2	0x11
#define CORTINA_PHY_ADDR3	0x12
#define CORTINA_PHY_ADDR4	0x13
#define AQ_PHY_ADDR1		0x00
#define AQ_PHY_ADDR2		0x01
#define AQ_PHY_ADDR3		0x02
#define AQ_PHY_ADDR4		0x03
#define AQR405_IRQ_MASK		0x36

#define CONFIG_MII
#define CONFIG_ETHPRIME		"DPMAC1@xgmii"
#define CONFIG_PHY_GIGE
#define CONFIG_PHY_AQUANTIA
#endif

#include <asm/fsl_secure_boot.h>

#endif /* __LS2_RDB_H */
Commit	Line	Data
e2b65ea9	1	/*
89a168f7	2	* Copyright 2017 NXP
e2b65ea9 YS	3	* Copyright 2015 Freescale Semiconductor
	4	*
	5	* SPDX-License-Identifier: GPL-2.0+
	6	*/
	7
	8	#ifndef __LS2_RDB_H
	9	#define __LS2_RDB_H
	10
44937214	11	#include "ls2080a_common.h"
e2b65ea9 YS	12
	13	#undef CONFIG_CONS_INDEX
	14	#define CONFIG_CONS_INDEX 2
	15
89a168f7	16	#ifdef CONFIG_FSL_QSPI
3049a583 PJ	17	#ifdef CONFIG_TARGET_LS2081ARDB
	18	#define CONFIG_QIXIS_I2C_ACCESS
	19	#endif
89a168f7 PJ	20	#define CONFIG_SYS_I2C_EARLY_INIT
	21	#define CONFIG_DISPLAY_BOARDINFO_LATE
	22	#endif
	23
ed2530d0 RH	24	#define I2C_MUX_CH_VOL_MONITOR 0xa
	25	#define I2C_VOL_MONITOR_ADDR 0x38
	26	#define CONFIG_VOL_MONITOR_IR36021_READ
	27	#define CONFIG_VOL_MONITOR_IR36021_SET
	28
	29	#define CONFIG_VID_FLS_ENV "ls2080ardb_vdd_mv"
	30	#ifndef CONFIG_SPL_BUILD
	31	#define CONFIG_VID
	32	#endif
	33	/* step the IR regulator in 5mV increments */
	34	#define IR_VDD_STEP_DOWN 5
	35	#define IR_VDD_STEP_UP 5
	36	/* The lowest and highest voltage allowed for LS2080ARDB */
	37	#define VDD_MV_MIN 819
	38	#define VDD_MV_MAX 1212
	39
e2b65ea9 YS	40	#ifndef __ASSEMBLY__
	41	unsigned long get_board_sys_clk(void);
	42	#endif
	43
	44	#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
	45	#define CONFIG_DDR_CLK_FREQ 133333333
	46	#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
	47
	48	#define CONFIG_DDR_SPD
	49	#define CONFIG_DDR_ECC
	50	#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
	51	#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
	52	#define SPD_EEPROM_ADDRESS1 0x51
	53	#define SPD_EEPROM_ADDRESS2 0x52
fc7b3855 YS	54	#define SPD_EEPROM_ADDRESS3 0x53
fc7b3855 YS	55	#define SPD_EEPROM_ADDRESS4 0x54
e2b65ea9 YS	56	#define SPD_EEPROM_ADDRESS5 0x55
	57	#define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */
	58	#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
	59	#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
	60	#define CONFIG_DIMM_SLOTS_PER_CTLR 2
	61	#define CONFIG_CHIP_SELECTS_PER_CTRL 4
44937214	62	#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
e2b65ea9	63	#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
44937214	64	#endif
e2b65ea9 YS	65	#define CONFIG_FSL_DDR_BIST /* enable built-in memory test */
e2b65ea9 YS	66
989c5f0a TY	67	/* SATA */
	68	#define CONFIG_LIBATA
	69	#define CONFIG_SCSI_AHCI
	70	#define CONFIG_SCSI_AHCI_PLAT
989c5f0a TY	71
	72	#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
	73	#define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2
	74
	75	#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
	76	#define CONFIG_SYS_SCSI_MAX_LUN 1
	77	#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
	78	CONFIG_SYS_SCSI_MAX_LUN)
	79
89a168f7	80	#ifndef CONFIG_FSL_QSPI
e2b65ea9 YS	81	/* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */
	82
	83	#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
	84	#define CONFIG_SYS_NOR_AMASK IFC_AMASK(12810241024)
	85	#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(6410241024)
	86
	87	#define CONFIG_SYS_NOR0_CSPR \
	88	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \| \
	89	CSPR_PORT_SIZE_16 \| \
	90	CSPR_MSEL_NOR \| \
	91	CSPR_V)
	92	#define CONFIG_SYS_NOR0_CSPR_EARLY \
	93	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) \| \
	94	CSPR_PORT_SIZE_16 \| \
	95	CSPR_MSEL_NOR \| \
	96	CSPR_V)
	97	#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
	98	#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) \| \
	99	FTIM0_NOR_TEADC(0x5) \| \
	100	FTIM0_NOR_TEAHC(0x5))
	101	#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) \| \
	102	FTIM1_NOR_TRAD_NOR(0x1a) \|\
	103	FTIM1_NOR_TSEQRAD_NOR(0x13))
	104	#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) \| \
	105	FTIM2_NOR_TCH(0x4) \| \
	106	FTIM2_NOR_TWPH(0x0E) \| \
	107	FTIM2_NOR_TWP(0x1c))
	108	#define CONFIG_SYS_NOR_FTIM3 0x04000000
	109	#define CONFIG_SYS_IFC_CCR 0x01000000
	110
e856bdcf	111	#ifdef CONFIG_MTD_NOR_FLASH
e2b65ea9 YS	112	#define CONFIG_FLASH_CFI_DRIVER
	113	#define CONFIG_SYS_FLASH_CFI
	114	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
	115	#define CONFIG_SYS_FLASH_QUIET_TEST
	116	#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
	117
	118	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
	119	#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
	120	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	121	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
	122
	123	#define CONFIG_SYS_FLASH_EMPTY_INFO
	124	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
	125	CONFIG_SYS_FLASH_BASE + 0x40000000}
	126	#endif
	127
	128	#define CONFIG_NAND_FSL_IFC
	129	#define CONFIG_SYS_NAND_MAX_ECCPOS 256
	130	#define CONFIG_SYS_NAND_MAX_OOBFREE 2
	131
e2b65ea9 YS	132	#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
	133	#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
	134	\| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
	135	\| CSPR_MSEL_NAND /* MSEL = NAND */ \
	136	\| CSPR_V)
	137	#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
	138
	139	#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
	140	\| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
	141	\| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
	142	\| CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
	143	\| CSOR_NAND_PGS_4K /* Page Size = 4K */ \
	144	\| CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
	145	\| CSOR_NAND_PB(128)) /* Pages Per Block 128*/
	146
	147	#define CONFIG_SYS_NAND_ONFI_DETECTION
	148
	149	/* ONFI NAND Flash mode0 Timing Params */
	150	#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x0e) \| \
	151	FTIM0_NAND_TWP(0x30) \| \
	152	FTIM0_NAND_TWCHT(0x0e) \| \
	153	FTIM0_NAND_TWH(0x14))
	154	#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x64) \| \
	155	FTIM1_NAND_TWBE(0xab) \| \
	156	FTIM1_NAND_TRR(0x1c) \| \
	157	FTIM1_NAND_TRP(0x30))
	158	#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x1e) \| \
	159	FTIM2_NAND_TREH(0x14) \| \
	160	FTIM2_NAND_TWHRE(0x3c))
	161	#define CONFIG_SYS_NAND_FTIM3 0x0
	162
	163	#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
	164	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	165	#define CONFIG_MTD_NAND_VERIFY_WRITE
	166	#define CONFIG_CMD_NAND
	167
	168	#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
e2b65ea9 YS	169	#define CONFIG_FSL_QIXIS /* use common QIXIS code */
	170	#define QIXIS_LBMAP_SWITCH 0x06
	171	#define QIXIS_LBMAP_MASK 0x0f
	172	#define QIXIS_LBMAP_SHIFT 0
	173	#define QIXIS_LBMAP_DFLTBANK 0x00
	174	#define QIXIS_LBMAP_ALTBANK 0x04
32eda7cc	175	#define QIXIS_LBMAP_NAND 0x09
e2b65ea9 YS	176	#define QIXIS_RST_CTL_RESET 0x31
	177	#define QIXIS_RST_CTL_RESET_EN 0x30
	178	#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
	179	#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
	180	#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
32eda7cc	181	#define QIXIS_RCW_SRC_NAND 0x119
e2b65ea9 YS	182	#define QIXIS_RST_FORCE_MEM 0x01
	183
	184	#define CONFIG_SYS_CSPR3_EXT (0x0)
	185	#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
	186	\| CSPR_PORT_SIZE_8 \
	187	\| CSPR_MSEL_GPCM \
	188	\| CSPR_V)
	189	#define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
	190	\| CSPR_PORT_SIZE_8 \
	191	\| CSPR_MSEL_GPCM \
	192	\| CSPR_V)
	193
	194	#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
	195	#define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12)
	196	/* QIXIS Timing parameters for IFC CS3 */
	197	#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) \| \
	198	FTIM0_GPCM_TEADC(0x0e) \| \
	199	FTIM0_GPCM_TEAHC(0x0e))
	200	#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) \| \
	201	FTIM1_GPCM_TRAD(0x3f))
	202	#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) \| \
	203	FTIM2_GPCM_TCH(0xf) \| \
	204	FTIM2_GPCM_TWP(0x3E))
	205	#define CONFIG_SYS_CS3_FTIM3 0x0
	206
32eda7cc SW	207	#if defined(CONFIG_SPL) && defined(CONFIG_NAND)
	208	#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
	209	#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR_EARLY
	210	#define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR0_CSPR
	211	#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
	212	#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
	213	#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
	214	#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
	215	#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
	216	#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
	217	#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
	218	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
	219	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
	220	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
	221	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
	222	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
	223	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
	224	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
	225
32eda7cc SW	226	#define CONFIG_ENV_OFFSET (2048 * 1024)
	227	#define CONFIG_ENV_SECT_SIZE 0x20000
	228	#define CONFIG_ENV_SIZE 0x2000
	229	#define CONFIG_SPL_PAD_TO 0x80000
	230	#define CONFIG_SYS_NAND_U_BOOT_OFFS (1024 * 1024)
	231	#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024)
	232	#else
e2b65ea9 YS	233	#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
	234	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
	235	#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
	236	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
	237	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
	238	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
	239	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
	240	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
	241	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
	242	#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
	243	#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
	244	#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
	245	#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
	246	#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
	247	#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
	248	#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
	249	#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
	250
32eda7cc	251	#define CONFIG_ENV_IS_IN_FLASH
f5bf23d8	252	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
32eda7cc SW	253	#define CONFIG_ENV_SECT_SIZE 0x20000
	254	#define CONFIG_ENV_SIZE 0x2000
	255	#endif
	256
e2b65ea9 YS	257	/* Debug Server firmware */
	258	#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
	259	#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
89a168f7	260	#endif
e2b65ea9 YS	261	#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
e2b65ea9 YS	262
3049a583 PJ	263	#ifdef CONFIG_TARGET_LS2081ARDB
	264	#define CONFIG_FSL_QIXIS /* use common QIXIS code */
	265	#define QIXIS_QMAP_MASK 0x07
	266	#define QIXIS_QMAP_SHIFT 5
	267	#define QIXIS_LBMAP_DFLTBANK 0x00
	268	#define QIXIS_LBMAP_QSPI 0x00
	269	#define QIXIS_RCW_SRC_QSPI 0x62
	270	#define QIXIS_LBMAP_ALTBANK 0x20
	271	#define QIXIS_RST_CTL_RESET 0x31
	272	#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
	273	#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
	274	#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
	275	#define QIXIS_LBMAP_MASK 0x0f
	276	#define QIXIS_RST_CTL_RESET_EN 0x30
	277	#endif
	278
e2b65ea9 YS	279	/*
	280	* I2C
	281	*/
3049a583 PJ	282	#ifdef CONFIG_TARGET_LS2081ARDB
	283	#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
	284	#endif
4012350d PK	285	#define I2C_MUX_PCA_ADDR 0x75
4012350d PK	286	#define I2C_MUX_PCA_ADDR_PRI 0x75 /* Primary Mux*/
e2b65ea9 YS	287
	288	/* I2C bus multiplexer */
	289	#define I2C_MUX_CH_DEFAULT 0x8
	290
0c42a8de	291	/* SPI */
89a168f7	292	#if defined(CONFIG_FSL_QSPI) \|\| defined(CONFIG_FSL_DSPI)
0c42a8de	293	#define CONFIG_SPI_FLASH
89a168f7	294	#ifdef CONFIG_FSL_QSPI
21640db5	295	#define CONFIG_SPI_FLASH_STMICRO
0c42a8de	296	#endif
89a168f7	297	#ifdef CONFIG_FSL_QSPI
3049a583 PJ	298	#ifdef CONFIG_TARGET_LS2081ARDB
	299	#define CONFIG_SPI_FLASH_STMICRO
	300	#else
89a168f7	301	#define CONFIG_SPI_FLASH_SPANSION
3049a583	302	#endif
89a168f7 PJ	303	#define FSL_QSPI_FLASH_SIZE SZ_64M /* 64MB */
	304	#define FSL_QSPI_FLASH_NUM 2
	305	#endif
	306	#endif
0c42a8de	307
e2b65ea9 YS	308	/*
	309	* RTC configuration
	310	*/
	311	#define RTC
3049a583 PJ	312	#ifdef CONFIG_TARGET_LS2081ARDB
	313	#define CONFIG_RTC_PCF8563 1
	314	#define CONFIG_SYS_I2C_RTC_ADDR 0x51
	315	#else
e2b65ea9 YS	316	#define CONFIG_RTC_DS3231 1
e2b65ea9 YS	317	#define CONFIG_SYS_I2C_RTC_ADDR 0x68
3049a583	318	#endif
e2b65ea9 YS	319
	320	/* EEPROM */
	321	#define CONFIG_ID_EEPROM
e2b65ea9 YS	322	#define CONFIG_SYS_I2C_EEPROM_NXID
	323	#define CONFIG_SYS_EEPROM_BUS_NUM 0
	324	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
	325	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	326	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
	327	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
	328
e2b65ea9	329	#define CONFIG_FSL_MEMAC
e2b65ea9 YS	330
e2b65ea9 YS	331	#ifdef CONFIG_PCI
e2b65ea9 YS	332	#define CONFIG_PCI_SCAN_SHOW
e2b65ea9 YS	333	#define CONFIG_CMD_PCI
e2b65ea9 YS	334	#endif
e2b65ea9 YS	335
8b06460e	336	/* MMC */
8b06460e	337	#ifdef CONFIG_MMC
8b06460e YL	338	#define CONFIG_FSL_ESDHC
8b06460e YL	339	#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
8b06460e	340	#endif
e2b65ea9	341
5a4d744c YL	342	#define CONFIG_MISC_INIT_R
5a4d744c YL	343
e16b604e NB	344	/*
	345	* USB
	346	*/
	347	#define CONFIG_HAS_FSL_XHCI_USB
e16b604e	348	#define CONFIG_USB_XHCI_FSL
e16b604e NB	349	#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
e16b604e NB	350	#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
e16b604e	351
b99ebaf9 AG	352	#undef CONFIG_CMDLINE_EDITING
	353	#include <config_distro_defaults.h>
	354
	355	#define BOOT_TARGET_DEVICES(func) \
	356	func(USB, usb, 0) \
	357	func(MMC, mmc, 0) \
	358	func(SCSI, scsi, 0) \
	359	func(DHCP, dhcp, na)
	360	#include <config_distro_bootcmd.h>
	361
e2b65ea9 YS	362	/* Initial environment variables */
e2b65ea9 YS	363	#undef CONFIG_EXTRA_ENV_SETTINGS
9ed44787	364	#ifdef CONFIG_SECURE_BOOT
e2b65ea9 YS	365	#define CONFIG_EXTRA_ENV_SETTINGS \
e2b65ea9 YS	366	"hwconfig=fsl_ddr:bank_intlv=auto\0" \
b99ebaf9 AG	367	"scriptaddr=0x80800000\0" \
	368	"kernel_addr_r=0x81000000\0" \
	369	"pxefile_addr_r=0x81000000\0" \
	370	"fdt_addr_r=0x88000000\0" \
	371	"ramdisk_addr_r=0x89000000\0" \
e2b65ea9 YS	372	"loadaddr=0x80100000\0" \
	373	"kernel_addr=0x100000\0" \
	374	"ramdisk_addr=0x800000\0" \
	375	"ramdisk_size=0x2000000\0" \
	376	"fdt_high=0xa0000000\0" \
	377	"initrd_high=0xffffffffffffffff\0" \
7676074a	378	"kernel_start=0x581000000\0" \
e2b65ea9	379	"kernel_load=0xa0000000\0" \
16ed8560	380	"kernel_size=0x2800000\0" \
6d7b9e78	381	"mcmemsize=0x40000000\0" \
b99ebaf9	382	"fdtfile=fsl-ls2080a-rdb.dtb\0" \
7676074a UA	383	"mcinitcmd=esbc_validate 0x580700000;" \
	384	"esbc_validate 0x580740000;" \
	385	"fsl_mc start mc 0x580a00000" \
	386	" 0x580e00000 \0" \
b99ebaf9	387	BOOTENV
9ed44787	388	#else
89a168f7 PJ	389	#ifdef CONFIG_QSPI_BOOT
	390	#define CONFIG_EXTRA_ENV_SETTINGS \
	391	"hwconfig=fsl_ddr:bank_intlv=auto\0" \
	392	"scriptaddr=0x80800000\0" \
	393	"kernel_addr_r=0x81000000\0" \
	394	"pxefile_addr_r=0x81000000\0" \
	395	"fdt_addr_r=0x88000000\0" \
	396	"ramdisk_addr_r=0x89000000\0" \
	397	"loadaddr=0x80100000\0" \
	398	"kernel_addr=0x100000\0" \
	399	"ramdisk_size=0x2000000\0" \
	400	"fdt_high=0xa0000000\0" \
	401	"initrd_high=0xffffffffffffffff\0" \
	402	"kernel_start=0x21000000\0" \
	403	"mcmemsize=0x40000000\0" \
	404	"mcinitcmd=fsl_mc start mc 0x20a00000" \
	405	" 0x20e00000 \0" \
b99ebaf9	406	BOOTENV
9ed44787 UA	407	#else
	408	#define CONFIG_EXTRA_ENV_SETTINGS \
	409	"hwconfig=fsl_ddr:bank_intlv=auto\0" \
	410	"scriptaddr=0x80800000\0" \
	411	"kernel_addr_r=0x81000000\0" \
	412	"pxefile_addr_r=0x81000000\0" \
	413	"fdt_addr_r=0x88000000\0" \
	414	"ramdisk_addr_r=0x89000000\0" \
	415	"loadaddr=0x80100000\0" \
	416	"kernel_addr=0x100000\0" \
	417	"ramdisk_addr=0x800000\0" \
	418	"ramdisk_size=0x2000000\0" \
	419	"fdt_high=0xa0000000\0" \
	420	"initrd_high=0xffffffffffffffff\0" \
f5bf23d8	421	"kernel_start=0x581000000\0" \
9ed44787 UA	422	"kernel_load=0xa0000000\0" \
9ed44787 UA	423	"kernel_size=0x2800000\0" \
6d7b9e78	424	"mcmemsize=0x40000000\0" \
9ed44787	425	"fdtfile=fsl-ls2080a-rdb.dtb\0" \
f5bf23d8 SK	426	"mcinitcmd=fsl_mc start mc 0x580a00000" \
f5bf23d8 SK	427	" 0x580e00000 \0" \
9ed44787 UA	428	BOOTENV
9ed44787 UA	429	#endif
89a168f7	430	#endif
9ed44787	431
e2b65ea9	432
56cd0760 PK	433	#undef CONFIG_BOOTARGS
56cd0760 PK	434	#define CONFIG_BOOTARGS "console=ttyS1,115200 root=/dev/ram0 " \
ed77b704	435	"earlycon=uart8250,mmio,0x21c0600 " \
56cd0760	436	"ramdisk_size=0x2000000 default_hugepagesz=2m" \
9e71bb9c	437	" hugepagesz=2m hugepages=256"
56cd0760	438
b99ebaf9	439	#undef CONFIG_BOOTCOMMAND
89a168f7 PJ	440	#ifdef CONFIG_QSPI_BOOT
	441	/* Try to boot an on-QSPI kernel first, then do normal distro boot */
	442	#define CONFIG_BOOTCOMMAND "run mcinitcmd && fsl_mc lazyapply dpl 0x20d00000" \
	443	" && bootm $kernel_start" \
	444	" \|\| run distro_bootcmd"
	445	#else
b99ebaf9	446	/* Try to boot an on-NOR kernel first, then do normal distro boot */
f5bf23d8	447	#define CONFIG_BOOTCOMMAND "run mcinitcmd && fsl_mc lazyapply dpl 0x580d00000" \
b99ebaf9 AG	448	" && cp.b $kernel_start $kernel_load $kernel_size" \
	449	" && bootm $kernel_load" \
	450	" \|\| run distro_bootcmd"
89a168f7	451	#endif
b99ebaf9	452
3484d953 PK	453	/* MAC/PHY configuration */
	454	#ifdef CONFIG_FSL_MC_ENET
	455	#define CONFIG_PHYLIB_10G
c69384e1	456	#define CONFIG_PHY_AQUANTIA
3484d953 PK	457	#define CONFIG_PHY_CORTINA
	458	#define CONFIG_PHYLIB
	459	#define CONFIG_SYS_CORTINA_FW_IN_NOR
89a168f7 PJ	460	#ifdef CONFIG_QSPI_BOOT
	461	#define CONFIG_CORTINA_FW_ADDR 0x20980000
	462	#else
f5bf23d8	463	#define CONFIG_CORTINA_FW_ADDR 0x580980000
89a168f7	464	#endif
3484d953 PK	465	#define CONFIG_CORTINA_FW_LENGTH 0x40000
	466
	467	#define CORTINA_PHY_ADDR1 0x10
	468	#define CORTINA_PHY_ADDR2 0x11
	469	#define CORTINA_PHY_ADDR3 0x12
	470	#define CORTINA_PHY_ADDR4 0x13
	471	#define AQ_PHY_ADDR1 0x00
	472	#define AQ_PHY_ADDR2 0x01
	473	#define AQ_PHY_ADDR3 0x02
	474	#define AQ_PHY_ADDR4 0x03
abc7d0f7	475	#define AQR405_IRQ_MASK 0x36
3484d953 PK	476
3484d953 PK	477	#define CONFIG_MII
7ad9cc96	478	#define CONFIG_ETHPRIME "DPMAC1@xgmii"
3484d953	479	#define CONFIG_PHY_GIGE
95279315	480	#define CONFIG_PHY_AQUANTIA
3484d953 PK	481	#endif
3484d953 PK	482
fcfdb6d5 SJ	483	#include <asm/fsl_secure_boot.h>
fcfdb6d5 SJ	484
e2b65ea9	485	#endif /* __LS2_RDB_H */