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e2b65ea9 YS |
1 | /* |
2 | * Copyright 2015 Freescale Semiconductor | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
6 | ||
7 | #ifndef __LS2_RDB_H | |
8 | #define __LS2_RDB_H | |
9 | ||
44937214 | 10 | #include "ls2080a_common.h" |
e2b65ea9 YS |
11 | |
12 | #undef CONFIG_CONS_INDEX | |
13 | #define CONFIG_CONS_INDEX 2 | |
14 | ||
15 | #define CONFIG_DISPLAY_BOARDINFO | |
16 | ||
17 | #ifndef __ASSEMBLY__ | |
18 | unsigned long get_board_sys_clk(void); | |
19 | #endif | |
20 | ||
18fb0e3c | 21 | #define CONFIG_SYS_FSL_CLK |
e2b65ea9 YS |
22 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() |
23 | #define CONFIG_DDR_CLK_FREQ 133333333 | |
24 | #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) | |
25 | ||
26 | #define CONFIG_DDR_SPD | |
27 | #define CONFIG_DDR_ECC | |
28 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER | |
29 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef | |
30 | #define SPD_EEPROM_ADDRESS1 0x51 | |
31 | #define SPD_EEPROM_ADDRESS2 0x52 | |
fc7b3855 YS |
32 | #define SPD_EEPROM_ADDRESS3 0x53 |
33 | #define SPD_EEPROM_ADDRESS4 0x54 | |
e2b65ea9 YS |
34 | #define SPD_EEPROM_ADDRESS5 0x55 |
35 | #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */ | |
36 | #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 | |
37 | #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ | |
38 | #define CONFIG_DIMM_SLOTS_PER_CTLR 2 | |
39 | #define CONFIG_CHIP_SELECTS_PER_CTRL 4 | |
44937214 | 40 | #ifdef CONFIG_SYS_FSL_HAS_DP_DDR |
e2b65ea9 | 41 | #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 |
44937214 | 42 | #endif |
e2b65ea9 YS |
43 | #define CONFIG_FSL_DDR_BIST /* enable built-in memory test */ |
44 | ||
989c5f0a TY |
45 | /* SATA */ |
46 | #define CONFIG_LIBATA | |
47 | #define CONFIG_SCSI_AHCI | |
48 | #define CONFIG_SCSI_AHCI_PLAT | |
49 | #define CONFIG_CMD_SCSI | |
50 | #define CONFIG_CMD_FAT | |
51 | #define CONFIG_CMD_EXT2 | |
52 | #define CONFIG_DOS_PARTITION | |
53 | #define CONFIG_BOARD_LATE_INIT | |
54 | ||
55 | #define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 | |
56 | #define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2 | |
57 | ||
58 | #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 | |
59 | #define CONFIG_SYS_SCSI_MAX_LUN 1 | |
60 | #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ | |
61 | CONFIG_SYS_SCSI_MAX_LUN) | |
62 | ||
e2b65ea9 YS |
63 | /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */ |
64 | ||
65 | #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) | |
66 | #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) | |
67 | #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) | |
68 | ||
69 | #define CONFIG_SYS_NOR0_CSPR \ | |
70 | (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ | |
71 | CSPR_PORT_SIZE_16 | \ | |
72 | CSPR_MSEL_NOR | \ | |
73 | CSPR_V) | |
74 | #define CONFIG_SYS_NOR0_CSPR_EARLY \ | |
75 | (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ | |
76 | CSPR_PORT_SIZE_16 | \ | |
77 | CSPR_MSEL_NOR | \ | |
78 | CSPR_V) | |
79 | #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) | |
80 | #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ | |
81 | FTIM0_NOR_TEADC(0x5) | \ | |
82 | FTIM0_NOR_TEAHC(0x5)) | |
83 | #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ | |
84 | FTIM1_NOR_TRAD_NOR(0x1a) |\ | |
85 | FTIM1_NOR_TSEQRAD_NOR(0x13)) | |
86 | #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ | |
87 | FTIM2_NOR_TCH(0x4) | \ | |
88 | FTIM2_NOR_TWPH(0x0E) | \ | |
89 | FTIM2_NOR_TWP(0x1c)) | |
90 | #define CONFIG_SYS_NOR_FTIM3 0x04000000 | |
91 | #define CONFIG_SYS_IFC_CCR 0x01000000 | |
92 | ||
93 | #ifndef CONFIG_SYS_NO_FLASH | |
94 | #define CONFIG_FLASH_CFI_DRIVER | |
95 | #define CONFIG_SYS_FLASH_CFI | |
96 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
97 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
98 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
99 | ||
100 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
101 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
102 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
103 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
104 | ||
105 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
106 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ | |
107 | CONFIG_SYS_FLASH_BASE + 0x40000000} | |
108 | #endif | |
109 | ||
110 | #define CONFIG_NAND_FSL_IFC | |
111 | #define CONFIG_SYS_NAND_MAX_ECCPOS 256 | |
112 | #define CONFIG_SYS_NAND_MAX_OOBFREE 2 | |
113 | ||
114 | ||
115 | #define CONFIG_SYS_NAND_CSPR_EXT (0x0) | |
116 | #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | |
117 | | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ | |
118 | | CSPR_MSEL_NAND /* MSEL = NAND */ \ | |
119 | | CSPR_V) | |
120 | #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) | |
121 | ||
122 | #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | |
123 | | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | |
124 | | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | |
125 | | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ | |
126 | | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ | |
127 | | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ | |
128 | | CSOR_NAND_PB(128)) /* Pages Per Block 128*/ | |
129 | ||
130 | #define CONFIG_SYS_NAND_ONFI_DETECTION | |
131 | ||
132 | /* ONFI NAND Flash mode0 Timing Params */ | |
133 | #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x0e) | \ | |
134 | FTIM0_NAND_TWP(0x30) | \ | |
135 | FTIM0_NAND_TWCHT(0x0e) | \ | |
136 | FTIM0_NAND_TWH(0x14)) | |
137 | #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x64) | \ | |
138 | FTIM1_NAND_TWBE(0xab) | \ | |
139 | FTIM1_NAND_TRR(0x1c) | \ | |
140 | FTIM1_NAND_TRP(0x30)) | |
141 | #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x1e) | \ | |
142 | FTIM2_NAND_TREH(0x14) | \ | |
143 | FTIM2_NAND_TWHRE(0x3c)) | |
144 | #define CONFIG_SYS_NAND_FTIM3 0x0 | |
145 | ||
146 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } | |
147 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
148 | #define CONFIG_MTD_NAND_VERIFY_WRITE | |
149 | #define CONFIG_CMD_NAND | |
150 | ||
151 | #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) | |
152 | ||
153 | #define CONFIG_FSL_QIXIS /* use common QIXIS code */ | |
154 | #define QIXIS_LBMAP_SWITCH 0x06 | |
155 | #define QIXIS_LBMAP_MASK 0x0f | |
156 | #define QIXIS_LBMAP_SHIFT 0 | |
157 | #define QIXIS_LBMAP_DFLTBANK 0x00 | |
158 | #define QIXIS_LBMAP_ALTBANK 0x04 | |
32eda7cc | 159 | #define QIXIS_LBMAP_NAND 0x09 |
e2b65ea9 YS |
160 | #define QIXIS_RST_CTL_RESET 0x31 |
161 | #define QIXIS_RST_CTL_RESET_EN 0x30 | |
162 | #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 | |
163 | #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 | |
164 | #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 | |
32eda7cc | 165 | #define QIXIS_RCW_SRC_NAND 0x119 |
e2b65ea9 YS |
166 | #define QIXIS_RST_FORCE_MEM 0x01 |
167 | ||
168 | #define CONFIG_SYS_CSPR3_EXT (0x0) | |
169 | #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ | |
170 | | CSPR_PORT_SIZE_8 \ | |
171 | | CSPR_MSEL_GPCM \ | |
172 | | CSPR_V) | |
173 | #define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ | |
174 | | CSPR_PORT_SIZE_8 \ | |
175 | | CSPR_MSEL_GPCM \ | |
176 | | CSPR_V) | |
177 | ||
178 | #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) | |
179 | #define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12) | |
180 | /* QIXIS Timing parameters for IFC CS3 */ | |
181 | #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ | |
182 | FTIM0_GPCM_TEADC(0x0e) | \ | |
183 | FTIM0_GPCM_TEAHC(0x0e)) | |
184 | #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ | |
185 | FTIM1_GPCM_TRAD(0x3f)) | |
186 | #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ | |
187 | FTIM2_GPCM_TCH(0xf) | \ | |
188 | FTIM2_GPCM_TWP(0x3E)) | |
189 | #define CONFIG_SYS_CS3_FTIM3 0x0 | |
190 | ||
32eda7cc SW |
191 | #if defined(CONFIG_SPL) && defined(CONFIG_NAND) |
192 | #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT | |
193 | #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR_EARLY | |
194 | #define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR0_CSPR | |
195 | #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK | |
196 | #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR | |
197 | #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
198 | #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
199 | #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
200 | #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
201 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT | |
202 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR | |
203 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK | |
204 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR | |
205 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
206 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
207 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
208 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
209 | ||
210 | #define CONFIG_ENV_IS_IN_NAND | |
211 | #define CONFIG_ENV_OFFSET (2048 * 1024) | |
212 | #define CONFIG_ENV_SECT_SIZE 0x20000 | |
213 | #define CONFIG_ENV_SIZE 0x2000 | |
214 | #define CONFIG_SPL_PAD_TO 0x80000 | |
215 | #define CONFIG_SYS_NAND_U_BOOT_OFFS (1024 * 1024) | |
216 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024) | |
217 | #else | |
e2b65ea9 YS |
218 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT |
219 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY | |
220 | #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR | |
221 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK | |
222 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR | |
223 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
224 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
225 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
226 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
227 | #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT | |
228 | #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR | |
229 | #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK | |
230 | #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR | |
231 | #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
232 | #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
233 | #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
234 | #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
235 | ||
32eda7cc SW |
236 | #define CONFIG_ENV_IS_IN_FLASH |
237 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000) | |
238 | #define CONFIG_ENV_SECT_SIZE 0x20000 | |
239 | #define CONFIG_ENV_SIZE 0x2000 | |
240 | #endif | |
241 | ||
e2b65ea9 YS |
242 | /* Debug Server firmware */ |
243 | #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR | |
244 | #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL | |
245 | ||
e2b65ea9 YS |
246 | #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 |
247 | ||
248 | /* | |
249 | * I2C | |
250 | */ | |
4012350d PK |
251 | #define I2C_MUX_PCA_ADDR 0x75 |
252 | #define I2C_MUX_PCA_ADDR_PRI 0x75 /* Primary Mux*/ | |
e2b65ea9 YS |
253 | |
254 | /* I2C bus multiplexer */ | |
255 | #define I2C_MUX_CH_DEFAULT 0x8 | |
256 | ||
0c42a8de HW |
257 | /* SPI */ |
258 | #ifdef CONFIG_FSL_DSPI | |
259 | #define CONFIG_CMD_SF | |
260 | #define CONFIG_SPI_FLASH | |
0c42a8de HW |
261 | #define CONFIG_SPI_FLASH_BAR |
262 | #endif | |
263 | ||
e2b65ea9 YS |
264 | /* |
265 | * RTC configuration | |
266 | */ | |
267 | #define RTC | |
268 | #define CONFIG_RTC_DS3231 1 | |
269 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 | |
6581440c | 270 | #define CONFIG_CMD_DATE |
e2b65ea9 YS |
271 | |
272 | /* EEPROM */ | |
273 | #define CONFIG_ID_EEPROM | |
274 | #define CONFIG_CMD_EEPROM | |
275 | #define CONFIG_SYS_I2C_EEPROM_NXID | |
276 | #define CONFIG_SYS_EEPROM_BUS_NUM 0 | |
277 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 | |
278 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
279 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
280 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 | |
281 | ||
e2b65ea9 YS |
282 | #define CONFIG_FSL_MEMAC |
283 | #define CONFIG_PCI /* Enable PCIE */ | |
284 | #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ | |
285 | ||
286 | #ifdef CONFIG_PCI | |
e2b65ea9 | 287 | #define CONFIG_PCI_PNP |
e2b65ea9 YS |
288 | #define CONFIG_PCI_SCAN_SHOW |
289 | #define CONFIG_CMD_PCI | |
e2b65ea9 YS |
290 | #endif |
291 | ||
8b06460e YL |
292 | /* MMC */ |
293 | #define CONFIG_MMC | |
294 | #ifdef CONFIG_MMC | |
295 | #define CONFIG_CMD_MMC | |
296 | #define CONFIG_FSL_ESDHC | |
297 | #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 | |
298 | #define CONFIG_GENERIC_MMC | |
299 | #define CONFIG_CMD_FAT | |
300 | #define CONFIG_DOS_PARTITION | |
301 | #endif | |
e2b65ea9 | 302 | |
5a4d744c YL |
303 | #define CONFIG_MISC_INIT_R |
304 | ||
e16b604e NB |
305 | /* |
306 | * USB | |
307 | */ | |
308 | #define CONFIG_HAS_FSL_XHCI_USB | |
309 | #define CONFIG_USB_XHCI | |
310 | #define CONFIG_USB_XHCI_FSL | |
311 | #define CONFIG_USB_XHCI_DWC3 | |
312 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 | |
313 | #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 | |
314 | #define CONFIG_CMD_USB | |
315 | #define CONFIG_USB_STORAGE | |
316 | #define CONFIG_CMD_EXT2 | |
317 | ||
e2b65ea9 YS |
318 | /* Initial environment variables */ |
319 | #undef CONFIG_EXTRA_ENV_SETTINGS | |
320 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
321 | "hwconfig=fsl_ddr:bank_intlv=auto\0" \ | |
322 | "loadaddr=0x80100000\0" \ | |
323 | "kernel_addr=0x100000\0" \ | |
324 | "ramdisk_addr=0x800000\0" \ | |
325 | "ramdisk_size=0x2000000\0" \ | |
326 | "fdt_high=0xa0000000\0" \ | |
327 | "initrd_high=0xffffffffffffffff\0" \ | |
328 | "kernel_start=0x581100000\0" \ | |
329 | "kernel_load=0xa0000000\0" \ | |
97421bd2 | 330 | "kernel_size=0x2800000\0" |
e2b65ea9 | 331 | |
56cd0760 PK |
332 | #undef CONFIG_BOOTARGS |
333 | #define CONFIG_BOOTARGS "console=ttyS1,115200 root=/dev/ram0 " \ | |
b22b1dc6 | 334 | "earlycon=uart8250,mmio,0x21c0600" \ |
56cd0760 PK |
335 | "ramdisk_size=0x2000000 default_hugepagesz=2m" \ |
336 | " hugepagesz=2m hugepages=16" | |
337 | ||
3484d953 PK |
338 | /* MAC/PHY configuration */ |
339 | #ifdef CONFIG_FSL_MC_ENET | |
340 | #define CONFIG_PHYLIB_10G | |
c69384e1 | 341 | #define CONFIG_PHY_AQUANTIA |
3484d953 PK |
342 | #define CONFIG_PHY_CORTINA |
343 | #define CONFIG_PHYLIB | |
344 | #define CONFIG_SYS_CORTINA_FW_IN_NOR | |
345 | #define CONFIG_CORTINA_FW_ADDR 0x581000000 | |
346 | #define CONFIG_CORTINA_FW_LENGTH 0x40000 | |
347 | ||
348 | #define CORTINA_PHY_ADDR1 0x10 | |
349 | #define CORTINA_PHY_ADDR2 0x11 | |
350 | #define CORTINA_PHY_ADDR3 0x12 | |
351 | #define CORTINA_PHY_ADDR4 0x13 | |
352 | #define AQ_PHY_ADDR1 0x00 | |
353 | #define AQ_PHY_ADDR2 0x01 | |
354 | #define AQ_PHY_ADDR3 0x02 | |
355 | #define AQ_PHY_ADDR4 0x03 | |
356 | ||
357 | #define CONFIG_MII | |
358 | #define CONFIG_ETHPRIME "DPNI1" | |
359 | #define CONFIG_PHY_GIGE | |
95279315 | 360 | #define CONFIG_PHY_AQUANTIA |
3484d953 PK |
361 | #endif |
362 | ||
e2b65ea9 | 363 | #endif /* __LS2_RDB_H */ |