[people/ms/u-boot.git] / include / configs / ls2080ardb.h

/*
 * Copyright 2017 NXP
 * Copyright 2015 Freescale Semiconductor
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __LS2_RDB_H
#define __LS2_RDB_H

#include "ls2080a_common.h"

#undef CONFIG_CONS_INDEX
#define CONFIG_CONS_INDEX       2

#ifdef CONFIG_FSL_QSPI
#ifdef CONFIG_TARGET_LS2081ARDB
#define CONFIG_QIXIS_I2C_ACCESS
#endif
#define CONFIG_SYS_I2C_EARLY_INIT
#endif

#define I2C_MUX_CH_VOL_MONITOR		0xa
#define I2C_VOL_MONITOR_ADDR		0x38
#define CONFIG_VOL_MONITOR_IR36021_READ
#define CONFIG_VOL_MONITOR_IR36021_SET

#define CONFIG_VID_FLS_ENV		"ls2080ardb_vdd_mv"
#ifndef CONFIG_SPL_BUILD
#define CONFIG_VID
#endif
/* step the IR regulator in 5mV increments */
#define IR_VDD_STEP_DOWN		5
#define IR_VDD_STEP_UP			5
/* The lowest and highest voltage allowed for LS2080ARDB */
#define VDD_MV_MIN			819
#define VDD_MV_MAX			1212

#ifndef __ASSEMBLY__
unsigned long get_board_sys_clk(void);
#endif

#define CONFIG_SYS_CLK_FREQ		get_board_sys_clk()
#define CONFIG_DDR_CLK_FREQ		133333333
#define COUNTER_FREQUENCY_REAL		(CONFIG_SYS_CLK_FREQ/4)

#define CONFIG_DDR_SPD
#define CONFIG_DDR_ECC
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
#define SPD_EEPROM_ADDRESS1	0x51
#define SPD_EEPROM_ADDRESS2	0x52
#define SPD_EEPROM_ADDRESS3	0x53
#define SPD_EEPROM_ADDRESS4	0x54
#define SPD_EEPROM_ADDRESS5	0x55
#define SPD_EEPROM_ADDRESS6	0x56	/* dummy address */
#define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1
#define CONFIG_SYS_SPD_BUS_NUM	0	/* SPD on I2C bus 0 */
#define CONFIG_DIMM_SLOTS_PER_CTLR		2
#define CONFIG_CHIP_SELECTS_PER_CTRL		4
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR	1
#endif
#define CONFIG_FSL_DDR_BIST	/* enable built-in memory test */

/* SATA */
#define CONFIG_LIBATA
#define CONFIG_SCSI_AHCI_PLAT

#define CONFIG_SYS_SATA1			AHCI_BASE_ADDR1
#define CONFIG_SYS_SATA2			AHCI_BASE_ADDR2

#define CONFIG_SYS_SCSI_MAX_SCSI_ID		1
#define CONFIG_SYS_SCSI_MAX_LUN			1
#define CONFIG_SYS_SCSI_MAX_DEVICE		(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
						CONFIG_SYS_SCSI_MAX_LUN)

#ifndef CONFIG_FSL_QSPI
/* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */

#define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
#define CONFIG_SYS_NOR_AMASK		IFC_AMASK(128*1024*1024)
#define CONFIG_SYS_NOR_AMASK_EARLY	IFC_AMASK(64*1024*1024)

#define CONFIG_SYS_NOR0_CSPR					\
	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)		| \
	CSPR_PORT_SIZE_16					| \
	CSPR_MSEL_NOR						| \
	CSPR_V)
#define CONFIG_SYS_NOR0_CSPR_EARLY				\
	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)	| \
	CSPR_PORT_SIZE_16					| \
	CSPR_MSEL_NOR						| \
	CSPR_V)
#define CONFIG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(12)
#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
				FTIM0_NOR_TEADC(0x5) | \
				FTIM0_NOR_TEAHC(0x5))
#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
				FTIM1_NOR_TRAD_NOR(0x1a) |\
				FTIM1_NOR_TSEQRAD_NOR(0x13))
#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
				FTIM2_NOR_TCH(0x4) | \
				FTIM2_NOR_TWPH(0x0E) | \
				FTIM2_NOR_TWP(0x1c))
#define CONFIG_SYS_NOR_FTIM3	0x04000000
#define CONFIG_SYS_IFC_CCR	0x01000000

#ifdef CONFIG_MTD_NOR_FLASH
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */

#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */

#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE,\
					 CONFIG_SYS_FLASH_BASE + 0x40000000}
#endif

#define CONFIG_NAND_FSL_IFC
#define CONFIG_SYS_NAND_MAX_ECCPOS	256
#define CONFIG_SYS_NAND_MAX_OOBFREE	2

#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
				| CSPR_V)
#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)

#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
				| CSOR_NAND_RAL_3	/* RAL = 3Byes */ \
				| CSOR_NAND_PGS_4K	/* Page Size = 4K */ \
				| CSOR_NAND_SPRZ_224	/* Spare size = 224 */ \
				| CSOR_NAND_PB(128))	/* Pages Per Block 128*/

#define CONFIG_SYS_NAND_ONFI_DETECTION

/* ONFI NAND Flash mode0 Timing Params */
#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x0e) | \
					FTIM0_NAND_TWP(0x30)   | \
					FTIM0_NAND_TWCHT(0x0e) | \
					FTIM0_NAND_TWH(0x14))
#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x64) | \
					FTIM1_NAND_TWBE(0xab)  | \
					FTIM1_NAND_TRR(0x1c)   | \
					FTIM1_NAND_TRP(0x30))
#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x1e) | \
					FTIM2_NAND_TREH(0x14) | \
					FTIM2_NAND_TWHRE(0x3c))
#define CONFIG_SYS_NAND_FTIM3		0x0

#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_MTD_NAND_VERIFY_WRITE

#define CONFIG_SYS_NAND_BLOCK_SIZE	(512 * 1024)
#define CONFIG_FSL_QIXIS	/* use common QIXIS code */
#define QIXIS_LBMAP_SWITCH		0x06
#define QIXIS_LBMAP_MASK		0x0f
#define QIXIS_LBMAP_SHIFT		0
#define QIXIS_LBMAP_DFLTBANK		0x00
#define QIXIS_LBMAP_ALTBANK		0x04
#define QIXIS_LBMAP_NAND		0x09
#define QIXIS_RST_CTL_RESET		0x31
#define QIXIS_RST_CTL_RESET_EN		0x30
#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
#define QIXIS_RCW_SRC_NAND		0x119
#define	QIXIS_RST_FORCE_MEM		0x01

#define CONFIG_SYS_CSPR3_EXT	(0x0)
#define CONFIG_SYS_CSPR3	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
				| CSPR_PORT_SIZE_8 \
				| CSPR_MSEL_GPCM \
				| CSPR_V)
#define CONFIG_SYS_CSPR3_FINAL	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
				| CSPR_PORT_SIZE_8 \
				| CSPR_MSEL_GPCM \
				| CSPR_V)

#define CONFIG_SYS_AMASK3	IFC_AMASK(64*1024)
#define CONFIG_SYS_CSOR3	CSOR_GPCM_ADM_SHIFT(12)
/* QIXIS Timing parameters for IFC CS3 */
#define CONFIG_SYS_CS3_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
					FTIM0_GPCM_TEADC(0x0e) | \
					FTIM0_GPCM_TEAHC(0x0e))
#define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
					FTIM1_GPCM_TRAD(0x3f))
#define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0xf) | \
					FTIM2_GPCM_TCH(0xf) | \
					FTIM2_GPCM_TWP(0x3E))
#define CONFIG_SYS_CS3_FTIM3		0x0

#if defined(CONFIG_SPL) && defined(CONFIG_NAND)
#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR0_CSPR_EARLY
#define CONFIG_SYS_CSPR2_FINAL		CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3

#define CONFIG_ENV_OFFSET		(2048 * 1024)
#define CONFIG_ENV_SECT_SIZE		0x20000
#define CONFIG_ENV_SIZE			0x2000
#define CONFIG_SPL_PAD_TO		0x80000
#define CONFIG_SYS_NAND_U_BOOT_OFFS	(1024 * 1024)
#define CONFIG_SYS_NAND_U_BOOT_SIZE	(512 * 1024)
#else
#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR_EARLY
#define CONFIG_SYS_CSPR0_FINAL		CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3

#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x300000)
#define CONFIG_ENV_SECT_SIZE		0x20000
#define CONFIG_ENV_SIZE			0x2000
#endif

/* Debug Server firmware */
#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR	0x580D00000ULL
#endif
#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000

#ifdef CONFIG_TARGET_LS2081ARDB
#define CONFIG_FSL_QIXIS	/* use common QIXIS code */
#define QIXIS_QMAP_MASK			0x07
#define QIXIS_QMAP_SHIFT		5
#define QIXIS_LBMAP_DFLTBANK		0x00
#define QIXIS_LBMAP_QSPI		0x00
#define QIXIS_RCW_SRC_QSPI		0x62
#define QIXIS_LBMAP_ALTBANK		0x20
#define QIXIS_RST_CTL_RESET		0x31
#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
#define QIXIS_LBMAP_MASK		0x0f
#define QIXIS_RST_CTL_RESET_EN		0x30
#endif

/*
 * I2C
 */
#ifdef CONFIG_TARGET_LS2081ARDB
#define CONFIG_SYS_I2C_FPGA_ADDR	0x66
#endif
#define I2C_MUX_PCA_ADDR		0x75
#define I2C_MUX_PCA_ADDR_PRI		0x75 /* Primary Mux*/

/* I2C bus multiplexer */
#define I2C_MUX_CH_DEFAULT      0x8

/* SPI */
#if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI)
#define CONFIG_SPI_FLASH
#ifdef CONFIG_FSL_DSPI
#define CONFIG_SPI_FLASH_STMICRO
#endif
#ifdef CONFIG_FSL_QSPI
#define CONFIG_SPI_FLASH_SPANSION
#endif
#define FSL_QSPI_FLASH_SIZE		SZ_64M	/* 64MB */
#define FSL_QSPI_FLASH_NUM		2
#endif

/*
 * RTC configuration
 */
#define RTC
#ifdef CONFIG_TARGET_LS2081ARDB
#define CONFIG_RTC_PCF8563		1
#define CONFIG_SYS_I2C_RTC_ADDR         0x51
#else
#define CONFIG_RTC_DS3231               1
#define CONFIG_SYS_I2C_RTC_ADDR         0x68
#endif

/* EEPROM */
#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM	0
#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5

#define CONFIG_FSL_MEMAC

#ifdef CONFIG_PCI
#define CONFIG_PCI_SCAN_SHOW
#endif

/*  MMC  */
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif

#define CONFIG_MISC_INIT_R

#undef CONFIG_CMDLINE_EDITING
#include <config_distro_defaults.h>

#define BOOT_TARGET_DEVICES(func) \
	func(USB, usb, 0) \
	func(MMC, mmc, 0) \
	func(SCSI, scsi, 0) \
	func(DHCP, dhcp, na)
#include <config_distro_bootcmd.h>

#ifdef CONFIG_QSPI_BOOT
#define MC_INIT_CMD				\
	"mcinitcmd=env exists secureboot && "	\
	"esbc_validate 0x20700000 && "		\
	"esbc_validate 0x20740000;"		\
	"fsl_mc start mc 0x20a00000 0x20e00000 \0"
#elif defined(CONFIG_SD_BOOT)
#define MC_INIT_CMD                             \
	"mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \
	"mmc read 0x80100000 0x7000 0x800;"	\
	"env exists secureboot && "		\
	"mmc read 0x80700000 0x3800 0x10 && "	\
	"mmc read 0x80740000 0x3A00 0x10 && "	\
	"esbc_validate 0x80700000 && "		\
	"esbc_validate 0x80740000 ;"		\
	"fsl_mc start mc 0x80000000 0x80100000\0" \
	"mcmemsize=0x70000000\0"
#else
#define MC_INIT_CMD				\
	"mcinitcmd=env exists secureboot && "	\
	"esbc_validate 0x580700000 && "		\
	"esbc_validate 0x580740000; "		\
	"fsl_mc start mc 0x580a00000 0x580e00000 \0"
#endif

/* Initial environment variables */
#undef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
	"ramdisk_addr=0x800000\0"		\
	"ramdisk_size=0x2000000\0"		\
	"fdt_high=0xa0000000\0"			\
	"initrd_high=0xffffffffffffffff\0"	\
	"fdt_addr=0x64f00000\0"			\
	"kernel_addr=0x65000000\0"		\
	"kernel_start=0x1000000\0"		\
	"kernelheader_start=0x800000\0"		\
	"scriptaddr=0x80000000\0"		\
	"scripthdraddr=0x80080000\0"		\
	"fdtheader_addr_r=0x80100000\0"		\
	"kernelheader_addr_r=0x80200000\0"	\
	"kernelheader_addr=0x580800000\0"	\
	"kernel_addr_r=0x81000000\0"		\
	"kernelheader_size=0x40000\0"		\
	"fdt_addr_r=0x90000000\0"		\
	"load_addr=0xa0000000\0"		\
	"kernel_size=0x2800000\0"		\
	"kernel_addr_sd=0x8000\0"		\
	"kernel_size_sd=0x14000\0"              \
	"console=ttyAMA0,38400n8\0"		\
	"mcmemsize=0x70000000\0"		\
	"sd_bootcmd=echo Trying load from SD ..;" \
	"mmcinfo; mmc read $load_addr "		\
	"$kernel_addr_sd $kernel_size_sd && "	\
	"bootm $load_addr#$board\0"             \
	MC_INIT_CMD				\
	BOOTENV					\
	"boot_scripts=ls2088ardb_boot.scr\0"	\
	"boot_script_hdr=hdr_ls2088ardb_bs.out\0"	\
	"scan_dev_for_boot_part="		\
		"part list ${devtype} ${devnum} devplist; "	\
		"env exists devplist || setenv devplist 1; "	\
		"for distro_bootpart in ${devplist}; do "	\
			"if fstype ${devtype} "			\
				"${devnum}:${distro_bootpart} "	\
				"bootfstype; then "		\
				"run scan_dev_for_boot; "	\
			"fi; "					\
		"done\0"					\
	"scan_dev_for_boot="					\
		"echo Scanning ${devtype} "			\
			"${devnum}:${distro_bootpart}...; "	\
		"for prefix in ${boot_prefixes}; do "		\
			"run scan_dev_for_scripts; "		\
		"done;\0"					\
	"boot_a_script="					\
		"load ${devtype} ${devnum}:${distro_bootpart} "	\
			"${scriptaddr} ${prefix}${script}; "	\
		"env exists secureboot && load ${devtype} "	\
			"${devnum}:${distro_bootpart} "		\
			"${scripthdraddr} ${prefix}${boot_script_hdr} "	\
			"&& esbc_validate ${scripthdraddr};"	\
		"source ${scriptaddr}\0"			\
	"qspi_bootcmd=echo Trying load from qspi..;"		\
		"sf probe && sf read $load_addr "		\
		"$kernel_start $kernel_size ; env exists secureboot &&"	\
		"sf read $kernelheader_addr_r $kernelheader_start "	\
		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
		" bootm $load_addr#$board\0"			\
	"nor_bootcmd=echo Trying load from nor..;"		\
		"cp.b $kernel_addr $load_addr "			\
		"$kernel_size ; env exists secureboot && "	\
		"cp.b $kernelheader_addr $kernelheader_addr_r "	\
		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
		"bootm $load_addr#$board\0"

#undef CONFIG_BOOTCOMMAND
#ifdef CONFIG_QSPI_BOOT
/* Try to boot an on-QSPI kernel first, then do normal distro boot */
#define CONFIG_BOOTCOMMAND						\
			"env exists mcinitcmd && env exists secureboot "\
			"&& esbc_validate 0x20780000; "			\
			"env exists mcinitcmd && "			\
			"fsl_mc lazyapply dpl 0x20d00000; "		\
			"run distro_bootcmd;env exists secureboot "	\
			" && esbc_halt;run qspi_bootcmd; "
#elif defined(CONFIG_SD_BOOT)
/* Try to boot an on-SD kernel first, then do normal distro boot */
#define CONFIG_BOOTCOMMAND						\
			"env exists mcinitcmd && env exists secureboot "\
			"&& mmcinfo && mmc read $load_addr 0x3c00 0x800 " \
			"&& esbc_validate $load_addr; "			\
			"env exists mcinitcmd && run mcinitcmd "	\
			"&& mmc read 0x88000000 0x6800 0x800 "		\
			"&& fsl_mc lazyapply dpl 0x88000000; "		\
			"run distro_bootcmd;env exists secureboot "	\
			"&& esbc_halt;run sd_bootcmd;"
#else
/* Try to boot an on-NOR kernel first, then do normal distro boot */
#define CONFIG_BOOTCOMMAND						\
			"env exists mcinitcmd && env exists secureboot "\
			"&& esbc_validate 0x580780000; env exists mcinitcmd "\
			"&& fsl_mc lazyapply dpl 0x580d00000;"		\
			"run distro_bootcmd; env exists secureboot "	\
			"&& esbc_halt; run nor_bootcmd;"
#endif

/* MAC/PHY configuration */
#ifdef CONFIG_FSL_MC_ENET
#define CONFIG_PHYLIB_10G
#define CONFIG_PHY_AQUANTIA
#define CONFIG_PHY_CORTINA
#define	CONFIG_SYS_CORTINA_FW_IN_NOR
#ifdef CONFIG_QSPI_BOOT
#define CONFIG_CORTINA_FW_ADDR		0x20980000
#else
#define CONFIG_CORTINA_FW_ADDR		0x580980000
#endif
#define CONFIG_CORTINA_FW_LENGTH	0x40000

#define CORTINA_PHY_ADDR1	0x10
#define CORTINA_PHY_ADDR2	0x11
#define CORTINA_PHY_ADDR3	0x12
#define CORTINA_PHY_ADDR4	0x13
#define AQ_PHY_ADDR1		0x00
#define AQ_PHY_ADDR2		0x01
#define AQ_PHY_ADDR3		0x02
#define AQ_PHY_ADDR4		0x03
#define AQR405_IRQ_MASK		0x36

#define CONFIG_MII
#define CONFIG_ETHPRIME		"DPMAC1@xgmii"
#define CONFIG_PHY_AQUANTIA
#endif

#include <asm/fsl_secure_boot.h>

#endif /* __LS2_RDB_H */
Commit	Line	Data
e2b65ea9	1	/*
89a168f7	2	* Copyright 2017 NXP
e2b65ea9 YS	3	* Copyright 2015 Freescale Semiconductor
	4	*
	5	* SPDX-License-Identifier: GPL-2.0+
	6	*/
	7
	8	#ifndef __LS2_RDB_H
	9	#define __LS2_RDB_H
	10
44937214	11	#include "ls2080a_common.h"
e2b65ea9 YS	12
	13	#undef CONFIG_CONS_INDEX
	14	#define CONFIG_CONS_INDEX 2
	15
89a168f7	16	#ifdef CONFIG_FSL_QSPI
3049a583 PJ	17	#ifdef CONFIG_TARGET_LS2081ARDB
	18	#define CONFIG_QIXIS_I2C_ACCESS
	19	#endif
89a168f7	20	#define CONFIG_SYS_I2C_EARLY_INIT
89a168f7 PJ	21	#endif
89a168f7 PJ	22
ed2530d0 RH	23	#define I2C_MUX_CH_VOL_MONITOR 0xa
	24	#define I2C_VOL_MONITOR_ADDR 0x38
	25	#define CONFIG_VOL_MONITOR_IR36021_READ
	26	#define CONFIG_VOL_MONITOR_IR36021_SET
	27
	28	#define CONFIG_VID_FLS_ENV "ls2080ardb_vdd_mv"
	29	#ifndef CONFIG_SPL_BUILD
	30	#define CONFIG_VID
	31	#endif
	32	/* step the IR regulator in 5mV increments */
	33	#define IR_VDD_STEP_DOWN 5
	34	#define IR_VDD_STEP_UP 5
	35	/* The lowest and highest voltage allowed for LS2080ARDB */
	36	#define VDD_MV_MIN 819
	37	#define VDD_MV_MAX 1212
	38
e2b65ea9 YS	39	#ifndef __ASSEMBLY__
	40	unsigned long get_board_sys_clk(void);
	41	#endif
	42
	43	#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
	44	#define CONFIG_DDR_CLK_FREQ 133333333
	45	#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
	46
	47	#define CONFIG_DDR_SPD
	48	#define CONFIG_DDR_ECC
	49	#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
	50	#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
	51	#define SPD_EEPROM_ADDRESS1 0x51
	52	#define SPD_EEPROM_ADDRESS2 0x52
fc7b3855 YS	53	#define SPD_EEPROM_ADDRESS3 0x53
fc7b3855 YS	54	#define SPD_EEPROM_ADDRESS4 0x54
e2b65ea9 YS	55	#define SPD_EEPROM_ADDRESS5 0x55
	56	#define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */
	57	#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
	58	#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
	59	#define CONFIG_DIMM_SLOTS_PER_CTLR 2
	60	#define CONFIG_CHIP_SELECTS_PER_CTRL 4
44937214	61	#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
e2b65ea9	62	#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
44937214	63	#endif
e2b65ea9 YS	64	#define CONFIG_FSL_DDR_BIST /* enable built-in memory test */
e2b65ea9 YS	65
989c5f0a TY	66	/* SATA */
989c5f0a TY	67	#define CONFIG_LIBATA
989c5f0a	68	#define CONFIG_SCSI_AHCI_PLAT
989c5f0a TY	69
	70	#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
	71	#define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2
	72
	73	#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
	74	#define CONFIG_SYS_SCSI_MAX_LUN 1
	75	#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
	76	CONFIG_SYS_SCSI_MAX_LUN)
	77
89a168f7	78	#ifndef CONFIG_FSL_QSPI
e2b65ea9 YS	79	/* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */
	80
	81	#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
	82	#define CONFIG_SYS_NOR_AMASK IFC_AMASK(12810241024)
	83	#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(6410241024)
	84
	85	#define CONFIG_SYS_NOR0_CSPR \
	86	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \| \
	87	CSPR_PORT_SIZE_16 \| \
	88	CSPR_MSEL_NOR \| \
	89	CSPR_V)
	90	#define CONFIG_SYS_NOR0_CSPR_EARLY \
	91	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) \| \
	92	CSPR_PORT_SIZE_16 \| \
	93	CSPR_MSEL_NOR \| \
	94	CSPR_V)
	95	#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
	96	#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) \| \
	97	FTIM0_NOR_TEADC(0x5) \| \
	98	FTIM0_NOR_TEAHC(0x5))
	99	#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) \| \
	100	FTIM1_NOR_TRAD_NOR(0x1a) \|\
	101	FTIM1_NOR_TSEQRAD_NOR(0x13))
	102	#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) \| \
	103	FTIM2_NOR_TCH(0x4) \| \
	104	FTIM2_NOR_TWPH(0x0E) \| \
	105	FTIM2_NOR_TWP(0x1c))
	106	#define CONFIG_SYS_NOR_FTIM3 0x04000000
	107	#define CONFIG_SYS_IFC_CCR 0x01000000
	108
e856bdcf	109	#ifdef CONFIG_MTD_NOR_FLASH
e2b65ea9 YS	110	#define CONFIG_FLASH_CFI_DRIVER
	111	#define CONFIG_SYS_FLASH_CFI
	112	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
	113	#define CONFIG_SYS_FLASH_QUIET_TEST
	114	#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
	115
	116	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
	117	#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
	118	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	119	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
	120
	121	#define CONFIG_SYS_FLASH_EMPTY_INFO
	122	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
	123	CONFIG_SYS_FLASH_BASE + 0x40000000}
	124	#endif
	125
	126	#define CONFIG_NAND_FSL_IFC
	127	#define CONFIG_SYS_NAND_MAX_ECCPOS 256
	128	#define CONFIG_SYS_NAND_MAX_OOBFREE 2
	129
e2b65ea9 YS	130	#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
	131	#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
	132	\| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
	133	\| CSPR_MSEL_NAND /* MSEL = NAND */ \
	134	\| CSPR_V)
	135	#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
	136
	137	#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
	138	\| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
	139	\| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
	140	\| CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
	141	\| CSOR_NAND_PGS_4K /* Page Size = 4K */ \
	142	\| CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
	143	\| CSOR_NAND_PB(128)) /* Pages Per Block 128*/
	144
	145	#define CONFIG_SYS_NAND_ONFI_DETECTION
	146
	147	/* ONFI NAND Flash mode0 Timing Params */
	148	#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x0e) \| \
	149	FTIM0_NAND_TWP(0x30) \| \
	150	FTIM0_NAND_TWCHT(0x0e) \| \
	151	FTIM0_NAND_TWH(0x14))
	152	#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x64) \| \
	153	FTIM1_NAND_TWBE(0xab) \| \
	154	FTIM1_NAND_TRR(0x1c) \| \
	155	FTIM1_NAND_TRP(0x30))
	156	#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x1e) \| \
	157	FTIM2_NAND_TREH(0x14) \| \
	158	FTIM2_NAND_TWHRE(0x3c))
	159	#define CONFIG_SYS_NAND_FTIM3 0x0
	160
	161	#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
	162	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	163	#define CONFIG_MTD_NAND_VERIFY_WRITE
e2b65ea9 YS	164
e2b65ea9 YS	165	#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
e2b65ea9 YS	166	#define CONFIG_FSL_QIXIS /* use common QIXIS code */
	167	#define QIXIS_LBMAP_SWITCH 0x06
	168	#define QIXIS_LBMAP_MASK 0x0f
	169	#define QIXIS_LBMAP_SHIFT 0
	170	#define QIXIS_LBMAP_DFLTBANK 0x00
	171	#define QIXIS_LBMAP_ALTBANK 0x04
32eda7cc	172	#define QIXIS_LBMAP_NAND 0x09
e2b65ea9 YS	173	#define QIXIS_RST_CTL_RESET 0x31
	174	#define QIXIS_RST_CTL_RESET_EN 0x30
	175	#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
	176	#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
	177	#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
32eda7cc	178	#define QIXIS_RCW_SRC_NAND 0x119
e2b65ea9 YS	179	#define QIXIS_RST_FORCE_MEM 0x01
	180
	181	#define CONFIG_SYS_CSPR3_EXT (0x0)
	182	#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
	183	\| CSPR_PORT_SIZE_8 \
	184	\| CSPR_MSEL_GPCM \
	185	\| CSPR_V)
	186	#define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
	187	\| CSPR_PORT_SIZE_8 \
	188	\| CSPR_MSEL_GPCM \
	189	\| CSPR_V)
	190
	191	#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
	192	#define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12)
	193	/* QIXIS Timing parameters for IFC CS3 */
	194	#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) \| \
	195	FTIM0_GPCM_TEADC(0x0e) \| \
	196	FTIM0_GPCM_TEAHC(0x0e))
	197	#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) \| \
	198	FTIM1_GPCM_TRAD(0x3f))
	199	#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) \| \
	200	FTIM2_GPCM_TCH(0xf) \| \
	201	FTIM2_GPCM_TWP(0x3E))
	202	#define CONFIG_SYS_CS3_FTIM3 0x0
	203
32eda7cc SW	204	#if defined(CONFIG_SPL) && defined(CONFIG_NAND)
	205	#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
	206	#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR_EARLY
	207	#define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR0_CSPR
	208	#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
	209	#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
	210	#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
	211	#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
	212	#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
	213	#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
	214	#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
	215	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
	216	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
	217	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
	218	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
	219	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
	220	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
	221	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
	222
32eda7cc SW	223	#define CONFIG_ENV_OFFSET (2048 * 1024)
	224	#define CONFIG_ENV_SECT_SIZE 0x20000
	225	#define CONFIG_ENV_SIZE 0x2000
	226	#define CONFIG_SPL_PAD_TO 0x80000
	227	#define CONFIG_SYS_NAND_U_BOOT_OFFS (1024 * 1024)
	228	#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024)
	229	#else
e2b65ea9 YS	230	#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
	231	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
	232	#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
	233	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
	234	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
	235	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
	236	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
	237	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
	238	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
	239	#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
	240	#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
	241	#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
	242	#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
	243	#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
	244	#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
	245	#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
	246	#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
	247
f5bf23d8	248	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
32eda7cc SW	249	#define CONFIG_ENV_SECT_SIZE 0x20000
	250	#define CONFIG_ENV_SIZE 0x2000
	251	#endif
	252
e2b65ea9 YS	253	/* Debug Server firmware */
	254	#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
	255	#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
89a168f7	256	#endif
e2b65ea9 YS	257	#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
e2b65ea9 YS	258
3049a583 PJ	259	#ifdef CONFIG_TARGET_LS2081ARDB
	260	#define CONFIG_FSL_QIXIS /* use common QIXIS code */
	261	#define QIXIS_QMAP_MASK 0x07
	262	#define QIXIS_QMAP_SHIFT 5
	263	#define QIXIS_LBMAP_DFLTBANK 0x00
	264	#define QIXIS_LBMAP_QSPI 0x00
	265	#define QIXIS_RCW_SRC_QSPI 0x62
	266	#define QIXIS_LBMAP_ALTBANK 0x20
	267	#define QIXIS_RST_CTL_RESET 0x31
	268	#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
	269	#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
	270	#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
	271	#define QIXIS_LBMAP_MASK 0x0f
	272	#define QIXIS_RST_CTL_RESET_EN 0x30
	273	#endif
	274
e2b65ea9 YS	275	/*
	276	* I2C
	277	*/
3049a583 PJ	278	#ifdef CONFIG_TARGET_LS2081ARDB
	279	#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
	280	#endif
4012350d PK	281	#define I2C_MUX_PCA_ADDR 0x75
4012350d PK	282	#define I2C_MUX_PCA_ADDR_PRI 0x75 /* Primary Mux*/
e2b65ea9 YS	283
	284	/* I2C bus multiplexer */
	285	#define I2C_MUX_CH_DEFAULT 0x8
	286
0c42a8de	287	/* SPI */
89a168f7	288	#if defined(CONFIG_FSL_QSPI) \|\| defined(CONFIG_FSL_DSPI)
0c42a8de	289	#define CONFIG_SPI_FLASH
77dc01bd	290	#ifdef CONFIG_FSL_DSPI
21640db5	291	#define CONFIG_SPI_FLASH_STMICRO
0c42a8de	292	#endif
89a168f7 PJ	293	#ifdef CONFIG_FSL_QSPI
89a168f7 PJ	294	#define CONFIG_SPI_FLASH_SPANSION
3049a583	295	#endif
89a168f7 PJ	296	#define FSL_QSPI_FLASH_SIZE SZ_64M /* 64MB */
	297	#define FSL_QSPI_FLASH_NUM 2
	298	#endif
0c42a8de	299
e2b65ea9 YS	300	/*
	301	* RTC configuration
	302	*/
	303	#define RTC
3049a583 PJ	304	#ifdef CONFIG_TARGET_LS2081ARDB
	305	#define CONFIG_RTC_PCF8563 1
	306	#define CONFIG_SYS_I2C_RTC_ADDR 0x51
	307	#else
e2b65ea9 YS	308	#define CONFIG_RTC_DS3231 1
e2b65ea9 YS	309	#define CONFIG_SYS_I2C_RTC_ADDR 0x68
3049a583	310	#endif
e2b65ea9 YS	311
	312	/* EEPROM */
	313	#define CONFIG_ID_EEPROM
e2b65ea9 YS	314	#define CONFIG_SYS_I2C_EEPROM_NXID
	315	#define CONFIG_SYS_EEPROM_BUS_NUM 0
	316	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
	317	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	318	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
	319	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
	320
e2b65ea9	321	#define CONFIG_FSL_MEMAC
e2b65ea9 YS	322
e2b65ea9 YS	323	#ifdef CONFIG_PCI
e2b65ea9	324	#define CONFIG_PCI_SCAN_SHOW
e2b65ea9 YS	325	#endif
e2b65ea9 YS	326
8b06460e	327	/* MMC */
8b06460e	328	#ifdef CONFIG_MMC
8b06460e YL	329	#define CONFIG_FSL_ESDHC
8b06460e YL	330	#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
8b06460e	331	#endif
e2b65ea9	332
5a4d744c YL	333	#define CONFIG_MISC_INIT_R
5a4d744c YL	334
b99ebaf9 AG	335	#undef CONFIG_CMDLINE_EDITING
	336	#include <config_distro_defaults.h>
	337
	338	#define BOOT_TARGET_DEVICES(func) \
	339	func(USB, usb, 0) \
	340	func(MMC, mmc, 0) \
	341	func(SCSI, scsi, 0) \
	342	func(DHCP, dhcp, na)
	343	#include <config_distro_bootcmd.h>
	344
ec85721c VP	345	#ifdef CONFIG_QSPI_BOOT
	346	#define MC_INIT_CMD \
	347	"mcinitcmd=env exists secureboot && " \
	348	"esbc_validate 0x20700000 && " \
	349	"esbc_validate 0x20740000;" \
	350	"fsl_mc start mc 0x20a00000 0x20e00000 \0"
bc085549 SL	351	#elif defined(CONFIG_SD_BOOT)
	352	#define MC_INIT_CMD \
	353	"mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \
	354	"mmc read 0x80100000 0x7000 0x800;" \
	355	"env exists secureboot && " \
	356	"mmc read 0x80700000 0x3800 0x10 && " \
	357	"mmc read 0x80740000 0x3A00 0x10 && " \
	358	"esbc_validate 0x80700000 && " \
	359	"esbc_validate 0x80740000 ;" \
	360	"fsl_mc start mc 0x80000000 0x80100000\0" \
	361	"mcmemsize=0x70000000\0"
ec85721c VP	362	#else
	363	#define MC_INIT_CMD \
	364	"mcinitcmd=env exists secureboot && " \
	365	"esbc_validate 0x580700000 && " \
	366	"esbc_validate 0x580740000; " \
	367	"fsl_mc start mc 0x580a00000 0x580e00000 \0"
	368	#endif
	369
e2b65ea9 YS	370	/* Initial environment variables */
	371	#undef CONFIG_EXTRA_ENV_SETTINGS
	372	#define CONFIG_EXTRA_ENV_SETTINGS \
	373	"hwconfig=fsl_ddr:bank_intlv=auto\0" \
e2b65ea9 YS	374	"ramdisk_addr=0x800000\0" \
	375	"ramdisk_size=0x2000000\0" \
	376	"fdt_high=0xa0000000\0" \
	377	"initrd_high=0xffffffffffffffff\0" \
0a09d20b ZY	378	"fdt_addr=0x64f00000\0" \
0a09d20b ZY	379	"kernel_addr=0x65000000\0" \
ec85721c VP	380	"kernel_start=0x1000000\0" \
ec85721c VP	381	"kernelheader_start=0x800000\0" \
0a09d20b	382	"scriptaddr=0x80000000\0" \
ec85721c	383	"scripthdraddr=0x80080000\0" \
0a09d20b ZY	384	"fdtheader_addr_r=0x80100000\0" \
0a09d20b ZY	385	"kernelheader_addr_r=0x80200000\0" \
ec85721c	386	"kernelheader_addr=0x580800000\0" \
0a09d20b	387	"kernel_addr_r=0x81000000\0" \
ec85721c	388	"kernelheader_size=0x40000\0" \
0a09d20b ZY	389	"fdt_addr_r=0x90000000\0" \
0a09d20b ZY	390	"load_addr=0xa0000000\0" \
16ed8560	391	"kernel_size=0x2800000\0" \
bc085549 SL	392	"kernel_addr_sd=0x8000\0" \
bc085549 SL	393	"kernel_size_sd=0x14000\0" \
0a09d20b	394	"console=ttyAMA0,38400n8\0" \
8472d876	395	"mcmemsize=0x70000000\0" \
bc085549 SL	396	"sd_bootcmd=echo Trying load from SD ..;" \
	397	"mmcinfo; mmc read $load_addr " \
	398	"$kernel_addr_sd $kernel_size_sd && " \
	399	"bootm $load_addr#$board\0" \
ec85721c	400	MC_INIT_CMD \
0a09d20b ZY	401	BOOTENV \
0a09d20b ZY	402	"boot_scripts=ls2088ardb_boot.scr\0" \
ec85721c	403	"boot_script_hdr=hdr_ls2088ardb_bs.out\0" \
0a09d20b ZY	404	"scan_dev_for_boot_part=" \
	405	"part list ${devtype} ${devnum} devplist; " \
	406	"env exists devplist \|\| setenv devplist 1; " \
	407	"for distro_bootpart in ${devplist}; do " \
	408	"if fstype ${devtype} " \
	409	"${devnum}:${distro_bootpart} " \
	410	"bootfstype; then " \
	411	"run scan_dev_for_boot; " \
	412	"fi; " \
	413	"done\0" \
ec85721c VP	414	"scan_dev_for_boot=" \
	415	"echo Scanning ${devtype} " \
	416	"${devnum}:${distro_bootpart}...; " \
	417	"for prefix in ${boot_prefixes}; do " \
	418	"run scan_dev_for_scripts; " \
	419	"done;\0" \
	420	"boot_a_script=" \
	421	"load ${devtype} ${devnum}:${distro_bootpart} " \
	422	"${scriptaddr} ${prefix}${script}; " \
	423	"env exists secureboot && load ${devtype} " \
	424	"${devnum}:${distro_bootpart} " \
	425	"${scripthdraddr} ${prefix}${boot_script_hdr} " \
	426	"&& esbc_validate ${scripthdraddr};" \
	427	"source ${scriptaddr}\0" \
0a09d20b ZY	428	"qspi_bootcmd=echo Trying load from qspi..;" \
0a09d20b ZY	429	"sf probe && sf read $load_addr " \
ec85721c VP	430	"$kernel_start $kernel_size ; env exists secureboot &&" \
	431	"sf read $kernelheader_addr_r $kernelheader_start " \
	432	"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
0a09d20b ZY	433	" bootm $load_addr#$board\0" \
	434	"nor_bootcmd=echo Trying load from nor..;" \
	435	"cp.b $kernel_addr $load_addr " \
ec85721c VP	436	"$kernel_size ; env exists secureboot && " \
	437	"cp.b $kernelheader_addr $kernelheader_addr_r " \
	438	"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
	439	"bootm $load_addr#$board\0"
9ed44787	440
b99ebaf9	441	#undef CONFIG_BOOTCOMMAND
89a168f7	442	#ifdef CONFIG_QSPI_BOOT
89a168f7	443	/* Try to boot an on-QSPI kernel first, then do normal distro boot */
0a09d20b	444	#define CONFIG_BOOTCOMMAND \
ec85721c VP	445	"env exists mcinitcmd && env exists secureboot "\
	446	"&& esbc_validate 0x20780000; " \
	447	"env exists mcinitcmd && " \
	448	"fsl_mc lazyapply dpl 0x20d00000; " \
bc085549 SL	449	"run distro_bootcmd;env exists secureboot " \
	450	" && esbc_halt;run qspi_bootcmd; "
	451	#elif defined(CONFIG_SD_BOOT)
	452	/* Try to boot an on-SD kernel first, then do normal distro boot */
	453	#define CONFIG_BOOTCOMMAND \
	454	"env exists mcinitcmd && env exists secureboot "\
	455	"&& mmcinfo && mmc read $load_addr 0x3c00 0x800 " \
	456	"&& esbc_validate $load_addr; " \
	457	"env exists mcinitcmd && run mcinitcmd " \
	458	"&& mmc read 0x88000000 0x6800 0x800 " \
	459	"&& fsl_mc lazyapply dpl 0x88000000; " \
	460	"run distro_bootcmd;env exists secureboot " \
	461	"&& esbc_halt;run sd_bootcmd;"
9ed44787	462	#else
b99ebaf9	463	/* Try to boot an on-NOR kernel first, then do normal distro boot */
0a09d20b	464	#define CONFIG_BOOTCOMMAND \
ec85721c VP	465	"env exists mcinitcmd && env exists secureboot "\
	466	"&& esbc_validate 0x580780000; env exists mcinitcmd "\
	467	"&& fsl_mc lazyapply dpl 0x580d00000;" \
bc085549 SL	468	"run distro_bootcmd; env exists secureboot " \
bc085549 SL	469	"&& esbc_halt; run nor_bootcmd;"
89a168f7	470	#endif
9ed44787	471
3484d953 PK	472	/* MAC/PHY configuration */
	473	#ifdef CONFIG_FSL_MC_ENET
	474	#define CONFIG_PHYLIB_10G
c69384e1	475	#define CONFIG_PHY_AQUANTIA
3484d953	476	#define CONFIG_PHY_CORTINA
3484d953	477	#define CONFIG_SYS_CORTINA_FW_IN_NOR
89a168f7 PJ	478	#ifdef CONFIG_QSPI_BOOT
	479	#define CONFIG_CORTINA_FW_ADDR 0x20980000
	480	#else
f5bf23d8	481	#define CONFIG_CORTINA_FW_ADDR 0x580980000
89a168f7	482	#endif
3484d953 PK	483	#define CONFIG_CORTINA_FW_LENGTH 0x40000
	484
	485	#define CORTINA_PHY_ADDR1 0x10
	486	#define CORTINA_PHY_ADDR2 0x11
	487	#define CORTINA_PHY_ADDR3 0x12
	488	#define CORTINA_PHY_ADDR4 0x13
	489	#define AQ_PHY_ADDR1 0x00
	490	#define AQ_PHY_ADDR2 0x01
	491	#define AQ_PHY_ADDR3 0x02
	492	#define AQ_PHY_ADDR4 0x03
abc7d0f7	493	#define AQR405_IRQ_MASK 0x36
3484d953 PK	494
3484d953 PK	495	#define CONFIG_MII
7ad9cc96	496	#define CONFIG_ETHPRIME "DPMAC1@xgmii"
95279315	497	#define CONFIG_PHY_AQUANTIA
3484d953 PK	498	#endif
3484d953 PK	499
fcfdb6d5 SJ	500	#include <asm/fsl_secure_boot.h>
fcfdb6d5 SJ	501
e2b65ea9	502	#endif /* __LS2_RDB_H */