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f749db3a YS |
1 | /* |
2 | * Copyright (C) 2014 Freescale Semiconductor | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
6 | ||
7 | #ifndef __LS2_COMMON_H | |
8 | #define __LS2_COMMON_H | |
9 | ||
10 | #define CONFIG_SYS_GENERIC_BOARD | |
11 | ||
12 | #define CONFIG_REMAKE_ELF | |
13 | #define CONFIG_FSL_LSCH3 | |
14 | #define CONFIG_LS2085A | |
15 | #define CONFIG_GICV3 | |
9c66ce66 | 16 | #define CONFIG_FSL_TZPC_BP147 |
f749db3a | 17 | |
1b1069cd BS |
18 | /* Errata fixes */ |
19 | #define CONFIG_ARM_ERRATA_828024 | |
20 | #define CONFIG_ARM_ERRATA_826974 | |
21 | ||
422cb08a BS |
22 | /* We need architecture specific misc initializations */ |
23 | #define CONFIG_ARCH_MISC_INIT | |
24 | ||
f749db3a | 25 | /* Link Definitions */ |
f3f8c564 | 26 | #define CONFIG_SYS_TEXT_BASE 0x30100000 |
f749db3a | 27 | |
e211c12e | 28 | #ifdef CONFIG_EMU |
f749db3a | 29 | #define CONFIG_SYS_NO_FLASH |
e211c12e | 30 | #endif |
f749db3a YS |
31 | |
32 | #define CONFIG_SUPPORT_RAW_INITRD | |
33 | ||
34 | #define CONFIG_SKIP_LOWLEVEL_INIT | |
35 | #define CONFIG_BOARD_EARLY_INIT_F 1 | |
36 | ||
f749db3a YS |
37 | /* Flat Device Tree Definitions */ |
38 | #define CONFIG_OF_LIBFDT | |
39 | #define CONFIG_OF_BOARD_SETUP | |
40 | ||
41 | /* new uImage format support */ | |
42 | #define CONFIG_FIT | |
43 | #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ | |
44 | ||
45 | #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ | |
46 | #ifndef CONFIG_SYS_FSL_DDR4 | |
47 | #define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */ | |
48 | #define CONFIG_SYS_DDR_RAW_TIMING | |
49 | #endif | |
f749db3a YS |
50 | |
51 | #define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */ | |
52 | ||
f749db3a YS |
53 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL |
54 | #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 | |
55 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
56 | #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL | |
d9c68b14 YS |
57 | #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2 |
58 | ||
8bfa301b YS |
59 | /* |
60 | * SMP Definitinos | |
61 | */ | |
62 | #define CPU_RELEASE_ADDR secondary_boot_func | |
63 | ||
d9c68b14 YS |
64 | #define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS |
65 | #define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL | |
66 | /* | |
67 | * DDR controller use 0 as the base address for binding. | |
68 | * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access. | |
69 | */ | |
70 | #define CONFIG_SYS_DP_DDR_BASE_PHY 0 | |
71 | #define CONFIG_DP_DDR_CTRL 2 | |
72 | #define CONFIG_DP_DDR_NUM_CTRLS 1 | |
f749db3a YS |
73 | |
74 | /* Generic Timer Definitions */ | |
207774b2 YS |
75 | /* |
76 | * This is not an accurate number. It is used in start.S. The frequency | |
77 | * will be udpated later when get_bus_freq(0) is available. | |
78 | */ | |
79 | #define COUNTER_FREQUENCY 25000000 /* 25MHz */ | |
f749db3a YS |
80 | |
81 | /* Size of malloc() pool */ | |
aa66acbf | 82 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) |
f749db3a YS |
83 | |
84 | /* I2C */ | |
85 | #define CONFIG_CMD_I2C | |
86 | #define CONFIG_SYS_I2C | |
87 | #define CONFIG_SYS_I2C_MXC | |
f8cb101e YS |
88 | #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ |
89 | #define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */ | |
f749db3a YS |
90 | |
91 | /* Serial Port */ | |
92 | #define CONFIG_CONS_INDEX 2 | |
93 | #define CONFIG_SYS_NS16550 | |
94 | #define CONFIG_SYS_NS16550_SERIAL | |
95 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
96 | #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) | |
97 | ||
98 | #define CONFIG_BAUDRATE 115200 | |
99 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } | |
100 | ||
101 | /* IFC */ | |
102 | #define CONFIG_FSL_IFC | |
f3f8c564 | 103 | |
f749db3a YS |
104 | /* |
105 | * During booting, CS0 needs to be at the region of 0x30000000, i.e. the IFC | |
106 | * address 0. But this region is limited to 256MB. To accommodate bigger NOR | |
107 | * flash and other devices, we will map CS0 to 0x580000000 after relocation. | |
108 | * CONFIG_SYS_FLASH_BASE has the final address (core view) | |
109 | * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) | |
110 | * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address | |
111 | * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting | |
112 | */ | |
113 | #define CONFIG_SYS_FLASH_BASE 0x580000000ULL | |
114 | #define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000 | |
115 | #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 | |
116 | ||
e211c12e PK |
117 | #ifndef CONFIG_SYS_NO_FLASH |
118 | #define CONFIG_FLASH_CFI_DRIVER | |
119 | #define CONFIG_SYS_FLASH_CFI | |
120 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
121 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
e211c12e PK |
122 | #endif |
123 | ||
e211c12e PK |
124 | #define CONFIG_SYS_NAND_BASE 0x520000000 |
125 | #define CONFIG_SYS_NAND_BASE_PHYS 0x20000000 | |
126 | ||
422cb08a | 127 | /* Debug Server firmware */ |
422cb08a | 128 | #define CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024) |
422cb08a BS |
129 | /* 2 sec timeout */ |
130 | #define CONFIG_SYS_DEBUG_SERVER_TIMEOUT (2 * 1000 * 1000) | |
131 | ||
f749db3a YS |
132 | /* MC firmware */ |
133 | #define CONFIG_FSL_MC_ENET | |
134 | #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024) | |
f749db3a | 135 | /* TODO Actual DPL max length needs to be confirmed with the MC FW team */ |
f3f8c564 PK |
136 | #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH (256 * 1024) |
137 | #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0xe00000 | |
f749db3a | 138 | |
422cb08a BS |
139 | /* Carve out a DDR region which will not be used by u-boot/Linux */ |
140 | #if defined(CONFIG_FSL_MC_ENET) || defined(CONFIG_FSL_DEBUG_SERVER) | |
141 | #define CONFIG_SYS_MEM_TOP_HIDE get_dram_size_to_hide() | |
f749db3a YS |
142 | #endif |
143 | ||
f3f8c564 PK |
144 | /* PCIe */ |
145 | #define CONFIG_PCIE1 /* PCIE controler 1 */ | |
146 | #define CONFIG_PCIE2 /* PCIE controler 2 */ | |
147 | #define CONFIG_PCIE3 /* PCIE controler 3 */ | |
148 | #define CONFIG_PCIE4 /* PCIE controler 4 */ | |
149 | #define FSL_PCIE_COMPAT "fsl,20851a-pcie" | |
150 | ||
151 | #define CONFIG_SYS_PCI_64BIT | |
152 | ||
153 | #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 | |
154 | #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ | |
155 | #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 | |
156 | #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ | |
157 | ||
158 | #define CONFIG_SYS_PCIE_IO_BUS 0x00000000 | |
159 | #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 | |
160 | #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ | |
161 | ||
162 | #define CONFIG_SYS_PCIE_MEM_BUS 0x40000000 | |
163 | #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x40000000 | |
164 | #define CONFIG_SYS_PCIE_MEM_SIZE 0x40000000 /* 1G */ | |
165 | ||
f749db3a YS |
166 | /* Command line configuration */ |
167 | #define CONFIG_CMD_CACHE | |
168 | #define CONFIG_CMD_BDI | |
169 | #define CONFIG_CMD_DHCP | |
170 | #define CONFIG_CMD_ENV | |
171 | #define CONFIG_CMD_FLASH | |
172 | #define CONFIG_CMD_IMI | |
f3f8c564 | 173 | #define CONFIG_CMD_LOADB |
f749db3a YS |
174 | #define CONFIG_CMD_MEMORY |
175 | #define CONFIG_CMD_MII | |
176 | #define CONFIG_CMD_NET | |
177 | #define CONFIG_CMD_PING | |
178 | #define CONFIG_CMD_SAVEENV | |
179 | #define CONFIG_CMD_RUN | |
180 | #define CONFIG_CMD_BOOTD | |
181 | #define CONFIG_CMD_ECHO | |
182 | #define CONFIG_CMD_SOURCE | |
183 | #define CONFIG_CMD_FAT | |
184 | #define CONFIG_DOS_PARTITION | |
185 | ||
186 | /* Miscellaneous configurable options */ | |
187 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) | |
8bfa301b | 188 | #define CONFIG_ARCH_EARLY_INIT_R |
f749db3a YS |
189 | |
190 | /* Physical Memory Map */ | |
191 | /* fixme: these need to be checked against the board */ | |
192 | #define CONFIG_CHIP_SELECTS_PER_CTRL 4 | |
f749db3a | 193 | |
d9c68b14 | 194 | #define CONFIG_NR_DRAM_BANKS 3 |
f749db3a | 195 | |
f749db3a YS |
196 | #define CONFIG_HWCONFIG |
197 | #define HWCONFIG_BUFFER_SIZE 128 | |
198 | ||
199 | #define CONFIG_DISPLAY_CPUINFO | |
200 | ||
201 | /* Initial environment variables */ | |
202 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
203 | "hwconfig=fsl_ddr:bank_intlv=auto\0" \ | |
204 | "loadaddr=0x80100000\0" \ | |
205 | "kernel_addr=0x100000\0" \ | |
206 | "ramdisk_addr=0x800000\0" \ | |
207 | "ramdisk_size=0x2000000\0" \ | |
f3f8c564 | 208 | "fdt_high=0xa0000000\0" \ |
f749db3a YS |
209 | "initrd_high=0xffffffffffffffff\0" \ |
210 | "kernel_start=0x581200000\0" \ | |
052ddd5c | 211 | "kernel_load=0xa0000000\0" \ |
f749db3a YS |
212 | "kernel_size=0x1000000\0" \ |
213 | "console=ttyAMA0,38400n8\0" | |
214 | ||
40e61f8e AB |
215 | #define CONFIG_BOOTARGS "console=ttyS1,115200 root=/dev/ram0 " \ |
216 | "earlycon=uart8250,mmio,0x21c0600,115200 " \ | |
217 | "default_hugepagesz=2m hugepagesz=2m " \ | |
218 | "hugepages=16" | |
f749db3a YS |
219 | #define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ |
220 | "$kernel_size && bootm $kernel_load" | |
221 | #define CONFIG_BOOTDELAY 1 | |
222 | ||
f749db3a YS |
223 | /* Monitor Command Prompt */ |
224 | #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ | |
f3f8c564 | 225 | #define CONFIG_SYS_PROMPT "=> " |
f749db3a YS |
226 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ |
227 | sizeof(CONFIG_SYS_PROMPT) + 16) | |
228 | #define CONFIG_SYS_HUSH_PARSER | |
229 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
230 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ | |
231 | #define CONFIG_SYS_LONGHELP | |
232 | #define CONFIG_CMDLINE_EDITING 1 | |
f3f8c564 | 233 | #define CONFIG_AUTO_COMPLETE |
f749db3a YS |
234 | #define CONFIG_SYS_MAXARGS 64 /* max command args */ |
235 | ||
236 | #ifndef __ASSEMBLY__ | |
422cb08a | 237 | unsigned long get_dram_size_to_hide(void); |
f749db3a YS |
238 | #endif |
239 | ||
f3f8c564 PK |
240 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ |
241 | ||
f749db3a | 242 | #endif /* __LS2_COMMON_H */ |