[people/ms/u-boot.git] / include / configs / ls2085a_common.h

/*
 * Copyright (C) 2014 Freescale Semiconductor
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __LS2_COMMON_H
#define __LS2_COMMON_H

#define CONFIG_SYS_GENERIC_BOARD

#define CONFIG_REMAKE_ELF
#define CONFIG_FSL_LSCH3
#define CONFIG_LS2085A
#define CONFIG_GICV3
#define CONFIG_FSL_TZPC_BP147

/* Errata fixes */
#define CONFIG_ARM_ERRATA_828024
#define CONFIG_ARM_ERRATA_826974

#include <asm/arch-fsl-lsch3/config.h>
#if (defined(CONFIG_SYS_FSL_SRDS_1) || defined(CONFIG_SYS_FSL_SRDS_2))
#define	CONFIG_SYS_HAS_SERDES
#endif

/* We need architecture specific misc initializations */
#define CONFIG_ARCH_MISC_INIT

/* Link Definitions */
#define CONFIG_SYS_TEXT_BASE		0x30100000

#ifdef CONFIG_EMU
#define CONFIG_SYS_NO_FLASH
#endif

#define CONFIG_SUPPORT_RAW_INITRD

#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_BOARD_EARLY_INIT_F	1

/* Flat Device Tree Definitions */
#define CONFIG_OF_LIBFDT
#define CONFIG_OF_BOARD_SETUP

/* new uImage format support */
#define CONFIG_FIT
#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */

#define CONFIG_FSL_DDR_INTERACTIVE	/* Interactive debugging */
#ifndef CONFIG_SYS_FSL_DDR4
#define CONFIG_SYS_FSL_DDR3		/* Use DDR3 memory */
#define CONFIG_SYS_DDR_RAW_TIMING
#endif

#define CONFIG_SYS_FSL_DDR_INTLV_256B	/* force 256 byte interleaving */

#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000UL
#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY	0
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_DDR_BLOCK2_BASE	0x8080000000ULL
#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS	2

/*
 * SMP Definitinos
 */
#define CPU_RELEASE_ADDR		secondary_boot_func

#define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
#define CONFIG_SYS_DP_DDR_BASE		0x6000000000ULL
/*
 * DDR controller use 0 as the base address for binding.
 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
 */
#define CONFIG_SYS_DP_DDR_BASE_PHY	0
#define CONFIG_DP_DDR_CTRL		2
#define CONFIG_DP_DDR_NUM_CTRLS		1

/* Generic Timer Definitions */
/*
 * This is not an accurate number. It is used in start.S. The frequency
 * will be udpated later when get_bus_freq(0) is available.
 */
#define COUNTER_FREQUENCY		25000000	/* 25MHz */

/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2048 * 1024)

/* I2C */
#define CONFIG_CMD_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
#define CONFIG_SYS_I2C_MXC_I2C4		/* enable I2C bus 4 */

/* Serial Port */
#define CONFIG_CONS_INDEX       1
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE     1
#define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)

#define CONFIG_BAUDRATE			115200
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

/* IFC */
#define CONFIG_FSL_IFC

/*
 * During booting, IFC is mapped at the region of 0x30000000.
 * But this region is limited to 256MB. To accommodate NOR, promjet
 * and FPGA. This region is divided as below:
 * 0x30000000 - 0x37ffffff : 128MB : NOR flash
 * 0x38000000 - 0x3BFFFFFF : 64MB  : Promjet
 * 0x3C000000 - 0x40000000 : 64MB  : FPGA etc
 *
 * To accommodate bigger NOR flash and other devices, we will map IFC
 * chip selects to as below:
 * 0x5_1000_0000..0x5_1fff_ffff	Memory Hole
 * 0x5_2000_0000..0x5_3fff_ffff	IFC CSx (FPGA, NAND and others 512MB)
 * 0x5_4000_0000..0x5_7fff_ffff	ASIC or others 1GB
 * 0x5_8000_0000..0x5_bfff_ffff	IFC CS0 1GB (NOR/Promjet)
 * 0x5_C000_0000..0x5_ffff_ffff	IFC CS1 1GB (NOR/Promjet)
 *
 * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
 * CONFIG_SYS_FLASH_BASE has the final address (core view)
 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
 * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
 */

#define CONFIG_SYS_FLASH_BASE			0x580000000ULL
#define CONFIG_SYS_FLASH_BASE_PHYS		0x80000000
#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY	0x00000000

#define CONFIG_SYS_FLASH1_BASE_PHYS		0xC0000000
#define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY	0x8000000

#ifndef CONFIG_SYS_NO_FLASH
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_FLASH_QUIET_TEST
#endif

#ifndef __ASSEMBLY__
unsigned long long get_qixis_addr(void);
#endif
#define QIXIS_BASE				get_qixis_addr()
#define QIXIS_BASE_PHYS				0x20000000
#define QIXIS_BASE_PHYS_EARLY			0xC000000

#define CONFIG_SYS_NAND_BASE			0x530000000ULL
#define CONFIG_SYS_NAND_BASE_PHYS		0x30000000

/* Debug Server firmware */
#define CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE	(512UL * 1024 * 1024)
/* 2 sec timeout */
#define CONFIG_SYS_DEBUG_SERVER_TIMEOUT			(2 * 1000 * 1000)

/* MC firmware */
#define CONFIG_FSL_MC_ENET
#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE	(512UL * 1024 * 1024)
/* TODO Actual DPL max length needs to be confirmed with the MC FW team */
#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH	    0x20000
#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET    0x00F00000
#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH	    0x20000
#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET    0x00F20000

/* Carve out a DDR region which will not be used by u-boot/Linux */
#if defined(CONFIG_FSL_MC_ENET) || defined(CONFIG_FSL_DEBUG_SERVER)
#define CONFIG_SYS_MEM_TOP_HIDE		get_dram_size_to_hide()
#endif

/* PCIe */
#define CONFIG_PCIE1		/* PCIE controler 1 */
#define CONFIG_PCIE2		/* PCIE controler 2 */
#define CONFIG_PCIE3		/* PCIE controler 3 */
#define CONFIG_PCIE4		/* PCIE controler 4 */
#define FSL_PCIE_COMPAT "fsl,20851a-pcie"

#define CONFIG_SYS_PCI_64BIT

#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF	0x00000000
#define CONFIG_SYS_PCIE_CFG0_SIZE	0x00001000	/* 4k */
#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF	0x00001000
#define CONFIG_SYS_PCIE_CFG1_SIZE	0x00001000	/* 4k */

#define CONFIG_SYS_PCIE_IO_BUS		0x00000000
#define CONFIG_SYS_PCIE_IO_PHYS_OFF	0x00010000
#define CONFIG_SYS_PCIE_IO_SIZE		0x00010000	/* 64k */

#define CONFIG_SYS_PCIE_MEM_BUS		0x40000000
#define CONFIG_SYS_PCIE_MEM_PHYS_OFF	0x40000000
#define CONFIG_SYS_PCIE_MEM_SIZE	0x40000000	/* 1G */

/* Command line configuration */
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_BDI
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ENV
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_IMI
#define CONFIG_CMD_LOADB
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_RUN
#define CONFIG_CMD_BOOTD
#define CONFIG_CMD_ECHO
#define CONFIG_CMD_SOURCE
#define CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION

/* Miscellaneous configurable options */
#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
#define CONFIG_ARCH_EARLY_INIT_R

/* Physical Memory Map */
/* fixme: these need to be checked against the board */
#define CONFIG_CHIP_SELECTS_PER_CTRL	4

#define CONFIG_NR_DRAM_BANKS		3

#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE		128

#define CONFIG_DISPLAY_CPUINFO

/* Initial environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
	"loadaddr=0x80100000\0"			\
	"kernel_addr=0x100000\0"		\
	"ramdisk_addr=0x800000\0"		\
	"ramdisk_size=0x2000000\0"		\
	"fdt_high=0xa0000000\0"			\
	"initrd_high=0xffffffffffffffff\0"	\
	"kernel_start=0x581200000\0"		\
	"kernel_load=0xa0000000\0"		\
	"kernel_size=0x1000000\0"		\
	"console=ttyAMA0,38400n8\0"

#define CONFIG_BOOTARGS		"console=ttyS1,115200 root=/dev/ram0 " \
				"earlycon=uart8250,mmio,0x21c0600,115200 " \
				"default_hugepagesz=2m hugepagesz=2m " \
				"hugepages=16"
#define CONFIG_BOOTCOMMAND		"cp.b $kernel_start $kernel_load "     \
					"$kernel_size && bootm $kernel_load"
#define CONFIG_BOOTDELAY		10

/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
#define CONFIG_SYS_PROMPT		"=> "
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Boot args buffer */
#define CONFIG_SYS_LONGHELP
#define CONFIG_CMDLINE_EDITING		1
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_MAXARGS		64	/* max command args */

#ifndef __ASSEMBLY__
unsigned long get_dram_size_to_hide(void);
#endif

#define CONFIG_PANIC_HANG	/* do not reset board on panic */

#endif /* __LS2_COMMON_H */
Commit	Line	Data
f749db3a YS	1	/*
	2	* Copyright (C) 2014 Freescale Semiconductor
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#ifndef __LS2_COMMON_H
	8	#define __LS2_COMMON_H
	9
	10	#define CONFIG_SYS_GENERIC_BOARD
	11
	12	#define CONFIG_REMAKE_ELF
	13	#define CONFIG_FSL_LSCH3
	14	#define CONFIG_LS2085A
	15	#define CONFIG_GICV3
9c66ce66	16	#define CONFIG_FSL_TZPC_BP147
f749db3a	17
1b1069cd BS	18	/* Errata fixes */
	19	#define CONFIG_ARM_ERRATA_828024
	20	#define CONFIG_ARM_ERRATA_826974
	21
31d34c6c ML	22	#include <asm/arch-fsl-lsch3/config.h>
	23	#if (defined(CONFIG_SYS_FSL_SRDS_1) \|\| defined(CONFIG_SYS_FSL_SRDS_2))
	24	#define CONFIG_SYS_HAS_SERDES
	25	#endif
	26
422cb08a BS	27	/* We need architecture specific misc initializations */
	28	#define CONFIG_ARCH_MISC_INIT
	29
f749db3a	30	/* Link Definitions */
f3f8c564	31	#define CONFIG_SYS_TEXT_BASE 0x30100000
f749db3a	32
e211c12e	33	#ifdef CONFIG_EMU
f749db3a	34	#define CONFIG_SYS_NO_FLASH
e211c12e	35	#endif
f749db3a YS	36
	37	#define CONFIG_SUPPORT_RAW_INITRD
	38
	39	#define CONFIG_SKIP_LOWLEVEL_INIT
	40	#define CONFIG_BOARD_EARLY_INIT_F 1
	41
f749db3a YS	42	/* Flat Device Tree Definitions */
	43	#define CONFIG_OF_LIBFDT
	44	#define CONFIG_OF_BOARD_SETUP
	45
	46	/* new uImage format support */
	47	#define CONFIG_FIT
	48	#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
	49
	50	#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
	51	#ifndef CONFIG_SYS_FSL_DDR4
	52	#define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */
	53	#define CONFIG_SYS_DDR_RAW_TIMING
	54	#endif
f749db3a YS	55
	56	#define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */
	57
f749db3a YS	58	#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
	59	#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
	60	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
	61	#define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
d9c68b14 YS	62	#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2
d9c68b14 YS	63
8bfa301b YS	64	/*
	65	* SMP Definitinos
	66	*/
	67	#define CPU_RELEASE_ADDR secondary_boot_func
	68
d9c68b14 YS	69	#define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
	70	#define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL
	71	/*
	72	* DDR controller use 0 as the base address for binding.
	73	* It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
	74	*/
	75	#define CONFIG_SYS_DP_DDR_BASE_PHY 0
	76	#define CONFIG_DP_DDR_CTRL 2
	77	#define CONFIG_DP_DDR_NUM_CTRLS 1
f749db3a YS	78
f749db3a YS	79	/* Generic Timer Definitions */
207774b2 YS	80	/*
	81	* This is not an accurate number. It is used in start.S. The frequency
	82	* will be udpated later when get_bus_freq(0) is available.
	83	*/
	84	#define COUNTER_FREQUENCY 25000000 /* 25MHz */
f749db3a YS	85
f749db3a YS	86	/* Size of malloc() pool */
aa66acbf	87	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
f749db3a YS	88
	89	/* I2C */
	90	#define CONFIG_CMD_I2C
	91	#define CONFIG_SYS_I2C
	92	#define CONFIG_SYS_I2C_MXC
f8cb101e YS	93	#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
f8cb101e YS	94	#define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */
f749db3a YS	95
f749db3a YS	96	/* Serial Port */
7288c2c2	97	#define CONFIG_CONS_INDEX 1
f749db3a YS	98	#define CONFIG_SYS_NS16550
	99	#define CONFIG_SYS_NS16550_SERIAL
	100	#define CONFIG_SYS_NS16550_REG_SIZE 1
	101	#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
	102
	103	#define CONFIG_BAUDRATE 115200
	104	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
	105
	106	/* IFC */
	107	#define CONFIG_FSL_IFC
f3f8c564	108
f749db3a	109	/*
7288c2c2 YS	110	* During booting, IFC is mapped at the region of 0x30000000.
	111	* But this region is limited to 256MB. To accommodate NOR, promjet
	112	* and FPGA. This region is divided as below:
	113	* 0x30000000 - 0x37ffffff : 128MB : NOR flash
	114	* 0x38000000 - 0x3BFFFFFF : 64MB : Promjet
	115	* 0x3C000000 - 0x40000000 : 64MB : FPGA etc
	116	*
	117	* To accommodate bigger NOR flash and other devices, we will map IFC
	118	* chip selects to as below:
	119	* 0x5_1000_0000..0x5_1fff_ffff Memory Hole
	120	* 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB)
	121	* 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
	122	* 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
	123	* 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
	124	*
	125	* For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
f749db3a YS	126	* CONFIG_SYS_FLASH_BASE has the final address (core view)
	127	* CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
	128	* CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
	129	* CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
	130	*/
7288c2c2	131
f749db3a YS	132	#define CONFIG_SYS_FLASH_BASE 0x580000000ULL
	133	#define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000
	134	#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
	135
7288c2c2 YS	136	#define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000
	137	#define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000
	138
e211c12e PK	139	#ifndef CONFIG_SYS_NO_FLASH
	140	#define CONFIG_FLASH_CFI_DRIVER
	141	#define CONFIG_SYS_FLASH_CFI
	142	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
	143	#define CONFIG_SYS_FLASH_QUIET_TEST
e211c12e PK	144	#endif
e211c12e PK	145
7288c2c2 YS	146	#ifndef __ASSEMBLY__
	147	unsigned long long get_qixis_addr(void);
	148	#endif
	149	#define QIXIS_BASE get_qixis_addr()
	150	#define QIXIS_BASE_PHYS 0x20000000
	151	#define QIXIS_BASE_PHYS_EARLY 0xC000000
	152
	153	#define CONFIG_SYS_NAND_BASE 0x530000000ULL
	154	#define CONFIG_SYS_NAND_BASE_PHYS 0x30000000
e211c12e	155
422cb08a	156	/* Debug Server firmware */
422cb08a	157	#define CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024)
422cb08a BS	158	/* 2 sec timeout */
	159	#define CONFIG_SYS_DEBUG_SERVER_TIMEOUT (2 * 1000 * 1000)
	160
f749db3a YS	161	/* MC firmware */
	162	#define CONFIG_FSL_MC_ENET
	163	#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024)
f749db3a	164	/* TODO Actual DPL max length needs to be confirmed with the MC FW team */
125e2bc1 GR	165	#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
	166	#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
	167	#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
	168	#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
f749db3a	169
422cb08a BS	170	/* Carve out a DDR region which will not be used by u-boot/Linux */
	171	#if defined(CONFIG_FSL_MC_ENET) \|\| defined(CONFIG_FSL_DEBUG_SERVER)
	172	#define CONFIG_SYS_MEM_TOP_HIDE get_dram_size_to_hide()
f749db3a YS	173	#endif
f749db3a YS	174
f3f8c564 PK	175	/* PCIe */
	176	#define CONFIG_PCIE1 /* PCIE controler 1 */
	177	#define CONFIG_PCIE2 /* PCIE controler 2 */
	178	#define CONFIG_PCIE3 /* PCIE controler 3 */
	179	#define CONFIG_PCIE4 /* PCIE controler 4 */
	180	#define FSL_PCIE_COMPAT "fsl,20851a-pcie"
	181
	182	#define CONFIG_SYS_PCI_64BIT
	183
	184	#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
	185	#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
	186	#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
	187	#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
	188
	189	#define CONFIG_SYS_PCIE_IO_BUS 0x00000000
	190	#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
	191	#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
	192
	193	#define CONFIG_SYS_PCIE_MEM_BUS 0x40000000
	194	#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x40000000
	195	#define CONFIG_SYS_PCIE_MEM_SIZE 0x40000000 /* 1G */
	196
f749db3a YS	197	/* Command line configuration */
	198	#define CONFIG_CMD_CACHE
	199	#define CONFIG_CMD_BDI
	200	#define CONFIG_CMD_DHCP
	201	#define CONFIG_CMD_ENV
	202	#define CONFIG_CMD_FLASH
	203	#define CONFIG_CMD_IMI
f3f8c564	204	#define CONFIG_CMD_LOADB
f749db3a YS	205	#define CONFIG_CMD_MEMORY
	206	#define CONFIG_CMD_MII
	207	#define CONFIG_CMD_NET
	208	#define CONFIG_CMD_PING
	209	#define CONFIG_CMD_SAVEENV
	210	#define CONFIG_CMD_RUN
	211	#define CONFIG_CMD_BOOTD
	212	#define CONFIG_CMD_ECHO
	213	#define CONFIG_CMD_SOURCE
	214	#define CONFIG_CMD_FAT
	215	#define CONFIG_DOS_PARTITION
	216
	217	/* Miscellaneous configurable options */
	218	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
8bfa301b	219	#define CONFIG_ARCH_EARLY_INIT_R
f749db3a YS	220
	221	/* Physical Memory Map */
	222	/* fixme: these need to be checked against the board */
	223	#define CONFIG_CHIP_SELECTS_PER_CTRL 4
f749db3a	224
d9c68b14	225	#define CONFIG_NR_DRAM_BANKS 3
f749db3a	226
f749db3a YS	227	#define CONFIG_HWCONFIG
	228	#define HWCONFIG_BUFFER_SIZE 128
	229
	230	#define CONFIG_DISPLAY_CPUINFO
	231
	232	/* Initial environment variables */
	233	#define CONFIG_EXTRA_ENV_SETTINGS \
	234	"hwconfig=fsl_ddr:bank_intlv=auto\0" \
	235	"loadaddr=0x80100000\0" \
	236	"kernel_addr=0x100000\0" \
	237	"ramdisk_addr=0x800000\0" \
	238	"ramdisk_size=0x2000000\0" \
f3f8c564	239	"fdt_high=0xa0000000\0" \
f749db3a YS	240	"initrd_high=0xffffffffffffffff\0" \
f749db3a YS	241	"kernel_start=0x581200000\0" \
052ddd5c	242	"kernel_load=0xa0000000\0" \
f749db3a YS	243	"kernel_size=0x1000000\0" \
	244	"console=ttyAMA0,38400n8\0"
	245
40e61f8e AB	246	#define CONFIG_BOOTARGS "console=ttyS1,115200 root=/dev/ram0 " \
	247	"earlycon=uart8250,mmio,0x21c0600,115200 " \
	248	"default_hugepagesz=2m hugepagesz=2m " \
	249	"hugepages=16"
f749db3a YS	250	#define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \
f749db3a YS	251	"$kernel_size && bootm $kernel_load"
7288c2c2	252	#define CONFIG_BOOTDELAY 10
f749db3a	253
f749db3a YS	254	/* Monitor Command Prompt */
f749db3a YS	255	#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
f3f8c564	256	#define CONFIG_SYS_PROMPT "=> "
f749db3a YS	257	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	258	sizeof(CONFIG_SYS_PROMPT) + 16)
	259	#define CONFIG_SYS_HUSH_PARSER
	260	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
	261	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
	262	#define CONFIG_SYS_LONGHELP
	263	#define CONFIG_CMDLINE_EDITING 1
f3f8c564	264	#define CONFIG_AUTO_COMPLETE
f749db3a YS	265	#define CONFIG_SYS_MAXARGS 64 /* max command args */
	266
	267	#ifndef __ASSEMBLY__
422cb08a	268	unsigned long get_dram_size_to_hide(void);
f749db3a YS	269	#endif
f749db3a YS	270
f3f8c564 PK	271	#define CONFIG_PANIC_HANG /* do not reset board on panic */
f3f8c564 PK	272
f749db3a	273	#endif /* __LS2_COMMON_H */