projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| e2b65ea9 YS |
1 | /* |
| 2 | * Copyright 2015 Freescale Semiconductor | |
| 3 | * | |
| 4 | * SPDX-License-Identifier: GPL-2.0+ | |
| 5 | */ | |
| 6 | ||
| 7 | #ifndef __LS2_RDB_H | |
| 8 | #define __LS2_RDB_H | |
| 9 | ||
| 10 | #include "ls2085a_common.h" | |
| e2b65ea9 YS |
11 | |
| 12 | #undef CONFIG_CONS_INDEX | |
| 13 | #define CONFIG_CONS_INDEX 2 | |
| 14 | ||
| 15 | #define CONFIG_DISPLAY_BOARDINFO | |
| 16 | ||
| 17 | #ifndef __ASSEMBLY__ | |
| 18 | unsigned long get_board_sys_clk(void); | |
| 19 | #endif | |
| 20 | ||
| 21 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() | |
| 22 | #define CONFIG_DDR_CLK_FREQ 133333333 | |
| 23 | #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) | |
| 24 | ||
| 25 | #define CONFIG_DDR_SPD | |
| 26 | #define CONFIG_DDR_ECC | |
| 27 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER | |
| 28 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef | |
| 29 | #define SPD_EEPROM_ADDRESS1 0x51 | |
| 30 | #define SPD_EEPROM_ADDRESS2 0x52 | |
| fc7b3855 YS |
31 | #define SPD_EEPROM_ADDRESS3 0x53 |
| 32 | #define SPD_EEPROM_ADDRESS4 0x54 | |
| e2b65ea9 YS |
33 | #define SPD_EEPROM_ADDRESS5 0x55 |
| 34 | #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */ | |
| 35 | #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 | |
| 36 | #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ | |
| 37 | #define CONFIG_DIMM_SLOTS_PER_CTLR 2 | |
| 38 | #define CONFIG_CHIP_SELECTS_PER_CTRL 4 | |
| 39 | #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 | |
| 40 | #define CONFIG_FSL_DDR_BIST /* enable built-in memory test */ | |
| 41 | ||
| 42 | /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */ | |
| 43 | ||
| 44 | #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) | |
| 45 | #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) | |
| 46 | #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) | |
| 47 | ||
| 48 | #define CONFIG_SYS_NOR0_CSPR \ | |
| 49 | (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ | |
| 50 | CSPR_PORT_SIZE_16 | \ | |
| 51 | CSPR_MSEL_NOR | \ | |
| 52 | CSPR_V) | |
| 53 | #define CONFIG_SYS_NOR0_CSPR_EARLY \ | |
| 54 | (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ | |
| 55 | CSPR_PORT_SIZE_16 | \ | |
| 56 | CSPR_MSEL_NOR | \ | |
| 57 | CSPR_V) | |
| 58 | #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) | |
| 59 | #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ | |
| 60 | FTIM0_NOR_TEADC(0x5) | \ | |
| 61 | FTIM0_NOR_TEAHC(0x5)) | |
| 62 | #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ | |
| 63 | FTIM1_NOR_TRAD_NOR(0x1a) |\ | |
| 64 | FTIM1_NOR_TSEQRAD_NOR(0x13)) | |
| 65 | #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ | |
| 66 | FTIM2_NOR_TCH(0x4) | \ | |
| 67 | FTIM2_NOR_TWPH(0x0E) | \ | |
| 68 | FTIM2_NOR_TWP(0x1c)) | |
| 69 | #define CONFIG_SYS_NOR_FTIM3 0x04000000 | |
| 70 | #define CONFIG_SYS_IFC_CCR 0x01000000 | |
| 71 | ||
| 72 | #ifndef CONFIG_SYS_NO_FLASH | |
| 73 | #define CONFIG_FLASH_CFI_DRIVER | |
| 74 | #define CONFIG_SYS_FLASH_CFI | |
| 75 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
| 76 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
| 77 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
| 78 | ||
| 79 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
| 80 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
| 81 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
| 82 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
| 83 | ||
| 84 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
| 85 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ | |
| 86 | CONFIG_SYS_FLASH_BASE + 0x40000000} | |
| 87 | #endif | |
| 88 | ||
| 89 | #define CONFIG_NAND_FSL_IFC | |
| 90 | #define CONFIG_SYS_NAND_MAX_ECCPOS 256 | |
| 91 | #define CONFIG_SYS_NAND_MAX_OOBFREE 2 | |
| 92 | ||
| 93 | ||
| 94 | #define CONFIG_SYS_NAND_CSPR_EXT (0x0) | |
| 95 | #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | |
| 96 | | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ | |
| 97 | | CSPR_MSEL_NAND /* MSEL = NAND */ \ | |
| 98 | | CSPR_V) | |
| 99 | #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) | |
| 100 | ||
| 101 | #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | |
| 102 | | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | |
| 103 | | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | |
| 104 | | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ | |
| 105 | | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ | |
| 106 | | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ | |
| 107 | | CSOR_NAND_PB(128)) /* Pages Per Block 128*/ | |
| 108 | ||
| 109 | #define CONFIG_SYS_NAND_ONFI_DETECTION | |
| 110 | ||
| 111 | /* ONFI NAND Flash mode0 Timing Params */ | |
| 112 | #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x0e) | \ | |
| 113 | FTIM0_NAND_TWP(0x30) | \ | |
| 114 | FTIM0_NAND_TWCHT(0x0e) | \ | |
| 115 | FTIM0_NAND_TWH(0x14)) | |
| 116 | #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x64) | \ | |
| 117 | FTIM1_NAND_TWBE(0xab) | \ | |
| 118 | FTIM1_NAND_TRR(0x1c) | \ | |
| 119 | FTIM1_NAND_TRP(0x30)) | |
| 120 | #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x1e) | \ | |
| 121 | FTIM2_NAND_TREH(0x14) | \ | |
| 122 | FTIM2_NAND_TWHRE(0x3c)) | |
| 123 | #define CONFIG_SYS_NAND_FTIM3 0x0 | |
| 124 | ||
| 125 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } | |
| 126 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
| 127 | #define CONFIG_MTD_NAND_VERIFY_WRITE | |
| 128 | #define CONFIG_CMD_NAND | |
| 129 | ||
| 130 | #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) | |
| 131 | ||
| 132 | #define CONFIG_FSL_QIXIS /* use common QIXIS code */ | |
| 133 | #define QIXIS_LBMAP_SWITCH 0x06 | |
| 134 | #define QIXIS_LBMAP_MASK 0x0f | |
| 135 | #define QIXIS_LBMAP_SHIFT 0 | |
| 136 | #define QIXIS_LBMAP_DFLTBANK 0x00 | |
| 137 | #define QIXIS_LBMAP_ALTBANK 0x04 | |
| 32eda7cc | 138 | #define QIXIS_LBMAP_NAND 0x09 |
| e2b65ea9 YS |
139 | #define QIXIS_RST_CTL_RESET 0x31 |
| 140 | #define QIXIS_RST_CTL_RESET_EN 0x30 | |
| 141 | #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 | |
| 142 | #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 | |
| 143 | #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 | |
| 32eda7cc | 144 | #define QIXIS_RCW_SRC_NAND 0x119 |
| e2b65ea9 YS |
145 | #define QIXIS_RST_FORCE_MEM 0x01 |
| 146 | ||
| 147 | #define CONFIG_SYS_CSPR3_EXT (0x0) | |
| 148 | #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ | |
| 149 | | CSPR_PORT_SIZE_8 \ | |
| 150 | | CSPR_MSEL_GPCM \ | |
| 151 | | CSPR_V) | |
| 152 | #define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ | |
| 153 | | CSPR_PORT_SIZE_8 \ | |
| 154 | | CSPR_MSEL_GPCM \ | |
| 155 | | CSPR_V) | |
| 156 | ||
| 157 | #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) | |
| 158 | #define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12) | |
| 159 | /* QIXIS Timing parameters for IFC CS3 */ | |
| 160 | #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ | |
| 161 | FTIM0_GPCM_TEADC(0x0e) | \ | |
| 162 | FTIM0_GPCM_TEAHC(0x0e)) | |
| 163 | #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ | |
| 164 | FTIM1_GPCM_TRAD(0x3f)) | |
| 165 | #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ | |
| 166 | FTIM2_GPCM_TCH(0xf) | \ | |
| 167 | FTIM2_GPCM_TWP(0x3E)) | |
| 168 | #define CONFIG_SYS_CS3_FTIM3 0x0 | |
| 169 | ||
| 32eda7cc SW |
170 | #if defined(CONFIG_SPL) && defined(CONFIG_NAND) |
| 171 | #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT | |
| 172 | #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR_EARLY | |
| 173 | #define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR0_CSPR | |
| 174 | #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK | |
| 175 | #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR | |
| 176 | #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
| 177 | #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
| 178 | #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
| 179 | #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
| 180 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT | |
| 181 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR | |
| 182 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK | |
| 183 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR | |
| 184 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
| 185 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
| 186 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
| 187 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
| 188 | ||
| 189 | #define CONFIG_ENV_IS_IN_NAND | |
| 190 | #define CONFIG_ENV_OFFSET (2048 * 1024) | |
| 191 | #define CONFIG_ENV_SECT_SIZE 0x20000 | |
| 192 | #define CONFIG_ENV_SIZE 0x2000 | |
| 193 | #define CONFIG_SPL_PAD_TO 0x80000 | |
| 194 | #define CONFIG_SYS_NAND_U_BOOT_OFFS (1024 * 1024) | |
| 195 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024) | |
| 196 | #else | |
| e2b65ea9 YS |
197 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT |
| 198 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY | |
| 199 | #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR | |
| 200 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK | |
| 201 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR | |
| 202 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
| 203 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
| 204 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
| 205 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
| 206 | #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT | |
| 207 | #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR | |
| 208 | #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK | |
| 209 | #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR | |
| 210 | #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
| 211 | #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
| 212 | #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
| 213 | #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
| 214 | ||
| 32eda7cc SW |
215 | #define CONFIG_ENV_IS_IN_FLASH |
| 216 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000) | |
| 217 | #define CONFIG_ENV_SECT_SIZE 0x20000 | |
| 218 | #define CONFIG_ENV_SIZE 0x2000 | |
| 219 | #endif | |
| 220 | ||
| e2b65ea9 YS |
221 | /* Debug Server firmware */ |
| 222 | #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR | |
| 223 | #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL | |
| 224 | ||
| 225 | /* MC firmware */ | |
| 226 | #define CONFIG_SYS_LS_MC_FW_IN_NOR | |
| 227 | #define CONFIG_SYS_LS_MC_FW_ADDR 0x580300000ULL | |
| 228 | ||
| 229 | #define CONFIG_SYS_LS_MC_DPL_IN_NOR | |
| 230 | #define CONFIG_SYS_LS_MC_DPL_ADDR 0x580700000ULL | |
| 231 | ||
| 232 | #define CONFIG_SYS_LS_MC_DPC_IN_NOR | |
| 233 | #define CONFIG_SYS_LS_MC_DPC_ADDR 0x580800000ULL | |
| 234 | ||
| 235 | #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 | |
| c1000c12 GR |
236 | #define CONFIG_SYS_LS_MC_AIOP_IMG_IN_NOR |
| 237 | #define CONFIG_SYS_LS_MC_AIOP_IMG_ADDR 0x580900000ULL | |
| e2b65ea9 YS |
238 | |
| 239 | /* | |
| 240 | * I2C | |
| 241 | */ | |
| 4012350d PK |
242 | #define I2C_MUX_PCA_ADDR 0x75 |
| 243 | #define I2C_MUX_PCA_ADDR_PRI 0x75 /* Primary Mux*/ | |
| e2b65ea9 YS |
244 | |
| 245 | /* I2C bus multiplexer */ | |
| 246 | #define I2C_MUX_CH_DEFAULT 0x8 | |
| 247 | ||
| 0c42a8de HW |
248 | /* SPI */ |
| 249 | #ifdef CONFIG_FSL_DSPI | |
| 250 | #define CONFIG_CMD_SF | |
| 251 | #define CONFIG_SPI_FLASH | |
| 252 | #define CONFIG_SPI_FLASH_STMICRO | |
| 253 | #define CONFIG_SPI_FLASH_BAR | |
| 254 | #endif | |
| 255 | ||
| e2b65ea9 YS |
256 | /* |
| 257 | * RTC configuration | |
| 258 | */ | |
| 259 | #define RTC | |
| 260 | #define CONFIG_RTC_DS3231 1 | |
| 261 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 | |
| 6581440c | 262 | #define CONFIG_CMD_DATE |
| e2b65ea9 YS |
263 | |
| 264 | /* EEPROM */ | |
| 265 | #define CONFIG_ID_EEPROM | |
| 266 | #define CONFIG_CMD_EEPROM | |
| 267 | #define CONFIG_SYS_I2C_EEPROM_NXID | |
| 268 | #define CONFIG_SYS_EEPROM_BUS_NUM 0 | |
| 269 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 | |
| 270 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
| 271 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
| 272 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 | |
| 273 | ||
| e2b65ea9 YS |
274 | #define CONFIG_FSL_MEMAC |
| 275 | #define CONFIG_PCI /* Enable PCIE */ | |
| 276 | #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ | |
| 277 | ||
| 278 | #ifdef CONFIG_PCI | |
| e2b65ea9 | 279 | #define CONFIG_PCI_PNP |
| e2b65ea9 YS |
280 | #define CONFIG_PCI_SCAN_SHOW |
| 281 | #define CONFIG_CMD_PCI | |
| e2b65ea9 YS |
282 | #endif |
| 283 | ||
| 8b06460e YL |
284 | /* MMC */ |
| 285 | #define CONFIG_MMC | |
| 286 | #ifdef CONFIG_MMC | |
| 287 | #define CONFIG_CMD_MMC | |
| 288 | #define CONFIG_FSL_ESDHC | |
| 289 | #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 | |
| 290 | #define CONFIG_GENERIC_MMC | |
| 291 | #define CONFIG_CMD_FAT | |
| 292 | #define CONFIG_DOS_PARTITION | |
| 293 | #endif | |
| e2b65ea9 | 294 | |
| 5a4d744c YL |
295 | #define CONFIG_MISC_INIT_R |
| 296 | ||
| e16b604e NB |
297 | /* |
| 298 | * USB | |
| 299 | */ | |
| 300 | #define CONFIG_HAS_FSL_XHCI_USB | |
| 301 | #define CONFIG_USB_XHCI | |
| 302 | #define CONFIG_USB_XHCI_FSL | |
| 303 | #define CONFIG_USB_XHCI_DWC3 | |
| 304 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 | |
| 305 | #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 | |
| 306 | #define CONFIG_CMD_USB | |
| 307 | #define CONFIG_USB_STORAGE | |
| 308 | #define CONFIG_CMD_EXT2 | |
| 309 | ||
| e2b65ea9 YS |
310 | /* Initial environment variables */ |
| 311 | #undef CONFIG_EXTRA_ENV_SETTINGS | |
| 312 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 313 | "hwconfig=fsl_ddr:bank_intlv=auto\0" \ | |
| 314 | "loadaddr=0x80100000\0" \ | |
| 315 | "kernel_addr=0x100000\0" \ | |
| 316 | "ramdisk_addr=0x800000\0" \ | |
| 317 | "ramdisk_size=0x2000000\0" \ | |
| 318 | "fdt_high=0xa0000000\0" \ | |
| 319 | "initrd_high=0xffffffffffffffff\0" \ | |
| 320 | "kernel_start=0x581100000\0" \ | |
| 321 | "kernel_load=0xa0000000\0" \ | |
| 97421bd2 | 322 | "kernel_size=0x2800000\0" |
| e2b65ea9 | 323 | |
| 3484d953 PK |
324 | /* MAC/PHY configuration */ |
| 325 | #ifdef CONFIG_FSL_MC_ENET | |
| 326 | #define CONFIG_PHYLIB_10G | |
| 327 | #define CONFIG_PHY_CORTINA | |
| 328 | #define CONFIG_PHYLIB | |
| 329 | #define CONFIG_SYS_CORTINA_FW_IN_NOR | |
| 330 | #define CONFIG_CORTINA_FW_ADDR 0x581000000 | |
| 331 | #define CONFIG_CORTINA_FW_LENGTH 0x40000 | |
| 332 | ||
| 333 | #define CORTINA_PHY_ADDR1 0x10 | |
| 334 | #define CORTINA_PHY_ADDR2 0x11 | |
| 335 | #define CORTINA_PHY_ADDR3 0x12 | |
| 336 | #define CORTINA_PHY_ADDR4 0x13 | |
| 337 | #define AQ_PHY_ADDR1 0x00 | |
| 338 | #define AQ_PHY_ADDR2 0x01 | |
| 339 | #define AQ_PHY_ADDR3 0x02 | |
| 340 | #define AQ_PHY_ADDR4 0x03 | |
| 341 | ||
| 342 | #define CONFIG_MII | |
| 343 | #define CONFIG_ETHPRIME "DPNI1" | |
| 344 | #define CONFIG_PHY_GIGE | |
| 95279315 | 345 | #define CONFIG_PHY_AQUANTIA |
| 3484d953 PK |
346 | #endif |
| 347 | ||
| e2b65ea9 | 348 | #endif /* __LS2_RDB_H */ |