[people/ms/u-boot.git] / include / configs / luan.h

/*
 * (C) Copyright 2005
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 * John Otken, jotken@softadvances.com
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/************************************************************************
 * luan.h - configuration for LUAN board
 ***********************************************************************/
#ifndef __CONFIG_H
#define __CONFIG_H

/*-----------------------------------------------------------------------
 * High Level Configuration Options
 *----------------------------------------------------------------------*/
#define CONFIG_LUAN		1	/* Board is Luan		*/
#define CONFIG_440SP		1	/* Specific PPC440SP support    */
#define CONFIG_4xx		1	/* PPC4xx family	        */
#define CONFIG_440		1
#define CONFIG_SYS_CLK_FREQ	33333333 /* external freq to pll	*/

#define CONFIG_BOARD_EARLY_INIT_F 1     /* call board_early_init_f()	*/
#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/

/*-----------------------------------------------------------------------
 * Base addresses -- Note these are effective addresses where the
 * actual resources get mapped (not physical addresses)
 *----------------------------------------------------------------------*/
#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor */
#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc  */
#define CFG_MONITOR_BASE	(-CFG_MONITOR_LEN)
#define CFG_SDRAM_BASE	        0x00000000	/* MUST be zero */

#define CFG_LARGE_FLASH		0xffc00000	/* 4MB flash address CS0 */
#define CFG_SMALL_FLASH		0xff900000	/* 1MB flash address CS2 */
#define CFG_SRAM_BASE		0xff800000	/* 1MB SRAM  address CS2 */
#define CFG_EPLD_BASE		0xff000000	/* EPLD and FRAM     CS1 */

#define CFG_ISRAM_BASE	        0xf8000000	/* internal 8k SRAM (L2 cache) */

#define CFG_PERIPHERAL_BASE     0xf0000000	/* internal peripherals */

#define CFG_PCI_MEMBASE		0x80000000	/* mapped pci memory */
#define CFG_PCI_BASE		0xd0000000	/* internal PCI regs */
#define CFG_PCI_TARGBASE	0x80000000	/* PCIaddr mapped to CFG_PCI_MEMBASE */

#if CFG_LARGE_FLASH == 0xffc00000
#define CFG_FLASH_BASE		CFG_LARGE_FLASH
#else
#define CFG_FLASH_BASE		CFG_SMALL_FLASH
#endif

#undef CFG_DRAM_TEST
#if CFG_SRAM_BASE
#define CFG_KBYTES_SDRAM	1024*2
#else
#define CFG_KBYTES_SDRAM	1024
#endif

/*-----------------------------------------------------------------------
 * Initial RAM & stack pointer (placed in SDRAM)
 *----------------------------------------------------------------------*/
#define CFG_INIT_RAM_ADDR	CFG_ISRAM_BASE
#define CFG_INIT_RAM_END	(8 << 10)
#define CFG_GBL_DATA_SIZE	256		/* num bytes initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Serial Port
 *----------------------------------------------------------------------*/
#define CFG_EXT_SERIAL_CLOCK	11059200 /* external 11.059MHz clk */
#define CONFIG_BAUDRATE		115200
#undef  CONFIG_SERIAL_MULTI
#undef  CONFIG_UART1_CONSOLE		/* define if you want console on UART1 */

#define CFG_BAUDRATE_TABLE  \
    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}

/*-----------------------------------------------------------------------
 * Environment
 *----------------------------------------------------------------------*/
/*
 * Define here the location of the environment variables (FLASH or EEPROM).
 * Note: DENX encourages to use redundant environment in FLASH.
 */
#define CFG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/

/*-----------------------------------------------------------------------
 * FLASH related
 *----------------------------------------------------------------------*/
#define CFG_MAX_FLASH_BANKS	3	/* max number of memory banks		*/
#define CFG_MAX_FLASH_SECT	64	/* max number of sectors on one chip	*/

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */

#define CFG_FLASH_ADDR0         0x555
#define CFG_FLASH_ADDR1         0x2aa
#define CFG_FLASH_WORD_SIZE     unsigned char

#ifdef CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE	0x10000 /* size of one complete sector	*/
#define CFG_ENV_ADDR		(CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/

/* Address and size of Redundant Environment Sector	*/
#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
#endif /* CFG_ENV_IS_IN_FLASH */

/*-----------------------------------------------------------------------
 * DDR SDRAM
 *----------------------------------------------------------------------*/
#undef  CONFIG_SPD_EEPROM		/* SPD EEPROM init doesn't support DDR2 */
#define SPD_EEPROM_ADDRESS {0x52,0x53}	/* I2C SPD addresses */
#define IIC0_DIMM0_ADDR         0x52
#define IIC0_DIMM1_ADDR         0x53

/*-----------------------------------------------------------------------
 * I2C
 *----------------------------------------------------------------------*/
#define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
#undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
#define CFG_I2C_SLAVE		0x7F

#define CONFIG_PREBOOT	"echo;"	\
	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"hostname=luan\0"						\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=$(serverip):$(rootpath)\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs $(bootargs) "				\
		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"	\
		":$(hostname):$(netdev):off panic=1\0"			\
	"addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\
	"flash_nfs=run nfsargs addip addtty;"				\
		"bootm $(kernel_addr)\0"				\
	"flash_self=run ramargs addip addtty;"				\
		"bootm $(kernel_addr) $(ramdisk_addr)\0"		\
	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;"     \
	        "bootm\0"						\
	"rootpath=/opt/eldk/ppc_4xx\0"					\
	"bootfile=/tftpboot/luan/uImage\0"				\
	"kernel_addr=fc000000\0"					\
	"ramdisk_addr=fc100000\0"					\
	"load=tftp 100000 /tftpboot/luan/u-boot.bin\0"			\
	"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;"	\
		"cp.b 100000 fffc0000 40000;"			        \
		"setenv filesize;saveenv\0"				\
	"upd=run load;run update\0"					\
	""
#define CONFIG_BOOTCOMMAND	"run flash_self"

#if 0
#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
#else
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
#endif

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/

#define CONFIG_MII		1	/* MII PHY management		*/
#define CONFIG_PHY_ADDR		1
#define CONFIG_CIS8201_PHY	1	/* Enable 'special' RGMII mode for Cicada phy */
#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */

#define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */

#define CONFIG_NETCONSOLE		/* include NetConsole support	*/
#define CONFIG_NET_MULTI		/* needed for NetConsole	*/

/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION

#ifdef DEBUG
#define CONFIG_PANIC_HANG
#else
#define CONFIG_HW_WATCHDOG			/* watchdog */
#endif

#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL		|	\
				CFG_CMD_ASKENV		|	\
			        CFG_CMD_CACHE		|	\
				CFG_CMD_DHCP		|	\
				CFG_CMD_DIAG		|	\
				CFG_CMD_ELF		|	\
				CFG_CMD_I2C		|	\
				CFG_CMD_IRQ		|	\
				CFG_CMD_MII		|	\
				CFG_CMD_NET		|	\
				CFG_CMD_NFS		|	\
				CFG_CMD_PCI		|	\
				CFG_CMD_PING		|	\
				CFG_CMD_REGINFO		|	\
				CFG_CMD_SETGETDCR	|	\
				CFG_CMD_SDRAM		|	\
				0)

/* this must be included AFTER the definition of CONFIG_COMMANDS */
#include <cmd_confdefs.h>

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory		*/
#define CFG_PROMPT	        "=> "	/* Monitor Command Prompt	*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE	        1024	/* Console I/O Buffer Size	*/
#else
#define CFG_CBSIZE	        256	/* Console I/O Buffer Size	*/
#endif
#define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS	        16	/* max number of command args	*/
#define CFG_BARGSIZE	        CFG_CBSIZE /* Boot Argument Buffer Size	*/

#define CFG_MEMTEST_START	0x0400000 /* memtest works on	        */
#define CFG_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/

#define CFG_LOAD_ADDR		0x100000 /* default load address */
#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
#undef  CONFIG_LYNXKDI			/* support kdi files            */

#define CFG_HZ		        1000	/* decrementer freq: 1 ms ticks */

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
#if (CONFIG_COMMANDS & CFG_CMD_PCI)

/* General PCI */
#define CONFIG_PCI			/* include pci support	        */
#define CONFIG_PCI_PNP			/* do (not) pci plug-and-play   */
#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */

/* Board-specific PCI */
#define CFG_PCI_PRE_INIT                /* enable board pci_pre_init()  */
#define CFG_PCI_TARGET_INIT
#undef  CFG_PCI_MASTER_INIT

#define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
#define CFG_PCI_SUBSYS_DEVICEID 0x4403	/* whatever */

#endif /* CONFIG_COMMANDS & CFG_CMD_PCI */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_DCACHE_SIZE		(32<<10) /* For AMCC 440 CPUs			*/
#define CFG_CACHELINE_SIZE	32	/* ...			*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
#endif

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/

#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
#endif

#endif	/* __CONFIG_H */
Commit	Line	Data
6e7fb6ea SR	1	/*
	2	* (C) Copyright 2005
	3	* Stefan Roese, DENX Software Engineering, sr@denx.de.
	4	* John Otken, jotken@softadvances.com
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	/************************************************************************
	26	* luan.h - configuration for LUAN board
	27	***********************************************************************/
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
	31	/*-----------------------------------------------------------------------
	32	* High Level Configuration Options
	33	----------------------------------------------------------------------/
	34	#define CONFIG_LUAN 1 /* Board is Luan */
	35	#define CONFIG_440SP 1 /* Specific PPC440SP support */
	36	#define CONFIG_4xx 1 /* PPC4xx family */
	37	#define CONFIG_440 1
	38	#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
	39
	40	#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
	41	#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
	42
	43	/*-----------------------------------------------------------------------
	44	* Base addresses -- Note these are effective addresses where the
	45	* actual resources get mapped (not physical addresses)
	46	----------------------------------------------------------------------/
	47	#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
	48	#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc */
	49	#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN)
	50	#define CFG_SDRAM_BASE 0x00000000 /* MUST be zero */
	51
	52	#define CFG_LARGE_FLASH 0xffc00000 /* 4MB flash address CS0 */
	53	#define CFG_SMALL_FLASH 0xff900000 /* 1MB flash address CS2 */
	54	#define CFG_SRAM_BASE 0xff800000 /* 1MB SRAM address CS2 */
	55	#define CFG_EPLD_BASE 0xff000000 /* EPLD and FRAM CS1 */
	56
	57	#define CFG_ISRAM_BASE 0xf8000000 /* internal 8k SRAM (L2 cache) */
	58
	59	#define CFG_PERIPHERAL_BASE 0xf0000000 /* internal peripherals */
	60
	61	#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
	62	#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
	63	#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
	64
65	#if CFG_LARGE_FLASH == 0xffc00000
66	#define CFG_FLASH_BASE CFG_LARGE_FLASH
67	#else
68	#define CFG_FLASH_BASE CFG_SMALL_FLASH
69	#endif
70
71	#undef CFG_DRAM_TEST
72	#if CFG_SRAM_BASE
73	#define CFG_KBYTES_SDRAM 1024*2
74	#else
75	#define CFG_KBYTES_SDRAM 1024
76	#endif
77
78	/*-----------------------------------------------------------------------
79	* Initial RAM & stack pointer (placed in SDRAM)
80	----------------------------------------------------------------------/
81	#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE
82	#define CFG_INIT_RAM_END (8 << 10)
83	#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
84	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
85	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
86
87	/*-----------------------------------------------------------------------
88	* Serial Port
89	----------------------------------------------------------------------/
90	#define CFG_EXT_SERIAL_CLOCK 11059200 /* external 11.059MHz clk */
91	#define CONFIG_BAUDRATE 115200
92	#undef CONFIG_SERIAL_MULTI
93	#undef CONFIG_UART1_CONSOLE /* define if you want console on UART1 */
94
95	#define CFG_BAUDRATE_TABLE \
96	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
97
98	/*-----------------------------------------------------------------------
99	* Environment
100	----------------------------------------------------------------------/
101	/*
102	* Define here the location of the environment variables (FLASH or EEPROM).
103	* Note: DENX encourages to use redundant environment in FLASH.
104	*/
105	#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
106
107	/*-----------------------------------------------------------------------
108	* FLASH related
109	----------------------------------------------------------------------/
110	#define CFG_MAX_FLASH_BANKS 3 /* max number of memory banks */
111	#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
112
113	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
114	#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
115
116	#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
117
118	#define CFG_FLASH_ADDR0 0x555
119	#define CFG_FLASH_ADDR1 0x2aa
120	#define CFG_FLASH_WORD_SIZE unsigned char
121
122	#ifdef CFG_ENV_IS_IN_FLASH
123	#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
124	#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
125	#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
126
127	/* Address and size of Redundant Environment Sector */
128	#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
129	#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
130	#endif /* CFG_ENV_IS_IN_FLASH */
131
132	/*-----------------------------------------------------------------------
133	* DDR SDRAM
134	----------------------------------------------------------------------/
135	#undef CONFIG_SPD_EEPROM /* SPD EEPROM init doesn't support DDR2 */
136	#define SPD_EEPROM_ADDRESS {0x52,0x53} /* I2C SPD addresses */
137	#define IIC0_DIMM0_ADDR 0x52
138	#define IIC0_DIMM1_ADDR 0x53
139
140	/*-----------------------------------------------------------------------
141	* I2C
142	----------------------------------------------------------------------/
143	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
144	#undef CONFIG_SOFT_I2C /* I2C bit-banged */
145	#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
146	#define CFG_I2C_SLAVE 0x7F
147
148	#define CONFIG_PREBOOT "echo;" \
149	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
150	"echo"
151
152	#undef CONFIG_BOOTARGS
153
154	#define CONFIG_EXTRA_ENV_SETTINGS \
155	"netdev=eth0\0" \
156	"hostname=luan\0" \
157	"nfsargs=setenv bootargs root=/dev/nfs rw " \
158	"nfsroot=$(serverip):$(rootpath)\0" \
159	"ramargs=setenv bootargs root=/dev/ram rw\0" \
160	"addip=setenv bootargs $(bootargs) " \
161	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
162	":$(hostname):$(netdev):off panic=1\0" \
163	"addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\
164	"flash_nfs=run nfsargs addip addtty;" \
165	"bootm $(kernel_addr)\0" \
166	"flash_self=run ramargs addip addtty;" \
167	"bootm $(kernel_addr) $(ramdisk_addr)\0" \
168	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \
169	"bootm\0" \
170	"rootpath=/opt/eldk/ppc_4xx\0" \
171	"bootfile=/tftpboot/luan/uImage\0" \
172	"kernel_addr=fc000000\0" \
173	"ramdisk_addr=fc100000\0" \
174	"load=tftp 100000 /tftpboot/luan/u-boot.bin\0" \
175	"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
176	"cp.b 100000 fffc0000 40000;" \
177	"setenv filesize;saveenv\0" \
178	"upd=run load;run update\0" \
179	""
180	#define CONFIG_BOOTCOMMAND "run flash_self"
181
182	#if 0
183	#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
184	#else
185	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
186	#endif
187
188	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
189	#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
190
191	#define CONFIG_MII 1 /* MII PHY management */
192	#define CONFIG_PHY_ADDR 1
193	#define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */
194	#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
195
196	#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
197
198	#define CONFIG_NETCONSOLE /* include NetConsole support */
199	#define CONFIG_NET_MULTI /* needed for NetConsole */
200
201	/* Partitions */
202	#define CONFIG_MAC_PARTITION
203	#define CONFIG_DOS_PARTITION
204	#define CONFIG_ISO_PARTITION
205
206	#ifdef DEBUG
207	#define CONFIG_PANIC_HANG
208	#else
209	#define CONFIG_HW_WATCHDOG /* watchdog */
210	#endif
211
212	#define CONFIG_COMMANDS (CONFIG_CMD_DFL \| \
213	CFG_CMD_ASKENV \| \
214	CFG_CMD_CACHE \| \
215	CFG_CMD_DHCP \| \
216	CFG_CMD_DIAG \| \
217	CFG_CMD_ELF \| \
218	CFG_CMD_I2C \| \
219	CFG_CMD_IRQ \| \
220	CFG_CMD_MII \| \
221	CFG_CMD_NET \| \
222	CFG_CMD_NFS \| \
223	CFG_CMD_PCI \| \
224	CFG_CMD_PING \| \
225	CFG_CMD_REGINFO \| \
226	CFG_CMD_SETGETDCR \| \
227	CFG_CMD_SDRAM \| \
228	0)
229
230	/* this must be included AFTER the definition of CONFIG_COMMANDS */
231	#include <cmd_confdefs.h>
232
233	/*
234	* Miscellaneous configurable options
235	*/
236	#define CFG_LONGHELP /* undef to save memory */
237	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
238	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
239	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
240	#else
241	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
242	#endif
243	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
244	#define CFG_MAXARGS 16 /* max number of command args */
245	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
246
247	#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
248	#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
249
250	#define CFG_LOAD_ADDR 0x100000 /* default load address */
251	#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
252	#undef CONFIG_LYNXKDI /* support kdi files */
253
254	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
255
256	/*-----------------------------------------------------------------------
257	* PCI stuff
258	*-----------------------------------------------------------------------
259	*/
260	#if (CONFIG_COMMANDS & CFG_CMD_PCI)
261
262	/* General PCI */
263	#define CONFIG_PCI /* include pci support */
264	#define CONFIG_PCI_PNP /* do (not) pci plug-and-play */
265	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
266
267	/* Board-specific PCI */
268	#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
269	#define CFG_PCI_TARGET_INIT
270	#undef CFG_PCI_MASTER_INIT
271
272	#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
273	#define CFG_PCI_SUBSYS_DEVICEID 0x4403 /* whatever */
274
275	#endif /* CONFIG_COMMANDS & CFG_CMD_PCI */
276
277	/*
278	* For booting Linux, the board info and command line data
279	* have to be in the first 8 MB of memory, since this is
280	* the maximum mapped by the Linux kernel during initialization.
281	*/
282	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
283
284	/*-----------------------------------------------------------------------
285	* Cache Configuration
286	*/
287	#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */
288	#define CFG_CACHELINE_SIZE 32 /* ... */
289	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
290	#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
291	#endif
292
293	/*
294	* Internal Definitions
295	*
296	* Boot Flags
297	*/
298	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
299	#define BOOTFLAG_WARM 0x02 /* Software reboot */
300
301	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
302	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
303	#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
304	#endif
305
306	#endif /* __CONFIG_H */