projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| e2211743 | 1 | /* |
| 414eec35 | 2 | * (C) Copyright 2001-2005 |
| e2211743 WD |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 4 | * | |
| 5 | * See file CREDITS for list of people who contributed to this | |
| 6 | * project. | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or | |
| 9 | * modify it under the terms of the GNU General Public License as | |
| 10 | * published by the Free Software Foundation; either version 2 of | |
| 11 | * the License, or (at your option) any later version. | |
| 12 | * | |
| 13 | * This program is distributed in the hope that it will be useful, | |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | * GNU General Public License for more details. | |
| 17 | * | |
| 18 | * You should have received a copy of the GNU General Public License | |
| 19 | * along with this program; if not, write to the Free Software | |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 21 | * MA 02111-1307 USA | |
| 22 | */ | |
| 23 | ||
| 24 | /* | |
| 25 | * board/config.h - configuration options, board specific | |
| 26 | */ | |
| 27 | ||
| 28 | #ifndef __CONFIG_H | |
| 29 | #define __CONFIG_H | |
| 30 | ||
| 56f94be3 WD |
31 | /* External logbuffer support */ |
| 32 | #define CONFIG_LOGBUFFER | |
| 33 | ||
| e2211743 WD |
34 | /* |
| 35 | * High Level Configuration Options | |
| 36 | * (easy to change) | |
| 37 | */ | |
| 38 | ||
| 39 | #define CONFIG_MPC823 1 /* This is a MPC823E CPU */ | |
| 40 | #define CONFIG_LWMON 1 /* ...on a LWMON board */ | |
| 41 | ||
| e3c9b9f9 WD |
42 | /* Default Ethernet MAC address */ |
| 43 | #define CONFIG_ETHADDR 00:11:B0:00:00:00 | |
| 44 | ||
| 45 | /* The default Ethernet MAC address can be overwritten just once */ | |
| 46 | #ifdef CONFIG_ETHADDR | |
| 47 | #define CONFIG_OVERWRITE_ETHADDR_ONCE 1 | |
| 48 | #endif | |
| 49 | ||
| c837dcb1 | 50 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ |
| 4532cb69 | 51 | #define CONFIG_BOARD_POSTCLK_INIT 1 /* Call board_postclk_init */ |
| e2211743 WD |
52 | |
| 53 | #define CONFIG_LCD 1 /* use LCD controller ... */ | |
| 54 | #define CONFIG_HLD1045 1 /* ... with a HLD1045 display */ | |
| 55 | ||
| 4532cb69 WD |
56 | #define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/ |
| 57 | ||
| 281e00a3 | 58 | #define CONFIG_SERIAL_MULTI 1 |
| e2211743 | 59 | #define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */ |
| 281e00a3 | 60 | #define CONFIG_8xx_CONS_SCC2 1 /* Console is on SCC2 */ |
| e2211743 WD |
61 | |
| 62 | #define CONFIG_BAUDRATE 115200 /* with watchdog >= 38400 needed */ | |
| 63 | ||
| 64 | #define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */ | |
| 65 | ||
| 66 | #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ | |
| 67 | ||
| 68 | /* pre-boot commands */ | |
| 69 | #define CONFIG_PREBOOT "setenv bootdelay 15" | |
| 70 | ||
| 71 | #undef CONFIG_BOOTARGS | |
| 72 | ||
| 73 | /* POST support */ | |
| ea909b76 | 74 | #define CONFIG_POST (CFG_POST_CACHE | \ |
| e2211743 | 75 | CFG_POST_WATCHDOG | \ |
| ea909b76 WD |
76 | CFG_POST_RTC | \ |
| 77 | CFG_POST_MEMORY | \ | |
| 78 | CFG_POST_CPU | \ | |
| 79 | CFG_POST_UART | \ | |
| 80 | CFG_POST_ETHER | \ | |
| 81 | CFG_POST_I2C | \ | |
| 82 | CFG_POST_SPI | \ | |
| 83 | CFG_POST_USB | \ | |
| 4532cb69 WD |
84 | CFG_POST_SPR | \ |
| 85 | CFG_POST_SYSMON) | |
| e2211743 | 86 | |
| 31a64923 WD |
87 | /* |
| 88 | * Keyboard commands: | |
| 89 | * # = 0x28 = ENTER : enable bootmessages on LCD | |
| 90 | * 2 = 0x3A+0x3C = F1 + F3 : enable update mode | |
| 91 | * 3 = 0x3C+0x3F = F3 + F6 : enable test mode | |
| 92 | */ | |
| e3c9b9f9 WD |
93 | |
| 94 | #define CONFIG_BOOTCOMMAND "autoscr 40040000;saveenv" | |
| 95 | ||
| 96 | /* "gatewayip=10.8.211.250\0" \ */ | |
| d126bfbd WD |
97 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 98 | "kernel_addr=40080000\0" \ | |
| 99 | "ramdisk_addr=40280000\0" \ | |
| e3c9b9f9 WD |
100 | "netmask=255.255.192.0\0" \ |
| 101 | "serverip=10.8.2.101\0" \ | |
| 102 | "ipaddr=10.8.57.0\0" \ | |
| 31a64923 | 103 | "magic_keys=#23\0" \ |
| d126bfbd WD |
104 | "key_magic#=28\0" \ |
| 105 | "key_cmd#=setenv addfb setenv 'bootargs $bootargs console=tty0'\0" \ | |
| 31a64923 WD |
106 | "key_magic2=3A+3C\0" \ |
| 107 | "key_cmd2=echo *** Entering Update Mode ***;" \ | |
| 108 | "if fatload ide 0:3 10000 update.scr;" \ | |
| 109 | "then autoscr 10000;" \ | |
| 110 | "else echo *** UPDATE FAILED ***;" \ | |
| 111 | "fi\0" \ | |
| d126bfbd WD |
112 | "key_magic3=3C+3F\0" \ |
| 113 | "key_cmd3=echo *** Entering Test Mode ***;" \ | |
| 114 | "setenv add_misc 'setenv bootargs $bootargs testmode'\0" \ | |
| 115 | "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath\0" \ | |
| 116 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
| 117 | "addfb=setenv bootargs $bootargs console=ttyS1,$baudrate\0" \ | |
| 118 | "addip=setenv bootargs $bootargs " \ | |
| 119 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off " \ | |
| 120 | "panic=1\0" \ | |
| 121 | "add_wdt=setenv bootargs $bootargs $wdt_args\0" \ | |
| 122 | "add_misc=setenv bootargs $bootargs runmode\0" \ | |
| 123 | "flash_nfs=run nfsargs addip add_wdt addfb add_misc;" \ | |
| 124 | "bootm $kernel_addr\0" \ | |
| 125 | "flash_self=run ramargs addip add_wdt addfb add_misc;" \ | |
| 126 | "bootm $kernel_addr $ramdisk_addr\0" \ | |
| 127 | "net_nfs=tftp 100000 /tftpboot/uImage.lwmon;" \ | |
| 128 | "run nfsargs addip add_wdt addfb;bootm\0" \ | |
| 129 | "rootpath=/opt/eldk/ppc_8xx\0" \ | |
| 130 | "load=tftp 100000 /tftpboot/u-boot.bin\0" \ | |
| 131 | "update=protect off 1:0;era 1:0;cp.b 100000 40000000 $filesize\0" \ | |
| 132 | "wdt_args=wdt_8xx=off\0" \ | |
| e2211743 WD |
133 | "verify=no" |
| 134 | ||
| 135 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
| 136 | #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ | |
| 137 | ||
| 138 | #define CONFIG_WATCHDOG 1 /* watchdog enabled */ | |
| a8c7c708 | 139 | #define CFG_WATCHDOG_FREQ (CFG_HZ / 20) |
| e2211743 WD |
140 | |
| 141 | #undef CONFIG_STATUS_LED /* Status LED disabled */ | |
| 142 | ||
| 143 | /* enable I2C and select the hardware/software driver */ | |
| ea909b76 WD |
144 | #undef CONFIG_HARD_I2C /* I2C with hardware support */ |
| 145 | #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ | |
| e2211743 | 146 | |
| ea909b76 WD |
147 | #define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */ |
| 148 | #define CFG_I2C_SLAVE 0xFE | |
| e2211743 WD |
149 | |
| 150 | #ifdef CONFIG_SOFT_I2C | |
| 151 | /* | |
| 152 | * Software (bit-bang) I2C driver configuration | |
| 153 | */ | |
| 154 | #define PB_SCL 0x00000020 /* PB 26 */ | |
| 155 | #define PB_SDA 0x00000010 /* PB 27 */ | |
| 156 | ||
| 157 | #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) | |
| 158 | #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) | |
| 159 | #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) | |
| 160 | #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) | |
| 161 | #define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ | |
| 162 | else immr->im_cpm.cp_pbdat &= ~PB_SDA | |
| 163 | #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ | |
| 164 | else immr->im_cpm.cp_pbdat &= ~PB_SCL | |
| 4532cb69 | 165 | #define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ |
| e2211743 WD |
166 | #endif /* CONFIG_SOFT_I2C */ |
| 167 | ||
| 168 | ||
| 169 | #define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */ | |
| 170 | ||
| 171 | #ifdef CONFIG_POST | |
| 172 | #define CFG_CMD_POST_DIAG CFG_CMD_DIAG | |
| 173 | #else | |
| 174 | #define CFG_CMD_POST_DIAG 0 | |
| 175 | #endif | |
| 176 | ||
| e2211743 | 177 | #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ |
| b0fce99b | 178 | CFG_CMD_ASKENV | \ |
| 414eec35 WD |
179 | CFG_CMD_BMP | \ |
| 180 | CFG_CMD_BSP | \ | |
| e2211743 | 181 | CFG_CMD_DATE | \ |
| 414eec35 WD |
182 | CFG_CMD_DHCP | \ |
| 183 | CFG_CMD_EEPROM | \ | |
| 31a64923 | 184 | CFG_CMD_FAT | \ |
| e2211743 | 185 | CFG_CMD_I2C | \ |
| e2211743 | 186 | CFG_CMD_IDE | \ |
| 414eec35 WD |
187 | CFG_CMD_NFS | \ |
| 188 | CFG_CMD_POST_DIAG | \ | |
| 189 | CFG_CMD_SNTP ) | |
| e2211743 WD |
190 | #define CONFIG_MAC_PARTITION |
| 191 | #define CONFIG_DOS_PARTITION | |
| 192 | ||
| 193 | #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) | |
| 194 | ||
| 195 | /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ | |
| 196 | #include <cmd_confdefs.h> | |
| 197 | ||
| 198 | /*----------------------------------------------------------------------*/ | |
| 199 | ||
| 200 | /* | |
| 201 | * Miscellaneous configurable options | |
| 202 | */ | |
| 203 | #define CFG_LONGHELP /* undef to save memory */ | |
| 204 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
| 205 | ||
| d126bfbd | 206 | #define CFG_HUSH_PARSER 1 /* use "hush" command parser */ |
| e2211743 WD |
207 | #ifdef CFG_HUSH_PARSER |
| 208 | #define CFG_PROMPT_HUSH_PS2 "> " | |
| f12e568c | 209 | #endif |
| e2211743 WD |
210 | |
| 211 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
| 212 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ | |
| 213 | #else | |
| 214 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
| 215 | #endif | |
| 216 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
| 217 | #define CFG_MAXARGS 16 /* max number of command args */ | |
| 218 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
| 219 | ||
| 220 | #define CFG_MEMTEST_START 0x00100000 /* memtest works on */ | |
| 221 | #define CFG_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */ | |
| 222 | ||
| 223 | #define CFG_LOAD_ADDR 0x00100000 /* default load address */ | |
| 224 | ||
| 225 | #define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */ | |
| 226 | ||
| 227 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
| 228 | ||
| d0fb80c3 WD |
229 | /* |
| 230 | * When the watchdog is enabled, output must be fast enough in Linux. | |
| 231 | */ | |
| 232 | #ifdef CONFIG_WATCHDOG | |
| 233 | #define CFG_BAUDRATE_TABLE { 38400, 57600, 115200 } | |
| 234 | #else | |
| 235 | #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } | |
| 236 | #endif | |
| e2211743 | 237 | |
| 2e5983d2 WD |
238 | /*----------------------------------------------------------------------*/ |
| 239 | #define CONFIG_MODEM_SUPPORT 1 /* enable modem initialization stuff */ | |
| 240 | #undef CONFIG_MODEM_SUPPORT_DEBUG | |
| 241 | ||
| ad12965d | 242 | #define CONFIG_MODEM_KEY_MAGIC "3C+3D" /* press F3 + F4 keys to enable modem */ |
| 2e5983d2 WD |
243 | #define CONFIG_POST_KEY_MAGIC "3C+3E" /* press F3 + F5 keys to force POST */ |
| 244 | #if 0 | |
| 245 | #define CONFIG_AUTOBOOT_KEYED /* Enable "password" protection */ | |
| 246 | #define CONFIG_AUTOBOOT_PROMPT "\nEnter password - autoboot in %d sec...\n" | |
| 247 | #define CONFIG_AUTOBOOT_DELAY_STR " " /* "password" */ | |
| 248 | #endif | |
| 249 | /*----------------------------------------------------------------------*/ | |
| 250 | ||
| e2211743 WD |
251 | /* |
| 252 | * Low Level Configuration Settings | |
| 253 | * (address mappings, register initial values, etc.) | |
| 254 | * You should know what you are doing if you make changes here. | |
| 255 | */ | |
| 256 | /*----------------------------------------------------------------------- | |
| 257 | * Internal Memory Mapped Register | |
| 258 | */ | |
| 259 | #define CFG_IMMR 0xFFF00000 | |
| 260 | ||
| 261 | /*----------------------------------------------------------------------- | |
| 262 | * Definitions for initial stack pointer and data area (in DPRAM) | |
| 263 | */ | |
| 264 | #define CFG_INIT_RAM_ADDR CFG_IMMR | |
| 265 | #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ | |
| 4532cb69 | 266 | #define CFG_GBL_DATA_SIZE 68 /* size in bytes reserved for initial data */ |
| e2211743 WD |
267 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
| 268 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
| 269 | ||
| 270 | /*----------------------------------------------------------------------- | |
| 271 | * Start addresses for the final memory configuration | |
| 272 | * (Set up by the startup code) | |
| 273 | * Please note that CFG_SDRAM_BASE _must_ start at 0 | |
| 274 | */ | |
| 275 | #define CFG_SDRAM_BASE 0x00000000 | |
| 276 | #define CFG_FLASH_BASE 0x40000000 | |
| 277 | #if defined(DEBUG) || (CONFIG_COMMANDS & CFG_CMD_IDE) | |
| 278 | #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
| 279 | #else | |
| 280 | #define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ | |
| 281 | #endif | |
| 282 | #define CFG_MONITOR_BASE CFG_FLASH_BASE | |
| 283 | #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
| 284 | ||
| 285 | /* | |
| 286 | * For booting Linux, the board info and command line data | |
| 287 | * have to be in the first 8 MB of memory, since this is | |
| 288 | * the maximum mapped by the Linux kernel during initialization. | |
| 289 | */ | |
| 290 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
| 291 | /*----------------------------------------------------------------------- | |
| 292 | * FLASH organization | |
| 293 | */ | |
| 294 | #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ | |
| 295 | #define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ | |
| 296 | ||
| 297 | #define CFG_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */ | |
| 298 | #define CFG_FLASH_WRITE_TOUT 600 /* Timeout for Flash Write (in ms) */ | |
| c837dcb1 WD |
299 | #define CFG_FLASH_USE_BUFFER_WRITE |
| 300 | #define CFG_FLASH_BUFFER_WRITE_TOUT 2048 /* Timeout for Flash Buffer Write (in ms) */ | |
| a2d18bb7 WD |
301 | /* Buffer size. |
| 302 | We have two flash devices connected in parallel. | |
| 303 | Each device incorporates a Write Buffer of 32 bytes. | |
| 304 | */ | |
| 305 | #define CFG_FLASH_BUFFER_SIZE (2*32) | |
| e2211743 | 306 | |
| 31a64923 | 307 | /* Put environment in flash which is much faster to boot than using the EEPROM */ |
| e2211743 WD |
308 | #define CFG_ENV_IS_IN_FLASH 1 |
| 309 | #define CFG_ENV_ADDR 0x40040000 /* Address of Environment Sector */ | |
| 310 | #define CFG_ENV_SIZE 0x2000 /* Total Size of Environment */ | |
| 311 | #define CFG_ENV_SECT_SIZE 0x40000 /* we have BIG sectors only :-( */ | |
| 31a64923 | 312 | |
| e2211743 WD |
313 | /*----------------------------------------------------------------------- |
| 314 | * I2C/EEPROM Configuration | |
| 315 | */ | |
| 316 | ||
| 317 | #define CFG_I2C_AUDIO_ADDR 0x28 /* Audio volume control */ | |
| 318 | #define CFG_I2C_SYSMON_ADDR 0x2E /* LM87 System Monitor */ | |
| 319 | #define CFG_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */ | |
| 320 | #define CFG_I2C_POWER_A_ADDR 0x52 /* PCMCIA/USB power switch, channel A */ | |
| 321 | #define CFG_I2C_POWER_B_ADDR 0x53 /* PCMCIA/USB power switch, channel B */ | |
| 322 | #define CFG_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */ | |
| 323 | #define CFG_I2C_PICIO_ADDR 0x57 /* PIC IO Expander */ | |
| 324 | ||
| 288b3d7f WD |
325 | #undef CONFIG_USE_FRAM /* Use FRAM instead of EEPROM */ |
| 326 | ||
| e2211743 WD |
327 | #ifdef CONFIG_USE_FRAM /* use FRAM */ |
| 328 | #define CFG_I2C_EEPROM_ADDR 0x55 /* FRAM FM24CL64 */ | |
| 329 | #define CFG_I2C_EEPROM_ADDR_LEN 2 | |
| 330 | #else /* use EEPROM */ | |
| 331 | #define CFG_I2C_EEPROM_ADDR 0x58 /* EEPROM AT24C164 */ | |
| 332 | #define CFG_I2C_EEPROM_ADDR_LEN 1 | |
| 333 | #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */ | |
| 334 | #endif /* CONFIG_USE_FRAM */ | |
| 335 | #define CFG_EEPROM_PAGE_WRITE_BITS 4 | |
| 336 | ||
| 6aff3115 | 337 | /* List of I2C addresses to be verified by POST */ |
| 288b3d7f | 338 | #ifdef CONFIG_USE_FRAM |
| 6aff3115 WD |
339 | #define I2C_ADDR_LIST { /* CFG_I2C_AUDIO_ADDR, */ \ |
| 340 | CFG_I2C_SYSMON_ADDR, \ | |
| 341 | CFG_I2C_RTC_ADDR, \ | |
| 342 | CFG_I2C_POWER_A_ADDR, \ | |
| 343 | CFG_I2C_POWER_B_ADDR, \ | |
| 344 | CFG_I2C_KEYBD_ADDR, \ | |
| 345 | CFG_I2C_PICIO_ADDR, \ | |
| 346 | CFG_I2C_EEPROM_ADDR, \ | |
| 347 | } | |
| 288b3d7f WD |
348 | #else /* Use EEPROM - which show up on 8 consequtive addresses */ |
| 349 | #define I2C_ADDR_LIST { /* CFG_I2C_AUDIO_ADDR, */ \ | |
| 350 | CFG_I2C_SYSMON_ADDR, \ | |
| 351 | CFG_I2C_RTC_ADDR, \ | |
| 352 | CFG_I2C_POWER_A_ADDR, \ | |
| 353 | CFG_I2C_POWER_B_ADDR, \ | |
| 354 | CFG_I2C_KEYBD_ADDR, \ | |
| 355 | CFG_I2C_PICIO_ADDR, \ | |
| 356 | CFG_I2C_EEPROM_ADDR+0, \ | |
| 357 | CFG_I2C_EEPROM_ADDR+1, \ | |
| 358 | CFG_I2C_EEPROM_ADDR+2, \ | |
| 359 | CFG_I2C_EEPROM_ADDR+3, \ | |
| 360 | CFG_I2C_EEPROM_ADDR+4, \ | |
| 361 | CFG_I2C_EEPROM_ADDR+5, \ | |
| 362 | CFG_I2C_EEPROM_ADDR+6, \ | |
| 363 | CFG_I2C_EEPROM_ADDR+7, \ | |
| 364 | } | |
| 365 | #endif /* CONFIG_USE_FRAM */ | |
| 6aff3115 | 366 | |
| e2211743 WD |
367 | /*----------------------------------------------------------------------- |
| 368 | * Cache Configuration | |
| 369 | */ | |
| 370 | #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ | |
| 371 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
| 372 | #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ | |
| 373 | #endif | |
| 374 | ||
| 375 | /*----------------------------------------------------------------------- | |
| 376 | * SYPCR - System Protection Control 11-9 | |
| 377 | * SYPCR can only be written once after reset! | |
| 378 | *----------------------------------------------------------------------- | |
| 379 | * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze | |
| 380 | */ | |
| 381 | #if 0 && defined(CONFIG_WATCHDOG) /* LWMON uses external MAX706TESA WD */ | |
| 382 | #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ | |
| 383 | SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) | |
| 384 | #else | |
| 385 | #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) | |
| 386 | #endif | |
| 387 | ||
| 388 | /*----------------------------------------------------------------------- | |
| 389 | * SIUMCR - SIU Module Configuration 11-6 | |
| 390 | *----------------------------------------------------------------------- | |
| 391 | * PCMCIA config., multi-function pin tri-state | |
| 392 | */ | |
| 393 | /* EARB, DBGC and DBPC are initialised by the HCW */ | |
| 394 | /* => 0x000000C0 */ | |
| 395 | #define CFG_SIUMCR (SIUMCR_GB5E) | |
| 396 | /*#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) */ | |
| 397 | ||
| 398 | /*----------------------------------------------------------------------- | |
| 399 | * TBSCR - Time Base Status and Control 11-26 | |
| 400 | *----------------------------------------------------------------------- | |
| 401 | * Clear Reference Interrupt Status, Timebase freezing enabled | |
| 402 | */ | |
| 403 | #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) | |
| 404 | ||
| 405 | /*----------------------------------------------------------------------- | |
| 406 | * PISCR - Periodic Interrupt Status and Control 11-31 | |
| 407 | *----------------------------------------------------------------------- | |
| 408 | * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled | |
| 409 | */ | |
| 410 | #define CFG_PISCR (PISCR_PS | PISCR_PITF) | |
| 411 | ||
| 412 | /*----------------------------------------------------------------------- | |
| 413 | * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 | |
| 414 | *----------------------------------------------------------------------- | |
| 415 | * Reset PLL lock status sticky bit, timer expired status bit and timer | |
| 416 | * interrupt status bit, set PLL multiplication factor ! | |
| 417 | */ | |
| 418 | /* 0x00405000 */ | |
| 419 | #define CFG_PLPRCR_MF 4 /* (4+1) * 13.2 = 66 MHz Clock */ | |
| 420 | #define CFG_PLPRCR \ | |
| 421 | ( (CFG_PLPRCR_MF << PLPRCR_MF_SHIFT) | \ | |
| 422 | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | \ | |
| 423 | /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \ | |
| 424 | PLPRCR_CSR /*| PLPRCR_LOLRE|PLPRCR_FIOPD*/ \ | |
| 425 | ) | |
| 426 | ||
| 427 | #define CONFIG_8xx_GCLK_FREQ ((CFG_PLPRCR_MF+1)*13200000) | |
| 428 | ||
| 429 | /*----------------------------------------------------------------------- | |
| 430 | * SCCR - System Clock and reset Control Register 15-27 | |
| 431 | *----------------------------------------------------------------------- | |
| 432 | * Set clock output, timebase and RTC source and divider, | |
| 433 | * power management and some other internal clocks | |
| 434 | */ | |
| 435 | #define SCCR_MASK SCCR_EBDF11 | |
| 436 | /* 0x01800000 */ | |
| 437 | #define CFG_SCCR (SCCR_COM00 | /*SCCR_TBS|*/ \ | |
| 438 | SCCR_RTDIV | SCCR_RTSEL | \ | |
| 439 | /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \ | |
| 440 | SCCR_EBDF00 | SCCR_DFSYNC00 | \ | |
| 441 | SCCR_DFBRG00 | SCCR_DFNL000 | \ | |
| 442 | SCCR_DFNH000 | SCCR_DFLCD100 | \ | |
| 443 | SCCR_DFALCD01) | |
| 444 | ||
| 445 | /*----------------------------------------------------------------------- | |
| 446 | * RTCSC - Real-Time Clock Status and Control Register 11-27 | |
| 447 | *----------------------------------------------------------------------- | |
| 448 | */ | |
| 449 | /* 0x00C3 => 0x0003 */ | |
| 450 | #define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) | |
| 451 | ||
| 452 | ||
| 453 | /*----------------------------------------------------------------------- | |
| 454 | * RCCR - RISC Controller Configuration Register 19-4 | |
| 455 | *----------------------------------------------------------------------- | |
| 456 | */ | |
| 457 | #define CFG_RCCR 0x0000 | |
| 458 | ||
| 459 | /*----------------------------------------------------------------------- | |
| 460 | * RMDS - RISC Microcode Development Support Control Register | |
| 461 | *----------------------------------------------------------------------- | |
| 462 | */ | |
| 463 | #define CFG_RMDS 0 | |
| 464 | ||
| 465 | /*----------------------------------------------------------------------- | |
| 466 | * | |
| 467 | * Interrupt Levels | |
| 468 | *----------------------------------------------------------------------- | |
| 469 | */ | |
| 470 | #define CFG_CPM_INTERRUPT 13 /* SIU_LEVEL6 */ | |
| 471 | ||
| 472 | /*----------------------------------------------------------------------- | |
| 473 | * PCMCIA stuff | |
| 474 | *----------------------------------------------------------------------- | |
| 475 | * | |
| 476 | */ | |
| 477 | #define CFG_PCMCIA_MEM_ADDR (0x50000000) | |
| 478 | #define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) | |
| 479 | #define CFG_PCMCIA_DMA_ADDR (0x54000000) | |
| 480 | #define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) | |
| 481 | #define CFG_PCMCIA_ATTRB_ADDR (0x58000000) | |
| 482 | #define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) | |
| 483 | #define CFG_PCMCIA_IO_ADDR (0x5C000000) | |
| 484 | #define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) | |
| 485 | ||
| 486 | /*----------------------------------------------------------------------- | |
| 487 | * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) | |
| 488 | *----------------------------------------------------------------------- | |
| 489 | */ | |
| 490 | ||
| 491 | #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ | |
| 492 | ||
| 493 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ | |
| 494 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
| 495 | #undef CONFIG_IDE_RESET /* reset for ide not supported */ | |
| 496 | ||
| 497 | #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ | |
| 498 | #define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ | |
| 499 | ||
| 500 | #define CFG_ATA_IDE0_OFFSET 0x0000 | |
| 501 | ||
| 502 | #define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR | |
| 503 | ||
| 504 | /* Offset for data I/O */ | |
| 505 | #define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) | |
| 506 | ||
| 507 | /* Offset for normal register accesses */ | |
| 508 | #define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) | |
| 509 | ||
| 510 | /* Offset for alternate registers */ | |
| 511 | #define CFG_ATA_ALT_OFFSET 0x0100 | |
| 512 | ||
| 31a64923 WD |
513 | #define CONFIG_SUPPORT_VFAT /* enable VFAT support */ |
| 514 | ||
| e2211743 WD |
515 | /*----------------------------------------------------------------------- |
| 516 | * | |
| 517 | *----------------------------------------------------------------------- | |
| 518 | * | |
| 519 | */ | |
| e2211743 WD |
520 | #define CFG_DER 0 |
| 521 | ||
| 522 | /* | |
| 523 | * Init Memory Controller: | |
| 524 | * | |
| 525 | * BR0/1 and OR0/1 (FLASH) - second Flash bank optional | |
| 526 | */ | |
| 527 | ||
| 528 | #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ | |
| 529 | #define FLASH_BASE1_PRELIM 0x41000000 /* FLASH bank #1 */ | |
| 530 | ||
| 531 | /* used to re-map FLASH: | |
| 532 | * restrict access enough to keep SRAM working (if any) | |
| 533 | * but not too much to meddle with FLASH accesses | |
| 534 | */ | |
| 535 | #define CFG_REMAP_OR_AM 0xFF000000 /* OR addr mask */ | |
| 536 | #define CFG_PRELIM_OR_AM 0xFF000000 /* OR addr mask */ | |
| 537 | ||
| 538 | /* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 8, EHTR = 0 */ | |
| 539 | #define CFG_OR_TIMING_FLASH (OR_SCY_8_CLK) | |
| 540 | ||
| 541 | #define CFG_OR0_REMAP ( CFG_REMAP_OR_AM | OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \ | |
| 542 | CFG_OR_TIMING_FLASH) | |
| 543 | #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | OR_ACS_DIV1 | OR_BI | \ | |
| 544 | CFG_OR_TIMING_FLASH) | |
| 545 | /* 16 bit, bank valid */ | |
| 546 | #define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V ) | |
| 547 | ||
| 548 | #define CFG_OR1_REMAP CFG_OR0_REMAP | |
| 549 | #define CFG_OR1_PRELIM CFG_OR0_PRELIM | |
| 550 | #define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V ) | |
| 551 | ||
| 552 | /* | |
| 553 | * BR3/OR3: SDRAM | |
| 554 | * | |
| 555 | * Multiplexed addresses, GPL5 output to GPL5_A (don't care) | |
| 556 | */ | |
| 557 | #define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */ | |
| 558 | #define SDRAM_PRELIM_OR_AM 0xF0000000 /* map 256 MB (>SDRAM_MAX_SIZE!) */ | |
| 559 | #define SDRAM_TIMING OR_SCY_0_CLK /* SDRAM-Timing */ | |
| 560 | ||
| 561 | #define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB SDRAM */ | |
| 562 | ||
| 563 | #define CFG_OR3_PRELIM (SDRAM_PRELIM_OR_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING ) | |
| 564 | #define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) | |
| 565 | ||
| 566 | /* | |
| 567 | * BR5/OR5: Touch Panel | |
| 568 | * | |
| 569 | * AM=0xFFC00 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=3 BIH=1 SCY=0 SETA=0 TRLX=0 EHTR=0 | |
| 570 | */ | |
| 571 | #define TOUCHPNL_BASE 0x20000000 | |
| 572 | #define TOUCHPNL_OR_AM 0xFFFF8000 | |
| 573 | #define TOUCHPNL_TIMING OR_SCY_0_CLK | |
| 574 | ||
| 575 | #define CFG_OR5_PRELIM (TOUCHPNL_OR_AM | OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \ | |
| 576 | TOUCHPNL_TIMING ) | |
| 577 | #define CFG_BR5_PRELIM ((TOUCHPNL_BASE & BR_BA_MSK) | BR_PS_32 | BR_V ) | |
| 578 | ||
| 579 | #define CFG_MEMORY_75 | |
| 580 | #undef CFG_MEMORY_7E | |
| 581 | #undef CFG_MEMORY_8E | |
| 582 | ||
| 583 | /* | |
| 584 | * Memory Periodic Timer Prescaler | |
| 585 | */ | |
| 586 | ||
| 587 | /* periodic timer for refresh */ | |
| 588 | #define CFG_MPTPR 0x200 | |
| 589 | ||
| 590 | /* | |
| 591 | * MAMR settings for SDRAM | |
| 592 | */ | |
| 593 | ||
| 594 | #define CFG_MAMR_8COL 0x80802114 | |
| 595 | #define CFG_MAMR_9COL 0x80904114 | |
| 596 | ||
| 597 | /* | |
| 598 | * MAR setting for SDRAM | |
| 599 | */ | |
| 600 | #define CFG_MAR 0x00000088 | |
| 601 | ||
| 602 | /* | |
| 603 | * Internal Definitions | |
| 604 | * | |
| 605 | * Boot Flags | |
| 606 | */ | |
| 607 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
| 608 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
| 609 | ||
| 610 | #endif /* __CONFIG_H */ |