projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 04386f65 SR |
1 | /* |
| 2 | * (C) Copyright 2007-2013 | |
| 3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
| 4 | * | |
| 5 | * SPDX-License-Identifier: GPL-2.0+ | |
| 6 | */ | |
| 7 | ||
| 8 | /* | |
| 9 | * lwmon5.h - configuration for lwmon5 board | |
| 10 | */ | |
| 11 | #ifndef __CONFIG_H | |
| 12 | #define __CONFIG_H | |
| 13 | ||
| 04386f65 SR |
14 | /* |
| 15 | * High Level Configuration Options | |
| 16 | */ | |
| 17 | #define CONFIG_LWMON5 1 /* Board is lwmon5 */ | |
| 18 | #define CONFIG_440EPX 1 /* Specific PPC440EPx */ | |
| 19 | #define CONFIG_440 1 /* ... PPC440 family */ | |
| 20 | ||
| 04386f65 SR |
21 | #define CONFIG_SYS_TEXT_BASE 0xFFF80000 |
| 22 | #define CONFIG_HOSTNAME lwmon5 | |
| 04386f65 SR |
23 | |
| 24 | #define CONFIG_SYS_CLK_FREQ 33300000 /* external freq to pll */ | |
| 25 | ||
| 26 | #define CONFIG_4xx_DCACHE /* enable cache in SDRAM */ | |
| 27 | ||
| 28 | #define CONFIG_BOARD_EARLY_INIT_F /* Call board_early_init_f */ | |
| 29 | #define CONFIG_BOARD_EARLY_INIT_R /* Call board_early_init_r */ | |
| 30 | #define CONFIG_BOARD_POSTCLK_INIT /* Call board_postclk_init */ | |
| 31 | #define CONFIG_MISC_INIT_R /* Call misc_init_r */ | |
| 32 | #define CONFIG_BOARD_RESET /* Call board_reset */ | |
| 33 | ||
| 34 | /* | |
| 35 | * Base addresses -- Note these are effective addresses where the | |
| 36 | * actual resources get mapped (not physical addresses) | |
| 37 | */ | |
| 38 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Start of U-Boot */ | |
| 39 | #define CONFIG_SYS_MONITOR_LEN 0x80000 | |
| 40 | #define CONFIG_SYS_MALLOC_LEN (1 << 20) /* Reserved for malloc */ | |
| 41 | ||
| 42 | #define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000 | |
| 43 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */ | |
| 44 | #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */ | |
| 45 | #define CONFIG_SYS_LIME_BASE_0 0xc0000000 | |
| 46 | #define CONFIG_SYS_LIME_BASE_1 0xc1000000 | |
| 47 | #define CONFIG_SYS_LIME_BASE_2 0xc2000000 | |
| 48 | #define CONFIG_SYS_LIME_BASE_3 0xc3000000 | |
| 49 | #define CONFIG_SYS_FPGA_BASE_0 0xc4000000 | |
| 50 | #define CONFIG_SYS_FPGA_BASE_1 0xc4200000 | |
| 51 | #define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */ | |
| 52 | #define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */ | |
| 53 | #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ | |
| 54 | #define CONFIG_SYS_PCI_MEMBASE1 (CONFIG_SYS_PCI_MEMBASE + 0x10000000) | |
| 55 | #define CONFIG_SYS_PCI_MEMBASE2 (CONFIG_SYS_PCI_MEMBASE1 + 0x10000000) | |
| 56 | #define CONFIG_SYS_PCI_MEMBASE3 (CONFIG_SYS_PCI_MEMBASE2 + 0x10000000) | |
| 57 | ||
| 04386f65 SR |
58 | #define CONFIG_SYS_USB2D0_BASE 0xe0000100 |
| 59 | #define CONFIG_SYS_USB_DEVICE 0xe0000000 | |
| 60 | #define CONFIG_SYS_USB_HOST 0xe0000400 | |
| 04386f65 SR |
61 | |
| 62 | /* | |
| 63 | * Initial RAM & stack pointer | |
| 64 | * | |
| 65 | * On LWMON5 we use D-cache as init-ram and stack pointer. We also move | |
| 66 | * the POST_WORD from OCM to a 440EPx register that preserves it's | |
| 67 | * content during reset (GPT0_COMP6). This way we reserve the OCM (16k) | |
| 68 | * for logbuffer only. (GPT0_COMP1-COMP5 are reserved for logbuffer header.) | |
| 69 | */ | |
| 04386f65 SR |
70 | #define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram */ |
| 71 | #define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */ | |
| 72 | #define CONFIG_SYS_INIT_RAM_SIZE (4 << 10) | |
| 73 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ | |
| 74 | GENERATED_GBL_DATA_SIZE) | |
| 75 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
| b6b5e394 | 76 | |
| 04386f65 SR |
77 | /* unused GPT0 COMP reg */ |
| 78 | #define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6) | |
| 79 | #define CONFIG_SYS_OCM_SIZE (16 << 10) | |
| 80 | /* 440EPx errata CHIP 11: don't use last 4kbytes */ | |
| 81 | #define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) | |
| 82 | ||
| 83 | /* Additional registers for watchdog timer post test */ | |
| 84 | #define CONFIG_SYS_WATCHDOG_TIME_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK2) | |
| 85 | #define CONFIG_SYS_WATCHDOG_FLAGS_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK1) | |
| 86 | #define CONFIG_SYS_DSPIC_TEST_ADDR CONFIG_SYS_WATCHDOG_FLAGS_ADDR | |
| 87 | #define CONFIG_SYS_OCM_STATUS_ADDR CONFIG_SYS_WATCHDOG_FLAGS_ADDR | |
| 88 | #define CONFIG_SYS_WATCHDOG_MAGIC 0x12480000 | |
| 89 | #define CONFIG_SYS_WATCHDOG_MAGIC_MASK 0xFFFF0000 | |
| 90 | #define CONFIG_SYS_DSPIC_TEST_MASK 0x00000001 | |
| 91 | #define CONFIG_SYS_OCM_STATUS_OK 0x00009A00 | |
| 92 | #define CONFIG_SYS_OCM_STATUS_FAIL 0x0000A300 | |
| 93 | #define CONFIG_SYS_OCM_STATUS_MASK 0x0000FF00 | |
| 94 | ||
| 95 | /* | |
| 96 | * Serial Port | |
| 97 | */ | |
| 98 | #define CONFIG_CONS_INDEX 2 /* Use UART1 */ | |
| 04386f65 SR |
99 | #define CONFIG_SYS_NS16550_SERIAL |
| 100 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
| 101 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() | |
| 102 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external clock provided */ | |
| 103 | #define CONFIG_BAUDRATE 115200 | |
| 104 | ||
| 105 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
| 106 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} | |
| 107 | ||
| 108 | /* | |
| 109 | * Environment | |
| 110 | */ | |
| 111 | #define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */ | |
| 112 | ||
| 113 | /* | |
| 114 | * FLASH related | |
| 115 | */ | |
| 116 | #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ | |
| 117 | #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ | |
| 118 | ||
| 119 | #define CONFIG_SYS_FLASH0 0xFC000000 | |
| 120 | #define CONFIG_SYS_FLASH1 0xF8000000 | |
| 121 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 } | |
| 122 | ||
| 123 | #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2 /* max number of memory banks */ | |
| 124 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ | |
| 125 | ||
| 126 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ | |
| 127 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
| 128 | ||
| 129 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */ | |
| 130 | #define CONFIG_SYS_FLASH_PROTECTION /* use hardware flash protection */ | |
| 131 | ||
| 132 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ | |
| 133 | #define CONFIG_SYS_FLASH_QUIET_TEST /* don't warn upon unknown flash */ | |
| 134 | ||
| 135 | #define CONFIG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */ | |
| 136 | #define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN) - CONFIG_ENV_SECT_SIZE) | |
| 137 | #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ | |
| 138 | ||
| 139 | /* Address and size of Redundant Environment Sector */ | |
| 140 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE) | |
| 141 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
| 142 | ||
| 143 | /* | |
| 144 | * DDR SDRAM | |
| 145 | */ | |
| 146 | #define CONFIG_SYS_MBYTES_SDRAM 256 | |
| 147 | #define CONFIG_SYS_DDR_CACHED_ADDR 0x40000000 /* setup 2nd TLB cached here */ | |
| 148 | #define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */ | |
| 04386f65 | 149 | #define CONFIG_DDR_ECC /* enable ECC */ |
| 04386f65 | 150 | |
| 04386f65 SR |
151 | /* POST support */ |
| 152 | #define CONFIG_POST (CONFIG_SYS_POST_CACHE | \ | |
| 153 | CONFIG_SYS_POST_CPU | \ | |
| 154 | CONFIG_SYS_POST_ECC | \ | |
| 155 | CONFIG_SYS_POST_ETHER | \ | |
| 156 | CONFIG_SYS_POST_FPU | \ | |
| 157 | CONFIG_SYS_POST_I2C | \ | |
| 158 | CONFIG_SYS_POST_MEMORY | \ | |
| 159 | CONFIG_SYS_POST_OCM | \ | |
| 160 | CONFIG_SYS_POST_RTC | \ | |
| 161 | CONFIG_SYS_POST_SPR | \ | |
| 162 | CONFIG_SYS_POST_UART | \ | |
| 163 | CONFIG_SYS_POST_SYSMON | \ | |
| 164 | CONFIG_SYS_POST_WATCHDOG | \ | |
| 165 | CONFIG_SYS_POST_DSP | \ | |
| 166 | CONFIG_SYS_POST_BSPEC1 | \ | |
| 167 | CONFIG_SYS_POST_BSPEC2 | \ | |
| 168 | CONFIG_SYS_POST_BSPEC3 | \ | |
| 169 | CONFIG_SYS_POST_BSPEC4 | \ | |
| 170 | CONFIG_SYS_POST_BSPEC5) | |
| 171 | ||
| 172 | /* Define here the base-addresses of the UARTs to test in POST */ | |
| 173 | #define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1, \ | |
| 174 | CONFIG_SYS_NS16550_COM2 } | |
| 175 | ||
| 176 | #define CONFIG_POST_UART { \ | |
| 177 | "UART test", \ | |
| 178 | "uart", \ | |
| 179 | "This test verifies the UART operation.", \ | |
| 180 | POST_RAM | POST_SLOWTEST | POST_ALWAYS | POST_MANUAL, \ | |
| 181 | &uart_post_test, \ | |
| 182 | NULL, \ | |
| 183 | NULL, \ | |
| 184 | CONFIG_SYS_POST_UART \ | |
| 185 | } | |
| 186 | ||
| 187 | #define CONFIG_POST_WATCHDOG { \ | |
| 188 | "Watchdog timer test", \ | |
| 189 | "watchdog", \ | |
| 190 | "This test checks the watchdog timer.", \ | |
| 191 | POST_RAM | POST_POWERON | POST_SLOWTEST | POST_MANUAL | POST_REBOOT, \ | |
| 192 | &lwmon5_watchdog_post_test, \ | |
| 193 | NULL, \ | |
| 194 | NULL, \ | |
| 195 | CONFIG_SYS_POST_WATCHDOG \ | |
| 196 | } | |
| 197 | ||
| 198 | #define CONFIG_POST_BSPEC1 { \ | |
| 199 | "dsPIC init test", \ | |
| 200 | "dspic_init", \ | |
| 201 | "This test returns result of dsPIC READY test run earlier.", \ | |
| 202 | POST_RAM | POST_ALWAYS, \ | |
| 203 | &dspic_init_post_test, \ | |
| 204 | NULL, \ | |
| 205 | NULL, \ | |
| 206 | CONFIG_SYS_POST_BSPEC1 \ | |
| 207 | } | |
| 208 | ||
| 209 | #define CONFIG_POST_BSPEC2 { \ | |
| 210 | "dsPIC test", \ | |
| 211 | "dspic", \ | |
| 212 | "This test gets result of dsPIC POST and dsPIC version.", \ | |
| 213 | POST_RAM | POST_ALWAYS, \ | |
| 214 | &dspic_post_test, \ | |
| 215 | NULL, \ | |
| 216 | NULL, \ | |
| 217 | CONFIG_SYS_POST_BSPEC2 \ | |
| 218 | } | |
| 219 | ||
| 220 | #define CONFIG_POST_BSPEC3 { \ | |
| 221 | "FPGA test", \ | |
| 222 | "fpga", \ | |
| 223 | "This test checks FPGA registers and memory.", \ | |
| 224 | POST_RAM | POST_ALWAYS | POST_MANUAL, \ | |
| 225 | &fpga_post_test, \ | |
| 226 | NULL, \ | |
| 227 | NULL, \ | |
| 228 | CONFIG_SYS_POST_BSPEC3 \ | |
| 229 | } | |
| 230 | ||
| 231 | #define CONFIG_POST_BSPEC4 { \ | |
| 232 | "GDC test", \ | |
| 233 | "gdc", \ | |
| 234 | "This test checks GDC registers and memory.", \ | |
| 235 | POST_RAM | POST_ALWAYS | POST_MANUAL,\ | |
| 236 | &gdc_post_test, \ | |
| 237 | NULL, \ | |
| 238 | NULL, \ | |
| 239 | CONFIG_SYS_POST_BSPEC4 \ | |
| 240 | } | |
| 241 | ||
| 242 | #define CONFIG_POST_BSPEC5 { \ | |
| 243 | "SYSMON1 test", \ | |
| 244 | "sysmon1", \ | |
| 245 | "This test checks GPIO_62_EPX pin indicating power failure.", \ | |
| 246 | POST_RAM | POST_MANUAL | POST_NORMAL | POST_SLOWTEST, \ | |
| 247 | &sysmon1_post_test, \ | |
| 248 | NULL, \ | |
| 249 | NULL, \ | |
| 250 | CONFIG_SYS_POST_BSPEC5 \ | |
| 251 | } | |
| 252 | ||
| 253 | #define CONFIG_SYS_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */ | |
| 254 | #define CONFIG_LOGBUFFER | |
| 255 | /* Reserve GPT0_COMP1-COMP5 for logbuffer header */ | |
| 256 | #define CONFIG_ALT_LH_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP1) | |
| 257 | #define CONFIG_ALT_LB_ADDR (CONFIG_SYS_OCM_BASE) | |
| 258 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ | |
| 04386f65 SR |
259 | |
| 260 | /* | |
| 261 | * I2C | |
| 262 | */ | |
| 263 | #define CONFIG_SYS_I2C | |
| 264 | #define CONFIG_SYS_I2C_PPC4XX | |
| 265 | #define CONFIG_SYS_I2C_PPC4XX_CH0 | |
| 266 | #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000 | |
| 267 | #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F | |
| 268 | ||
| 269 | #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* RTC */ | |
| 270 | #define CONFIG_SYS_I2C_EEPROM_CPU_ADDR 0x52 /* EEPROM (CPU Modul) */ | |
| 271 | #define CONFIG_SYS_I2C_EEPROM_MB_ADDR 0x53 /* EEPROM AT24C128 (MainBoard) */ | |
| 272 | #define CONFIG_SYS_I2C_DSPIC_ADDR 0x54 /* dsPIC */ | |
| 273 | #define CONFIG_SYS_I2C_DSPIC_2_ADDR 0x55 /* dsPIC */ | |
| 274 | #define CONFIG_SYS_I2C_DSPIC_KEYB_ADDR 0x56 /* dsPIC */ | |
| 275 | #define CONFIG_SYS_I2C_DSPIC_IO_ADDR 0x57 /* dsPIC */ | |
| 276 | ||
| 277 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ | |
| 278 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel AT24C128 has */ | |
| 279 | /* 64 byte page write mode using*/ | |
| 280 | /* last 6 bits of the address */ | |
| 281 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ | |
| 282 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE | |
| 283 | ||
| 284 | #define CONFIG_RTC_PCF8563 /* enable Philips PCF8563 RTC */ | |
| 285 | #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */ | |
| 286 | #define CONFIG_SYS_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */ | |
| 287 | #define CONFIG_SYS_I2C_DSPIC_IO_ADDR 0x57 /* PIC I/O addr */ | |
| 288 | ||
| 289 | #define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_RTC_ADDR, \ | |
| 290 | CONFIG_SYS_I2C_EEPROM_CPU_ADDR,\ | |
| 291 | CONFIG_SYS_I2C_EEPROM_MB_ADDR, \ | |
| 292 | CONFIG_SYS_I2C_DSPIC_ADDR, \ | |
| 293 | CONFIG_SYS_I2C_DSPIC_2_ADDR, \ | |
| 294 | CONFIG_SYS_I2C_DSPIC_KEYB_ADDR,\ | |
| 295 | CONFIG_SYS_I2C_DSPIC_IO_ADDR } | |
| 296 | ||
| 04386f65 SR |
297 | /* Update size in "reg" property of NOR FLASH device tree nodes */ |
| 298 | #define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE | |
| 299 | ||
| 04386f65 SR |
300 | #define CONFIG_POST_KEY_MAGIC "3C+3E" /* press F3 + F5 keys to force POST */ |
| 301 | ||
| 302 | #define CONFIG_PREBOOT "setenv bootdelay 15" | |
| 303 | ||
| 304 | #undef CONFIG_BOOTARGS | |
| 305 | ||
| 306 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 307 | "hostname=lwmon5\0" \ | |
| 308 | "netdev=eth0\0" \ | |
| 309 | "unlock=yes\0" \ | |
| 310 | "logversion=2\0" \ | |
| 311 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
| 312 | "nfsroot=${serverip}:${rootpath}\0" \ | |
| 313 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
| 314 | "addip=setenv bootargs ${bootargs} " \ | |
| 315 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
| 316 | ":${hostname}:${netdev}:off panic=1\0" \ | |
| 317 | "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\ | |
| 318 | "addmisc=setenv bootargs ${bootargs} rtc-pcf8563.probe=0,0x51\0"\ | |
| 319 | "flash_nfs=run nfsargs addip addtty addmisc;" \ | |
| 320 | "bootm ${kernel_addr}\0" \ | |
| 321 | "flash_self=run ramargs addip addtty addmisc;" \ | |
| 322 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ | |
| 323 | "net_nfs=tftp 200000 ${bootfile};" \ | |
| 324 | "run nfsargs addip addtty addmisc;bootm\0" \ | |
| 325 | "rootpath=/opt/eldk/ppc_4xxFP\0" \ | |
| 326 | "bootfile=/tftpboot/lwmon5/uImage\0" \ | |
| 327 | "kernel_addr=FC000000\0" \ | |
| 328 | "ramdisk_addr=FC180000\0" \ | |
| 329 | "load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \ | |
| 330 | "update=protect off FFF80000 FFFFFFFF;era FFF80000 FFFFFFFF;" \ | |
| 331 | "cp.b 200000 FFF80000 80000\0" \ | |
| 332 | "upd=run load update\0" \ | |
| 333 | "lwe_env=tftp 200000 /tftpboot.dev/lwmon5/env_uboot.bin;" \ | |
| 334 | "autoscr 200000\0" \ | |
| 335 | "" | |
| 336 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
| 337 | ||
| 04386f65 SR |
338 | |
| 339 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
| 340 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
| 341 | ||
| 342 | #define CONFIG_PPC4xx_EMAC | |
| 343 | #define CONFIG_IBM_EMAC4_V4 1 | |
| 344 | #define CONFIG_MII 1 /* MII PHY management */ | |
| 345 | #define CONFIG_PHY_ADDR 3 /* PHY address, See schematics */ | |
| 346 | ||
| 347 | #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ | |
| 348 | #define CONFIG_PHY_RESET_DELAY 300 | |
| 349 | ||
| 350 | #define CONFIG_HAS_ETH0 | |
| 351 | #define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ | |
| 352 | ||
| 353 | #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ | |
| 354 | #define CONFIG_PHY1_ADDR 1 | |
| 355 | ||
| 356 | /* Video console */ | |
| 04386f65 SR |
357 | #define CONFIG_VIDEO_MB862xx |
| 358 | #define CONFIG_VIDEO_MB862xx_ACCEL | |
| 359 | #define CONFIG_CFB_CONSOLE | |
| 360 | #define CONFIG_VIDEO_LOGO | |
| 361 | #define CONFIG_CONSOLE_EXTRA_INFO | |
| 362 | #define VIDEO_FB_16BPP_PIXEL_SWAP | |
| 363 | #define VIDEO_FB_16BPP_WORD_SWAP | |
| 364 | ||
| 365 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
| 366 | #define CONFIG_VIDEO_SW_CURSOR | |
| 367 | #define CONFIG_SPLASH_SCREEN | |
| 368 | ||
| 04386f65 SR |
369 | /* |
| 370 | * USB/EHCI | |
| 371 | */ | |
| 372 | #define CONFIG_USB_EHCI /* Enable EHCI USB support */ | |
| 373 | #define CONFIG_USB_EHCI_PPC4XX /* on PPC4xx platform */ | |
| 374 | #define CONFIG_SYS_PPC4XX_USB_ADDR 0xe0000300 | |
| 375 | #define CONFIG_EHCI_MMIO_BIG_ENDIAN | |
| 376 | #define CONFIG_EHCI_DESC_BIG_ENDIAN | |
| 377 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* re-init HCD after CMD_RESET */ | |
| 04386f65 SR |
378 | |
| 379 | /* Partitions */ | |
| 380 | #define CONFIG_MAC_PARTITION | |
| 381 | #define CONFIG_DOS_PARTITION | |
| 382 | #define CONFIG_ISO_PARTITION | |
| 04386f65 SR |
383 | |
| 384 | /* | |
| 385 | * BOOTP options | |
| 386 | */ | |
| 387 | #define CONFIG_BOOTP_BOOTFILESIZE | |
| 388 | #define CONFIG_BOOTP_BOOTPATH | |
| 389 | #define CONFIG_BOOTP_GATEWAY | |
| 390 | #define CONFIG_BOOTP_HOSTNAME | |
| 391 | ||
| 392 | /* | |
| 393 | * Command line configuration. | |
| 394 | */ | |
| 04386f65 | 395 | #define CONFIG_CMD_DATE |
| 04386f65 SR |
396 | #define CONFIG_CMD_DIAG |
| 397 | #define CONFIG_CMD_EEPROM | |
| 04386f65 | 398 | #define CONFIG_CMD_IRQ |
| 04386f65 SR |
399 | #define CONFIG_CMD_REGINFO |
| 400 | #define CONFIG_CMD_SDRAM | |
| 401 | ||
| 402 | #ifdef CONFIG_VIDEO | |
| 403 | #define CONFIG_CMD_BMP | |
| 404 | #endif | |
| 405 | ||
| 04386f65 | 406 | #ifdef CONFIG_440EPX |
| 04386f65 | 407 | #endif |
| 04386f65 SR |
408 | |
| 409 | /* | |
| 410 | * Miscellaneous configurable options | |
| 411 | */ | |
| 412 | #define CONFIG_SUPPORT_VFAT | |
| 413 | ||
| 414 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
| 415 | ||
| 04386f65 SR |
416 | #if defined(CONFIG_CMD_KGDB) |
| 417 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
| 418 | #else | |
| 419 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
| 420 | #endif | |
| 421 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
| 422 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
| 423 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
| 424 | ||
| 425 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ | |
| 426 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
| 427 | ||
| 428 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ | |
| 429 | #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ | |
| 430 | ||
| 431 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ | |
| 04386f65 | 432 | #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ |
| 04386f65 SR |
433 | |
| 434 | #define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup*/ | |
| 435 | ||
| 04386f65 SR |
436 | #ifndef DEBUG |
| 437 | #define CONFIG_HW_WATCHDOG 1 /* Use external HW-Watchdog */ | |
| 438 | #endif | |
| 439 | #define CONFIG_WD_PERIOD 40000 /* in usec */ | |
| 440 | #define CONFIG_WD_MAX_RATE 66600 /* in ticks */ | |
| 04386f65 SR |
441 | |
| 442 | /* | |
| 443 | * For booting Linux, the board info and command line data | |
| 444 | * have to be in the first 16 MB of memory, since this is | |
| 445 | * the maximum mapped by the 40x Linux kernel during initialization. | |
| 446 | */ | |
| 447 | #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux */ | |
| 448 | #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ | |
| 449 | ||
| 450 | /* | |
| 451 | * External Bus Controller (EBC) Setup | |
| 452 | */ | |
| 453 | #define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE | |
| 454 | ||
| 455 | /* Memory Bank 0 (NOR-FLASH) initialization */ | |
| 456 | #define CONFIG_SYS_EBC_PB0AP 0x03000280 | |
| 457 | #define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH | 0xfc000) | |
| 458 | ||
| 459 | /* Memory Bank 1 (Lime) initialization */ | |
| 460 | #define CONFIG_SYS_EBC_PB1AP 0x01004380 | |
| 461 | #define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_LIME_BASE_0 | 0xbc000) | |
| 462 | ||
| 463 | /* Memory Bank 2 (FPGA) initialization */ | |
| 464 | #define CONFIG_SYS_EBC_PB2AP 0x01004400 | |
| 465 | #define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FPGA_BASE_0 | 0x1c000) | |
| 466 | ||
| 467 | /* Memory Bank 3 (FPGA2) initialization */ | |
| 468 | #define CONFIG_SYS_EBC_PB3AP 0x01004400 | |
| 469 | #define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_FPGA_BASE_1 | 0x1c000) | |
| 470 | ||
| 471 | #define CONFIG_SYS_EBC_CFG 0xb8400000 | |
| 472 | ||
| 473 | /* | |
| 474 | * Graphics (Fujitsu Lime) | |
| 475 | */ | |
| 476 | /* SDRAM Clock frequency adjustment register */ | |
| 477 | #define CONFIG_SYS_LIME_SDRAM_CLOCK 0xC1FC0038 | |
| 478 | #if 1 /* 133MHz is not tested enough, use 100MHz for now */ | |
| 479 | /* Lime Clock frequency is to set 100MHz */ | |
| 480 | #define CONFIG_SYS_LIME_CLOCK_100MHZ 0x00000 | |
| 481 | #else | |
| 482 | /* Lime Clock frequency for 133MHz */ | |
| 483 | #define CONFIG_SYS_LIME_CLOCK_133MHZ 0x10000 | |
| 484 | #endif | |
| 485 | ||
| 486 | /* SDRAM Parameter register */ | |
| 487 | #define CONFIG_SYS_LIME_MMR 0xC1FCFFFC | |
| 488 | /* | |
| 489 | * SDRAM parameter value; was 0x414FB7F2, caused several vertical bars | |
| 490 | * and pixel flare on display when 133MHz was configured. According to | |
| 491 | * SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed | |
| 492 | * Grade | |
| 493 | */ | |
| 494 | #ifdef CONFIG_SYS_LIME_CLOCK_133MHZ | |
| 495 | #define CONFIG_SYS_MB862xx_MMR 0x414FB7F3 | |
| 496 | #define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_133MHZ | |
| 497 | #else | |
| 498 | #define CONFIG_SYS_MB862xx_MMR 0x414FB7F2 | |
| 499 | #define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_100MHZ | |
| 500 | #endif | |
| 501 | ||
| 502 | /* | |
| 503 | * GPIO Setup | |
| 504 | */ | |
| 505 | #define CONFIG_SYS_GPIO_PHY1_RST 12 | |
| 506 | #define CONFIG_SYS_GPIO_FLASH_WP 14 | |
| 507 | #define CONFIG_SYS_GPIO_PHY0_RST 22 | |
| 508 | #define CONFIG_SYS_GPIO_PERM_VOLT_FEED 49 | |
| 509 | #define CONFIG_SYS_GPIO_DSPIC_READY 51 | |
| 510 | #define CONFIG_SYS_GPIO_CAN_ENABLE 53 | |
| 511 | #define CONFIG_SYS_GPIO_LSB_ENABLE 54 | |
| 512 | #define CONFIG_SYS_GPIO_EEPROM_EXT_WP 55 | |
| 513 | #define CONFIG_SYS_GPIO_HIGHSIDE 56 | |
| 514 | #define CONFIG_SYS_GPIO_EEPROM_INT_WP 57 | |
| 515 | #define CONFIG_SYS_GPIO_BOARD_RESET 58 | |
| 516 | #define CONFIG_SYS_GPIO_LIME_S 59 | |
| 517 | #define CONFIG_SYS_GPIO_LIME_RST 60 | |
| 518 | #define CONFIG_SYS_GPIO_SYSMON_STATUS 62 | |
| 519 | #define CONFIG_SYS_GPIO_WATCHDOG 63 | |
| 520 | ||
| 04386f65 | 521 | #define GPIO49_VAL 1 |
| 04386f65 SR |
522 | |
| 523 | /* | |
| 524 | * PPC440 GPIO Configuration | |
| 525 | */ | |
| 526 | #define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \ | |
| 527 | { \ | |
| 528 | /* GPIO Core 0 */ \ | |
| 529 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \ | |
| 530 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \ | |
| 531 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \ | |
| 532 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \ | |
| 533 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \ | |
| 534 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \ | |
| 535 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1) */ \ | |
| 536 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2) */ \ | |
| 537 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3) */ \ | |
| 538 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4) */ \ | |
| 539 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5) */ \ | |
| 540 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR */ \ | |
| 541 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \ | |
| 542 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \ | |
| 543 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14 */ \ | |
| 544 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO15 */ \ | |
| 545 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMCTxD(4) */ \ | |
| 546 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMCTxD(5) */ \ | |
| 547 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMCTxD(6) */ \ | |
| 548 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMCTxD(7) */ \ | |
| 549 | {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 RejectPkt0 */ \ | |
| 550 | {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 RejectPkt1 */ \ | |
| 551 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO22 */ \ | |
| 552 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 SCPD0 */ \ | |
| 553 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 GMCTxD(2) */ \ | |
| 554 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 GMCTxD(3) */ \ | |
| 555 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26 */ \ | |
| 556 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \ | |
| 557 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO28 USB2D_TXVALID */ \ | |
| 558 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \ | |
| 559 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \ | |
| 560 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \ | |
| 561 | }, \ | |
| 562 | { \ | |
| 563 | /* GPIO Core 1 */ \ | |
| 564 | {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO32 USB2D_OPMODE0 EBC_DATA(2) */ \ | |
| 565 | {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO33 USB2D_OPMODE1 EBC_DATA(3) */ \ | |
| 566 | {GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_0}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \ | |
| 567 | {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \ | |
| 568 | {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0) UART3_SIN*/ \ | |
| 569 | {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EBC_DATA(1) UART3_SOUT*/ \ | |
| 570 | {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \ | |
| 571 | {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \ | |
| 572 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0) */ \ | |
| 573 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1) */ \ | |
| 574 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2) */ \ | |
| 575 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3) */ \ | |
| 576 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \ | |
| 577 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \ | |
| 578 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \ | |
| 579 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \ | |
| 580 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \ | |
| 581 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO49_VAL}, /* GPIO49 Unselect via TraceSelect Bit */ \ | |
| 582 | {GPIO1_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \ | |
| 583 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \ | |
| 584 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \ | |
| 585 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \ | |
| 586 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \ | |
| 587 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55 Unselect via TraceSelect Bit */ \ | |
| 588 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \ | |
| 589 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO57 Unselect via TraceSelect Bit */ \ | |
| 590 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \ | |
| 591 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \ | |
| 592 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \ | |
| 593 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \ | |
| 594 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \ | |
| 595 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \ | |
| 596 | } \ | |
| 597 | } | |
| 598 | ||
| 599 | #if defined(CONFIG_CMD_KGDB) | |
| 600 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
| 601 | #endif | |
| 602 | ||
| 04386f65 | 603 | #endif /* __CONFIG_H */ |