projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| b765ffb7 SR |
1 | /* |
| 2 | * (C) Copyright 2007 | |
| 3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
| 4 | * | |
| 5 | * This program is free software; you can redistribute it and/or | |
| 6 | * modify it under the terms of the GNU General Public License as | |
| 7 | * published by the Free Software Foundation; either version 2 of | |
| 8 | * the License, or (at your option) any later version. | |
| 9 | * | |
| 10 | * This program is distributed in the hope that it will be useful, | |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 13 | * GNU General Public License for more details. | |
| 14 | * | |
| 15 | * You should have received a copy of the GNU General Public License | |
| 16 | * along with this program; if not, write to the Free Software | |
| 17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 18 | * MA 02111-1307 USA | |
| 19 | */ | |
| 20 | ||
| 21 | /************************************************************************ | |
| 22 | * lwmon5.h - configuration for lwmon5 board | |
| 23 | ***********************************************************************/ | |
| 24 | #ifndef __CONFIG_H | |
| 25 | #define __CONFIG_H | |
| 26 | ||
| 27 | /*----------------------------------------------------------------------- | |
| 28 | * High Level Configuration Options | |
| 29 | *----------------------------------------------------------------------*/ | |
| 30 | #define CONFIG_LWMON5 1 /* Board is lwmon5 */ | |
| 31 | #define CONFIG_440EPX 1 /* Specific PPC440EPx */ | |
| e73846b7 | 32 | #define CONFIG_440 1 /* ... PPC440 family */ |
| b765ffb7 SR |
33 | #define CONFIG_4xx 1 /* ... PPC4xx family */ |
| 34 | #define CONFIG_SYS_CLK_FREQ 33300000 /* external freq to pll */ | |
| 35 | ||
| 36 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ | |
| 3ad63878 | 37 | #define CONFIG_BOARD_POSTCLK_INIT 1 /* Call board_postclk_init */ |
| b765ffb7 | 38 | #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ |
| b765ffb7 SR |
39 | |
| 40 | /*----------------------------------------------------------------------- | |
| 41 | * Base addresses -- Note these are effective addresses where the | |
| 42 | * actual resources get mapped (not physical addresses) | |
| 43 | *----------------------------------------------------------------------*/ | |
| 44 | #define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */ | |
| 45 | #define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc() */ | |
| 46 | ||
| 47 | #define CFG_BOOT_BASE_ADDR 0xf0000000 | |
| 48 | #define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ | |
| 9f24a808 | 49 | #define CFG_FLASH_BASE 0xf8000000 /* start of FLASH */ |
| b765ffb7 SR |
50 | #define CFG_MONITOR_BASE TEXT_BASE |
| 51 | #define CFG_LIME_BASE_0 0xc0000000 | |
| 52 | #define CFG_LIME_BASE_1 0xc1000000 | |
| 53 | #define CFG_LIME_BASE_2 0xc2000000 | |
| 54 | #define CFG_LIME_BASE_3 0xc3000000 | |
| 55 | #define CFG_FPGA_BASE_0 0xc4000000 | |
| 56 | #define CFG_FPGA_BASE_1 0xc4200000 | |
| 57 | #define CFG_OCM_BASE 0xe0010000 /* ocm */ | |
| 58 | #define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */ | |
| 59 | #define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ | |
| 60 | #define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000 | |
| 61 | #define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000 | |
| 62 | #define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000 | |
| 63 | ||
| 64 | /* Don't change either of these */ | |
| 65 | #define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */ | |
| 66 | ||
| 67 | #define CFG_USB2D0_BASE 0xe0000100 | |
| 68 | #define CFG_USB_DEVICE 0xe0000000 | |
| 69 | #define CFG_USB_HOST 0xe0000400 | |
| 70 | ||
| 71 | /*----------------------------------------------------------------------- | |
| 72 | * Initial RAM & stack pointer | |
| 73 | *----------------------------------------------------------------------*/ | |
| 74 | /* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */ | |
| b765ffb7 | 75 | #define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */ |
| 531e3e8b | 76 | #define CFG_OCM_DATA_ADDR CFG_OCM_BASE |
| b765ffb7 SR |
77 | |
| 78 | #define CFG_INIT_RAM_END (4 << 10) | |
| 79 | #define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ | |
| 80 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
| 531e3e8b PK |
81 | #define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) |
| 82 | #define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR | |
| b765ffb7 SR |
83 | |
| 84 | /*----------------------------------------------------------------------- | |
| 85 | * Serial Port | |
| 86 | *----------------------------------------------------------------------*/ | |
| 87 | #undef CFG_EXT_SERIAL_CLOCK /* no external clock provided */ | |
| 88 | #define CONFIG_BAUDRATE 115200 | |
| 89 | #define CONFIG_SERIAL_MULTI 1 | |
| 90 | /* define this if you want console on UART1 */ | |
| 91 | #define CONFIG_UART1_CONSOLE 1 /* use UART1 as console */ | |
| 92 | ||
| 93 | #define CFG_BAUDRATE_TABLE \ | |
| 94 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} | |
| 95 | ||
| 96 | /*----------------------------------------------------------------------- | |
| 97 | * Environment | |
| 98 | *----------------------------------------------------------------------*/ | |
| 99 | #define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ | |
| 100 | ||
| 101 | /*----------------------------------------------------------------------- | |
| 102 | * FLASH related | |
| 103 | *----------------------------------------------------------------------*/ | |
| 104 | #define CFG_FLASH_CFI /* The flash is CFI compatible */ | |
| 105 | #define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ | |
| 106 | ||
| 9f24a808 SR |
107 | #define CFG_FLASH0 0xFC000000 |
| 108 | #define CFG_FLASH1 0xF8000000 | |
| 109 | #define CFG_FLASH_BANKS_LIST { CFG_FLASH1, CFG_FLASH0 } | |
| b765ffb7 | 110 | |
| 9f24a808 | 111 | #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
| b765ffb7 SR |
112 | #define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ |
| 113 | ||
| 114 | #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ | |
| 115 | #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
| 116 | ||
| 117 | #define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ | |
| 118 | #define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */ | |
| 119 | ||
| 120 | #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ | |
| 121 | #define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ | |
| 122 | ||
| 1636d1c8 | 123 | #define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */ |
| b765ffb7 SR |
124 | #define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE) |
| 125 | #define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ | |
| 126 | ||
| 127 | /* Address and size of Redundant Environment Sector */ | |
| 128 | #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) | |
| 129 | #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) | |
| 130 | ||
| 131 | /*----------------------------------------------------------------------- | |
| 132 | * DDR SDRAM | |
| 133 | *----------------------------------------------------------------------*/ | |
| 134 | #define CFG_MBYTES_SDRAM (256) /* 256MB */ | |
| 135 | #define CFG_DDR_CACHED_ADDR 0x40000000 /* setup 2nd TLB cached here */ | |
| 136 | #define CONFIG_DDR_DATA_EYE 1 /* use DDR2 optimization */ | |
| 137 | #if 0 /* test-only: disable ECC for now */ | |
| 138 | #define CONFIG_DDR_ECC 1 /* enable ECC */ | |
| 3e4c90c6 SR |
139 | #define CFG_POST_ECC_ON CFG_POST_ECC |
| 140 | #else | |
| 141 | #define CFG_POST_ECC_ON 0 | |
| 142 | #endif | |
| 531e3e8b PK |
143 | |
| 144 | /* POST support */ | |
| 75e1a84d | 145 | #define CONFIG_POST (CFG_POST_CACHE | \ |
| 3e4c90c6 | 146 | CFG_POST_CPU | \ |
| 75e1a84d | 147 | CFG_POST_ECC_ON | \ |
| 3e4c90c6 | 148 | CFG_POST_ETHER | \ |
| 75e1a84d SR |
149 | CFG_POST_FPU | \ |
| 150 | CFG_POST_I2C | \ | |
| 151 | CFG_POST_MEMORY | \ | |
| 152 | CFG_POST_RTC | \ | |
| 153 | CFG_POST_SPR | \ | |
| 154 | CFG_POST_UART) | |
| 3e4c90c6 SR |
155 | |
| 156 | #define CFG_POST_CACHE_ADDR 0x10000000 /* free virtual address */ | |
| 157 | #define CONFIG_LOGBUFFER | |
| 158 | #define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ | |
| b765ffb7 SR |
159 | |
| 160 | /*----------------------------------------------------------------------- | |
| 161 | * I2C | |
| 162 | *----------------------------------------------------------------------*/ | |
| 163 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ | |
| 164 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
| c25dd8fc | 165 | #define CFG_I2C_SPEED 100000 /* I2C speed and slave address */ |
| b765ffb7 SR |
166 | #define CFG_I2C_SLAVE 0x7F |
| 167 | ||
| c25dd8fc SR |
168 | #define CFG_I2C_EEPROM_ADDR 0x53 /* EEPROM AT24C128 */ |
| 169 | #define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ | |
| 170 | #define CFG_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel AT24C128 has */ | |
| 171 | /* 64 byte page write mode using*/ | |
| 172 | /* last 6 bits of the address */ | |
| 173 | #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ | |
| b765ffb7 | 174 | #define CFG_EEPROM_PAGE_WRITE_ENABLE |
| b765ffb7 SR |
175 | |
| 176 | #define CONFIG_RTC_PCF8563 1 /* enable Philips PCF8563 RTC */ | |
| 177 | #define CFG_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */ | |
| 3ad63878 | 178 | #define CFG_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */ |
| b765ffb7 | 179 | |
| 3ad63878 SR |
180 | #define CONFIG_POST_KEY_MAGIC "3C+3E" /* press F3 + F5 keys to force POST */ |
| 181 | #if 0 | |
| 182 | #define CONFIG_AUTOBOOT_KEYED /* Enable "password" protection */ | |
| 183 | #define CONFIG_AUTOBOOT_PROMPT "\nEnter password - autoboot in %d sec...\n" | |
| 184 | #define CONFIG_AUTOBOOT_DELAY_STR " " /* "password" */ | |
| 185 | #endif | |
| 186 | ||
| 187 | #define CONFIG_PREBOOT "setenv bootdelay 15" | |
| b765ffb7 SR |
188 | |
| 189 | #undef CONFIG_BOOTARGS | |
| 190 | ||
| 191 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 192 | "hostname=lwmon5\0" \ | |
| 193 | "netdev=eth0\0" \ | |
| 5d187430 | 194 | "unlock=yes\0" \ |
| 3e4c90c6 | 195 | "logversion=2\0" \ |
| b765ffb7 SR |
196 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
| 197 | "nfsroot=${serverip}:${rootpath}\0" \ | |
| 198 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
| 199 | "addip=setenv bootargs ${bootargs} " \ | |
| 200 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
| 201 | ":${hostname}:${netdev}:off panic=1\0" \ | |
| 202 | "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\ | |
| 203 | "flash_nfs=run nfsargs addip addtty;" \ | |
| 204 | "bootm ${kernel_addr}\0" \ | |
| 205 | "flash_self=run ramargs addip addtty;" \ | |
| 206 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ | |
| 207 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ | |
| 208 | "bootm\0" \ | |
| 209 | "rootpath=/opt/eldk/ppc_4xxFP\0" \ | |
| 210 | "bootfile=/tftpboot/lwmon5/uImage\0" \ | |
| 211 | "kernel_addr=FC000000\0" \ | |
| 212 | "ramdisk_addr=FC180000\0" \ | |
| 213 | "load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \ | |
| 214 | "update=protect off FFF80000 FFFFFFFF;era FFF80000 FFFFFFFF;" \ | |
| 215 | "cp.b 200000 FFF80000 80000\0" \ | |
| 216 | "upd=run load;run update\0" \ | |
| 334043f6 SR |
217 | "lwe_env=tftp 200000 /tftpboot.dev/lwmon5/env_uboot.bin;" \ |
| 218 | "autoscr 200000\0" \ | |
| b765ffb7 SR |
219 | "" |
| 220 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
| 221 | ||
| 222 | #if 0 | |
| 223 | #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ | |
| 224 | #else | |
| 225 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
| 226 | #endif | |
| 227 | ||
| 228 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
| 229 | #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
| 230 | ||
| 231 | #define CONFIG_IBM_EMAC4_V4 1 | |
| 232 | #define CONFIG_MII 1 /* MII PHY management */ | |
| 233 | #define CONFIG_PHY_ADDR 3 /* PHY address, See schematics */ | |
| 234 | ||
| 235 | #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ | |
| 3ad63878 | 236 | #define CONFIG_PHY_RESET_DELAY 300 |
| b765ffb7 SR |
237 | |
| 238 | #define CONFIG_HAS_ETH0 | |
| 239 | #define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ | |
| 240 | ||
| 241 | #define CONFIG_NET_MULTI 1 | |
| 242 | #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ | |
| 243 | #define CONFIG_PHY1_ADDR 1 | |
| 244 | ||
| 245 | /* USB */ | |
| 246 | #ifdef CONFIG_440EPX | |
| 247 | #define CONFIG_USB_OHCI | |
| 248 | #define CONFIG_USB_STORAGE | |
| 249 | ||
| 250 | /* Comment this out to enable USB 1.1 device */ | |
| 251 | #define USB_2_0_DEVICE | |
| 252 | ||
| b765ffb7 SR |
253 | #endif /* CONFIG_440EPX */ |
| 254 | ||
| 255 | /* Partitions */ | |
| 256 | #define CONFIG_MAC_PARTITION | |
| 257 | #define CONFIG_DOS_PARTITION | |
| 258 | #define CONFIG_ISO_PARTITION | |
| 259 | ||
| 079a136c JL |
260 | /* |
| 261 | * BOOTP options | |
| 262 | */ | |
| 263 | #define CONFIG_BOOTP_BOOTFILESIZE | |
| 264 | #define CONFIG_BOOTP_BOOTPATH | |
| 265 | #define CONFIG_BOOTP_GATEWAY | |
| 266 | #define CONFIG_BOOTP_HOSTNAME | |
| b765ffb7 | 267 | |
| a22d4da9 JL |
268 | /* |
| 269 | * Command line configuration. | |
| 270 | */ | |
| 271 | #include <config_cmd_default.h> | |
| 272 | ||
| 273 | #define CONFIG_CMD_ASKENV | |
| 274 | #define CONFIG_CMD_DATE | |
| 275 | #define CONFIG_CMD_DHCP | |
| 276 | #define CONFIG_CMD_DIAG | |
| 277 | #define CONFIG_CMD_EEPROM | |
| 278 | #define CONFIG_CMD_ELF | |
| 279 | #define CONFIG_CMD_FAT | |
| 280 | #define CONFIG_CMD_I2C | |
| 281 | #define CONFIG_CMD_IRQ | |
| 3b3bff4c | 282 | #define CONFIG_CMD_LOG |
| a22d4da9 JL |
283 | #define CONFIG_CMD_MII |
| 284 | #define CONFIG_CMD_NET | |
| 285 | #define CONFIG_CMD_NFS | |
| 286 | #define CONFIG_CMD_PCI | |
| 287 | #define CONFIG_CMD_PING | |
| 288 | #define CONFIG_CMD_REGINFO | |
| 289 | #define CONFIG_CMD_SDRAM | |
| b765ffb7 | 290 | |
| a22d4da9 JL |
291 | #ifdef CONFIG_440EPX |
| 292 | #define CONFIG_CMD_USB | |
| 293 | #endif | |
| b765ffb7 SR |
294 | |
| 295 | /*----------------------------------------------------------------------- | |
| 296 | * Miscellaneous configurable options | |
| 297 | *----------------------------------------------------------------------*/ | |
| a22d4da9 JL |
298 | #define CONFIG_SUPPORT_VFAT |
| 299 | ||
| b765ffb7 SR |
300 | #define CFG_LONGHELP /* undef to save memory */ |
| 301 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
| a22d4da9 | 302 | #if defined(CONFIG_CMD_KGDB) |
| b765ffb7 SR |
303 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
| 304 | #else | |
| 305 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
| 306 | #endif | |
| 307 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
| 308 | #define CFG_MAXARGS 16 /* max number of command args */ | |
| 309 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
| 310 | ||
| 311 | #define CFG_MEMTEST_START 0x0400000 /* memtest works on */ | |
| 312 | #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
| 313 | ||
| 314 | #define CFG_LOAD_ADDR 0x100000 /* default load address */ | |
| 315 | #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ | |
| 316 | ||
| 317 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
| 318 | ||
| 319 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ | |
| 320 | #define CONFIG_LOOPW 1 /* enable loopw command */ | |
| 321 | #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ | |
| 322 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ | |
| 323 | #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ | |
| 324 | ||
| 325 | /*----------------------------------------------------------------------- | |
| 326 | * PCI stuff | |
| 327 | *----------------------------------------------------------------------*/ | |
| 328 | /* General PCI */ | |
| 329 | #define CONFIG_PCI /* include pci support */ | |
| 330 | #undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ | |
| 331 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
| 332 | #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/ | |
| 333 | ||
| 334 | /* Board-specific PCI */ | |
| b765ffb7 SR |
335 | #define CFG_PCI_TARGET_INIT |
| 336 | #define CFG_PCI_MASTER_INIT | |
| 337 | ||
| 338 | #define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ | |
| 339 | #define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */ | |
| 340 | ||
| 341 | #define CONFIG_HW_WATCHDOG 1 /* Use external HW-Watchdog */ | |
| 342 | ||
| 343 | /* | |
| 344 | * For booting Linux, the board info and command line data | |
| 345 | * have to be in the first 8 MB of memory, since this is | |
| 346 | * the maximum mapped by the Linux kernel during initialization. | |
| 347 | */ | |
| 348 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
| 349 | ||
| 350 | /*----------------------------------------------------------------------- | |
| 351 | * External Bus Controller (EBC) Setup | |
| 352 | *----------------------------------------------------------------------*/ | |
| 353 | #define CFG_FLASH CFG_FLASH_BASE | |
| 354 | ||
| 355 | /* Memory Bank 0 (NOR-FLASH) initialization */ | |
| 356 | #define CFG_EBC_PB0AP 0x03050200 | |
| 9f24a808 | 357 | #define CFG_EBC_PB0CR (CFG_FLASH | 0xfc000) |
| b765ffb7 SR |
358 | |
| 359 | /* Memory Bank 1 (Lime) initialization */ | |
| 360 | #define CFG_EBC_PB1AP 0x01004380 | |
| 361 | #define CFG_EBC_PB1CR (CFG_LIME_BASE_0 | 0xdc000) | |
| 362 | ||
| 363 | /* Memory Bank 2 (FPGA) initialization */ | |
| 364 | #define CFG_EBC_PB2AP 0x01004400 | |
| 365 | #define CFG_EBC_PB2CR (CFG_FPGA_BASE_0 | 0x1c000) | |
| 366 | ||
| 367 | /* Memory Bank 3 (FPGA2) initialization */ | |
| 368 | #define CFG_EBC_PB3AP 0x01004400 | |
| 369 | #define CFG_EBC_PB3CR (CFG_FPGA_BASE_1 | 0x1c000) | |
| 370 | ||
| 371 | #define CFG_EBC_CFG 0xb8400000 | |
| 372 | ||
| 04e6c38b SR |
373 | /*----------------------------------------------------------------------- |
| 374 | * Graphics (Fujitsu Lime) | |
| 375 | *----------------------------------------------------------------------*/ | |
| 376 | /* SDRAM Clock frequency adjustment register */ | |
| b66091de AG |
377 | #define CFG_LIME_SDRAM_CLOCK 0xC1FC0038 |
| 378 | /* Lime Clock frequency is to set 100MHz */ | |
| 379 | #define CFG_LIME_CLOCK_100MHZ 0x00000 | |
| 380 | #if 0 | |
| 381 | /* Lime Clock frequency for 133MHz */ | |
| 04e6c38b | 382 | #define CFG_LIME_CLOCK_133MHZ 0x10000 |
| b66091de | 383 | #endif |
| 04e6c38b SR |
384 | |
| 385 | /* SDRAM Parameter register */ | |
| 386 | #define CFG_LIME_MMR 0xC1FCFFFC | |
| b66091de AG |
387 | /* SDRAM parameter value; was 0x414FB7F2, caused several vertical bars |
| 388 | and pixel flare on display when 133MHz was configured. According to | |
| 389 | SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed Grade */ | |
| 390 | #ifdef CFG_LIME_CLOCK_133MHZ | |
| 391 | #define CFG_LIME_MMR_VALUE 0x414FB7F3 | |
| 392 | #else | |
| 04e6c38b | 393 | #define CFG_LIME_MMR_VALUE 0x414FB7F2 |
| b66091de | 394 | #endif |
| 04e6c38b | 395 | |
| b765ffb7 SR |
396 | /*----------------------------------------------------------------------- |
| 397 | * GPIO Setup | |
| 398 | *----------------------------------------------------------------------*/ | |
| 399 | #define CFG_GPIO_PHY1_RST 12 | |
| 400 | #define CFG_GPIO_FLASH_WP 14 | |
| 401 | #define CFG_GPIO_PHY0_RST 22 | |
| c25dd8fc SR |
402 | #define CFG_GPIO_EEPROM_EXT_WP 55 |
| 403 | #define CFG_GPIO_EEPROM_INT_WP 57 | |
| b765ffb7 SR |
404 | #define CFG_GPIO_LIME_S 59 |
| 405 | #define CFG_GPIO_LIME_RST 60 | |
| d7bfa620 | 406 | #define CFG_GPIO_WATCHDOG 63 |
| b765ffb7 SR |
407 | |
| 408 | /*----------------------------------------------------------------------- | |
| 409 | * PPC440 GPIO Configuration | |
| 410 | */ | |
| 411 | #define CFG_440_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \ | |
| 412 | { \ | |
| 413 | /* GPIO Core 0 */ \ | |
| 414 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \ | |
| 415 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \ | |
| 416 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \ | |
| 417 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \ | |
| 418 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \ | |
| 419 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \ | |
| 420 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1) */ \ | |
| 421 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2) */ \ | |
| 422 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3) */ \ | |
| 423 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4) */ \ | |
| 424 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5) */ \ | |
| 425 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR */ \ | |
| 426 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \ | |
| 427 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \ | |
| 428 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14 */ \ | |
| 429 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO15 */ \ | |
| 1636d1c8 | 430 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMCTxD(4) */ \ |
| b765ffb7 SR |
431 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMCTxD(5) */ \ |
| 432 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMCTxD(6) */ \ | |
| 433 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMCTxD(7) */ \ | |
| 434 | {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 RejectPkt0 */ \ | |
| 435 | {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 RejectPkt1 */ \ | |
| 436 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO22 */ \ | |
| 437 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 SCPD0 */ \ | |
| 438 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 GMCTxD(2) */ \ | |
| 439 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 GMCTxD(3) */ \ | |
| 440 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26 */ \ | |
| 441 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \ | |
| 442 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO28 USB2D_TXVALID */ \ | |
| 443 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \ | |
| 444 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \ | |
| 445 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \ | |
| 446 | }, \ | |
| 447 | { \ | |
| 448 | /* GPIO Core 1 */ \ | |
| 449 | {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO32 USB2D_OPMODE0 EBC_DATA(2) */ \ | |
| 450 | {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO33 USB2D_OPMODE1 EBC_DATA(3) */ \ | |
| 451 | {GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_0}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \ | |
| 452 | {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \ | |
| 453 | {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0) UART3_SIN*/ \ | |
| 454 | {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EBC_DATA(1) UART3_SOUT*/ \ | |
| 455 | {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \ | |
| 456 | {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \ | |
| 457 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0) */ \ | |
| 458 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1) */ \ | |
| 459 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2) */ \ | |
| 460 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3) */ \ | |
| 461 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \ | |
| 462 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \ | |
| 463 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \ | |
| 464 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \ | |
| 465 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \ | |
| 466 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO49 Unselect via TraceSelect Bit */ \ | |
| 04e6c38b | 467 | {GPIO1_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \ |
| b765ffb7 SR |
468 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \ |
| 469 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \ | |
| 470 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO53 Unselect via TraceSelect Bit */ \ | |
| 471 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \ | |
| 472 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55 Unselect via TraceSelect Bit */ \ | |
| 473 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \ | |
| 474 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO57 Unselect via TraceSelect Bit */ \ | |
| 475 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO58 Unselect via TraceSelect Bit */ \ | |
| 476 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \ | |
| 477 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \ | |
| 478 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \ | |
| 479 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \ | |
| 480 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \ | |
| 481 | } \ | |
| 482 | } | |
| 483 | ||
| 484 | /*----------------------------------------------------------------------- | |
| 485 | * Cache Configuration | |
| 486 | *----------------------------------------------------------------------*/ | |
| 487 | #define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */ | |
| 488 | #define CFG_CACHELINE_SIZE 32 /* ... */ | |
| a22d4da9 | 489 | #if defined(CONFIG_CMD_KGDB) |
| b765ffb7 SR |
490 | #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
| 491 | #endif | |
| 492 | ||
| 493 | /* | |
| 494 | * Internal Definitions | |
| 495 | * | |
| 496 | * Boot Flags | |
| 497 | */ | |
| 498 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
| 499 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
| 500 | ||
| a22d4da9 | 501 | #if defined(CONFIG_CMD_KGDB) |
| b765ffb7 SR |
502 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
| 503 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
| 504 | #endif | |
| 505 | #endif /* __CONFIG_H */ |