[people/ms/u-boot.git] / include / configs / m501sk.h

/*
 * Based on Modifications by Alan Lu / Artila and
 * Rick Bronson <rick@efn.org>
 *
 * Configuration settings for the Artila M-501 starter kit,
 * with V02 processor card.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/* ARM asynchronous clock */
/* from 18.432 MHz crystal (18432000 / 4 * 39) */
#define AT91C_MAIN_CLOCK	179712000
/* Perip clock (AT91C_MASTER_CLOCK / 3) */
#define AT91C_MASTER_CLOCK	59904000
#define AT91_SLOW_CLOCK	32768 /* slow clock */

#define CONFIG_AT91RM9200DK	1 /* on an AT91RM9200DK Board    */
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
#define CONFIG_CMDLINE_TAG	1 /* enable passing of ATAGs    */
#define CONFIG_SETUP_MEMORY_TAGS	1
#define CONFIG_INITRD_TAG		1

#define CONFIG_MENUPROMPT		"."
/*
 * LowLevel Init
 */
#define CONFIG_SYS_USE_MAIN_OSCILLATOR		1
/* flash */
#define CONFIG_SYS_MC_PUIA_VAL	0x00000000
#define CONFIG_SYS_MC_PUP_VAL	0x00000000
#define CONFIG_SYS_MC_PUER_VAL	0x00000000
#define CONFIG_SYS_MC_ASR_VAL	0x00000000
#define CONFIG_SYS_MC_AASR_VAL	0x00000000
#define CONFIG_SYS_EBI_CFGR_VAL	0x00000000
#define CONFIG_SYS_SMC_CSR0_VAL	0x00003284 /* 16bit, 2 TDF, 4 WS */

/* clocks */
#define CONFIG_SYS_PLLAR_VAL	0x20263E04 /* 179.712000 MHz for PCK */
#define CONFIG_SYS_PLLBR_VAL	0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
/* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
#define CONFIG_SYS_MCKR_VAL	0x00000202

/* sdram */
#define CONFIG_SYS_PIOC_ASR_VAL	0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
#define CONFIG_SYS_PIOC_BSR_VAL	0x00000000
#define CONFIG_SYS_PIOC_PDR_VAL	0xFFFF0000
#define CONFIG_SYS_EBI_CSA_VAL	0x00000002 /* CS1=CONFIG_SYS_SDRAM */
#define CONFIG_SYS_SDRC_CR_VAL	0x2188c155 /* set up the CONFIG_SYS_SDRAM */
#define CONFIG_SYS_SDRAM	0x20000000 /* address of the CONFIG_SYS_SDRAM */
#define CONFIG_SYS_SDRAM1	0x20000080 /* address of the CONFIG_SYS_SDRAM */
#define CONFIG_SYS_SDRAM_VAL	0x00000000 /* value written to CONFIG_SYS_SDRAM */
#define CONFIG_SYS_SDRC_MR_VAL	0x00000002 /* Precharge All */
#define CONFIG_SYS_SDRC_MR_VAL1	0x00000004 /* refresh */
#define CONFIG_SYS_SDRC_MR_VAL2	0x00000003 /* Load Mode Register */
#define CONFIG_SYS_SDRC_MR_VAL3	0x00000000 /* Normal Mode */
#define CONFIG_SYS_SDRC_TR_VAL	0x000002E0 /* Write refresh rate */

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
#define CONFIG_SYS_GBL_DATA_SIZE	128	/* Bytes reserved for initial data */

#define CONFIG_BAUDRATE			115200

/* Hardcode so no __divsi3 : AT91C_MASTER_CLOCK / baudrate / 16 */
#define CONFIG_SYS_AT91C_BRGR_DIVISOR	33

/*
 * Hardware drivers
 */
#define CONFIG_SYS_FLASH_CFI		1
#define CONFIG_FLASH_CFI_DRIVER	1
#define CONFIG_ENV_SECT_SIZE	0x20000
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_FLASH_PROTECTION	/*for Intel P30 Flash*/
#define CONFIG_HARD_I2C
#define CONFIG_SYS_I2C_SPEED		100
#define CONFIG_SYS_I2C_SLAVE		0
#define CONFIG_SYS_CONSOLE_INFO_QUIET
#undef CONFIG_ENV_IS_IN_EEPROM
#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
#define CONFIG_SYS_EEPROM_AT24C16
#define CONFIG_SYS_I2C_RTC_ADDR		0x32
#undef CONFIG_RTC_DS1338
#define CONFIG_RTC_RS5C372A
#undef CONFIG_POST
#define CONFIG_M501SK
#define CONFIG_CMC_PU2

/* define one of these to choose the DBGU, USART0  or USART1 as console */
#define CONFIG_DBGU
#undef CONFIG_USART0
#undef CONFIG_USART1

#undef CONFIG_HWFLOW		/* don't include RTS/CTS flow control support */
#undef CONFIG_MODEM_SUPPORT	/* disable modem initialization stuff */

#define CONFIG_BOOTARGS	"mem=32M console=ttyS0,115200 "	\
			"initrd=0x20800000,8192000 ramdisk_size=15360 "	\
			"root=/dev/ram0 rw mtdparts=phys_mapped_flash:"	\
			"128k(loader)ro,128k(reserved)ro,1408k(linux)"	\
			"ro,2560k(ramdisk)ro,-(userdisk)"
#define CONFIG_BOOTCOMMAND	"bootm 10040000 101a0000"
#define CONFIG_BOOTDELAY	1
#define CONFIG_BAUDRATE	115200
#define CONFIG_IPADDR		192.168.1.100
#define CONFIG_SERVERIP	192.168.1.1
#define CONFIG_GATEWAYIP	192.168.1.254
#define CONFIG_NETMASK		255.255.255.0
#define CONFIG_BOOTFILE	uImage
#define CONFIG_ETHADDR		00:13:48:aa:bb:cc
#define CONFIG_ENV_OVERWRITE	1
#define BOARD_LATE_INIT

#define	CONFIG_EXTRA_ENV_SETTINGS \
		"unlock=yes\0"

#define CONFIG_CMD_JFFS2
#undef CONFIG_CMD_EEPROM
#define CONFIG_CMD_NET
#define CONFIG_CMD_RUN
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_PING
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_I2C
#define CONFIG_CMD_DATE
#define CONFIG_CMD_POST
#define CONFIG_CMD_MISC
#define CONFIG_CMD_LOADS
#define CONFIG_CMD_IMI
#define CONFIG_CMD_NFS
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_SAVEENV

#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_PROMPT_HUSH_PS2	    ">>"

#define CONFIG_SYS_MAX_NAND_DEVICE	0 /* Max number of NAND devices */
#define SECTORSIZE			     512

#define ADDR_COLUMN		1
#define ADDR_PAGE		2
#define ADDR_COLUMN_PAGE	3

#define CONFIG_NR_DRAM_BANKS	1
#define PHYS_SDRAM		0x20000000
#define PHYS_SDRAM_SIZE	0x2000000 /* 32 megs */

#define CONFIG_SYS_MEMTEST_START	0x21000000 /* PHYS_SDRAM */
/* CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 262144 */
#define CONFIG_SYS_MEMTEST_END	0x00100000

#define CONFIG_DRIVER_ETHER
#define CONFIG_NET_RETRY_COUNT	20
#define CONFIG_AT91C_USE_RMII

#define PHYS_FLASH_1		0x10000000
#define PHYS_FLASH_SIZE	0x800000 /* 8 megs main flash */
#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
#define CONFIG_SYS_MAX_FLASH_BANKS	1
#define CONFIG_SYS_MAX_FLASH_SECT	256
#define CONFIG_SYS_FLASH_ERASE_TOUT	(2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
#define CONFIG_SYS_FLASH_WRITE_TOUT	(2*CONFIG_SYS_HZ) /* Timeout for Flash Write */

#ifdef CONFIG_ENV_IS_IN_DATAFLASH
#define CONFIG_ENV_OFFSET		0x20000
#define CONFIG_ENV_ADDR		(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
#define CONFIG_ENV_SIZE		0x2000
#else
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR		(PHYS_FLASH_1 + 0x00020000)
#define CONFIG_ENV_SIZE		2048
#endif

#ifdef CONFIG_ENV_IS_IN_EEPROM
#define CONFIG_ENV_OFFSET		1024
#define CONFIG_ENV_SIZE		1024
#endif

#define CONFIG_SYS_LOAD_ADDR		0x21000000 /* default load address */

/* use for protect flash sectors */
#define CONFIG_SYS_BOOT_SIZE		0x6000 /* 24 KBytes */
#define CONFIG_SYS_U_BOOT_BASE	(PHYS_FLASH_1 + 0x10000)
#define CONFIG_SYS_U_BOOT_SIZE	0x10000 /* 64 KBytes */

#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 , 19200, 38400, 57600, 9600 }

#define CONFIG_SYS_PROMPT		"U-Boot> " /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE		512 /* Console I/O Buffer Size */
#define CONFIG_SYS_MAXARGS		16 /* max number of command args */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)

#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_HZ_CLOCK		AT91C_MASTER_CLOCK/2

#define CONFIG_STACKSIZE	(32*1024) /* regular stack */

#ifdef CONFIG_USE_IRQ
#error CONFIG_USE_IRQ not supported
#endif

#endif
Commit	Line	Data
ea8d989f TT	1	/*
	2	* Based on Modifications by Alan Lu / Artila and
	3	* Rick Bronson <rick@efn.org>
	4	*
	5	* Configuration settings for the Artila M-501 starter kit,
	6	* with V02 processor card.
	7	*
	8	* See file CREDITS for list of people who contributed to this
	9	* project.
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	* MA 02111-1307 USA
	25	*/
	26
	27	#ifndef __CONFIG_H
	28	#define __CONFIG_H
	29
	30	/* ARM asynchronous clock */
	31	/* from 18.432 MHz crystal (18432000 / 4 * 39) */
	32	#define AT91C_MAIN_CLOCK 179712000
	33	/* Perip clock (AT91C_MASTER_CLOCK / 3) */
	34	#define AT91C_MASTER_CLOCK 59904000
	35	#define AT91_SLOW_CLOCK 32768 /* slow clock */
	36
	37	#define CONFIG_AT91RM9200DK 1 /* on an AT91RM9200DK Board */
	38	#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
	39	#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
	40	#define CONFIG_SETUP_MEMORY_TAGS 1
	41	#define CONFIG_INITRD_TAG 1
	42
ea8d989f	43	#define CONFIG_MENUPROMPT "."
8a48686f JCPV	44	/*
	45	* LowLevel Init
	46	*/
	47	#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
	48	/* flash */
	49	#define CONFIG_SYS_MC_PUIA_VAL 0x00000000
	50	#define CONFIG_SYS_MC_PUP_VAL 0x00000000
	51	#define CONFIG_SYS_MC_PUER_VAL 0x00000000
	52	#define CONFIG_SYS_MC_ASR_VAL 0x00000000
	53	#define CONFIG_SYS_MC_AASR_VAL 0x00000000
	54	#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
	55	#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
	56
	57	/* clocks */
	58	#define CONFIG_SYS_PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */
	59	#define CONFIG_SYS_PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
	60	/* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
	61	#define CONFIG_SYS_MCKR_VAL 0x00000202
	62
	63	/* sdram */
	64	#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
	65	#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000
	66	#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000
	67	#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */
	68	#define CONFIG_SYS_SDRC_CR_VAL 0x2188c155 /* set up the CONFIG_SYS_SDRAM */
	69	#define CONFIG_SYS_SDRAM 0x20000000 /* address of the CONFIG_SYS_SDRAM */
	70	#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the CONFIG_SYS_SDRAM */
	71	#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */
	72	#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */
	73	#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */
	74	#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
	75	#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */
	76	#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
ea8d989f TT	77
	78	/*
	79	* Size of malloc() pool
	80	*/
6d0f6bcf JCPV	81	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
6d0f6bcf JCPV	82	#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Bytes reserved for initial data */
ea8d989f TT	83
	84	#define CONFIG_BAUDRATE 115200
	85
	86	/* Hardcode so no __divsi3 : AT91C_MASTER_CLOCK / baudrate / 16 */
6d0f6bcf	87	#define CONFIG_SYS_AT91C_BRGR_DIVISOR 33
ea8d989f TT	88
	89	/*
	90	* Hardware drivers
	91	*/
6d0f6bcf	92	#define CONFIG_SYS_FLASH_CFI 1
00b1883a	93	#define CONFIG_FLASH_CFI_DRIVER 1
0e8d1586	94	#define CONFIG_ENV_SECT_SIZE 0x20000
6d0f6bcf JCPV	95	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
6d0f6bcf JCPV	96	#define CONFIG_SYS_FLASH_PROTECTION /for Intel P30 Flash/
ea8d989f	97	#define CONFIG_HARD_I2C
6d0f6bcf JCPV	98	#define CONFIG_SYS_I2C_SPEED 100
	99	#define CONFIG_SYS_I2C_SLAVE 0
	100	#define CONFIG_SYS_CONSOLE_INFO_QUIET
bb1f8b4f	101	#undef CONFIG_ENV_IS_IN_EEPROM
6d0f6bcf JCPV	102	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
	103	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	104	#define CONFIG_SYS_EEPROM_AT24C16
	105	#define CONFIG_SYS_I2C_RTC_ADDR 0x32
ea8d989f TT	106	#undef CONFIG_RTC_DS1338
	107	#define CONFIG_RTC_RS5C372A
	108	#undef CONFIG_POST
	109	#define CONFIG_M501SK
	110	#define CONFIG_CMC_PU2
	111
	112	/* define one of these to choose the DBGU, USART0 or USART1 as console */
	113	#define CONFIG_DBGU
	114	#undef CONFIG_USART0
	115	#undef CONFIG_USART1
	116
	117	#undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */
	118	#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */
	119
	120	#define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200 " \
	121	"initrd=0x20800000,8192000 ramdisk_size=15360 " \
	122	"root=/dev/ram0 rw mtdparts=phys_mapped_flash:" \
	123	"128k(loader)ro,128k(reserved)ro,1408k(linux)" \
	124	"ro,2560k(ramdisk)ro,-(userdisk)"
	125	#define CONFIG_BOOTCOMMAND "bootm 10040000 101a0000"
	126	#define CONFIG_BOOTDELAY 1
	127	#define CONFIG_BAUDRATE 115200
	128	#define CONFIG_IPADDR 192.168.1.100
	129	#define CONFIG_SERVERIP 192.168.1.1
	130	#define CONFIG_GATEWAYIP 192.168.1.254
	131	#define CONFIG_NETMASK 255.255.255.0
	132	#define CONFIG_BOOTFILE uImage
	133	#define CONFIG_ETHADDR 00:13:48:aa:bb:cc
	134	#define CONFIG_ENV_OVERWRITE 1
	135	#define BOARD_LATE_INIT
	136
	137	#define CONFIG_EXTRA_ENV_SETTINGS \
	138	"unlock=yes\0"
	139
936897d4	140	#define CONFIG_CMD_JFFS2
ea8d989f TT	141	#undef CONFIG_CMD_EEPROM
	142	#define CONFIG_CMD_NET
	143	#define CONFIG_CMD_RUN
	144	#define CONFIG_CMD_DHCP
	145	#define CONFIG_CMD_MEMORY
	146	#define CONFIG_CMD_PING
	147	#define CONFIG_CMD_SDRAM
	148	#define CONFIG_CMD_DIAG
	149	#define CONFIG_CMD_I2C
	150	#define CONFIG_CMD_DATE
	151	#define CONFIG_CMD_POST
	152	#define CONFIG_CMD_MISC
	153	#define CONFIG_CMD_LOADS
	154	#define CONFIG_CMD_IMI
	155	#define CONFIG_CMD_NFS
	156	#define CONFIG_CMD_FLASH
bdab39d3	157	#define CONFIG_CMD_SAVEENV
ea8d989f	158
6d0f6bcf	159	#define CONFIG_SYS_HUSH_PARSER
ea8d989f	160	#define CONFIG_AUTO_COMPLETE
6d0f6bcf	161	#define CONFIG_SYS_PROMPT_HUSH_PS2 ">>"
ea8d989f	162
6d0f6bcf	163	#define CONFIG_SYS_MAX_NAND_DEVICE 0 /* Max number of NAND devices */
ea8d989f TT	164	#define SECTORSIZE 512
	165
	166	#define ADDR_COLUMN 1
	167	#define ADDR_PAGE 2
	168	#define ADDR_COLUMN_PAGE 3
	169
	170	#define CONFIG_NR_DRAM_BANKS 1
	171	#define PHYS_SDRAM 0x20000000
	172	#define PHYS_SDRAM_SIZE 0x2000000 /* 32 megs */
	173
6d0f6bcf JCPV	174	#define CONFIG_SYS_MEMTEST_START 0x21000000 /* PHYS_SDRAM */
	175	/* CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 262144 */
	176	#define CONFIG_SYS_MEMTEST_END 0x00100000
ea8d989f TT	177
	178	#define CONFIG_DRIVER_ETHER
	179	#define CONFIG_NET_RETRY_COUNT 20
	180	#define CONFIG_AT91C_USE_RMII
	181
	182	#define PHYS_FLASH_1 0x10000000
	183	#define PHYS_FLASH_SIZE 0x800000 /* 8 megs main flash */
6d0f6bcf JCPV	184	#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
	185	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	186	#define CONFIG_SYS_MAX_FLASH_SECT 256
	187	#define CONFIG_SYS_FLASH_ERASE_TOUT (2CONFIG_SYS_HZ) / Timeout for Flash Erase */
	188	#define CONFIG_SYS_FLASH_WRITE_TOUT (2CONFIG_SYS_HZ) / Timeout for Flash Write */
ea8d989f	189
057c849c	190	#ifdef CONFIG_ENV_IS_IN_DATAFLASH
0e8d1586	191	#define CONFIG_ENV_OFFSET 0x20000
6d0f6bcf	192	#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
0e8d1586	193	#define CONFIG_ENV_SIZE 0x2000
ea8d989f	194	#else
5a1aceb0	195	#define CONFIG_ENV_IS_IN_FLASH
0e8d1586 JCPV	196	#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x00020000)
0e8d1586 JCPV	197	#define CONFIG_ENV_SIZE 2048
ea8d989f TT	198	#endif
ea8d989f TT	199
bb1f8b4f	200	#ifdef CONFIG_ENV_IS_IN_EEPROM
0e8d1586 JCPV	201	#define CONFIG_ENV_OFFSET 1024
0e8d1586 JCPV	202	#define CONFIG_ENV_SIZE 1024
ea8d989f TT	203	#endif
ea8d989f TT	204
6d0f6bcf	205	#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */
ea8d989f TT	206
ea8d989f TT	207	/* use for protect flash sectors */
6d0f6bcf JCPV	208	#define CONFIG_SYS_BOOT_SIZE 0x6000 /* 24 KBytes */
	209	#define CONFIG_SYS_U_BOOT_BASE (PHYS_FLASH_1 + 0x10000)
	210	#define CONFIG_SYS_U_BOOT_SIZE 0x10000 /* 64 KBytes */
ea8d989f	211
6d0f6bcf	212	#define CONFIG_SYS_BAUDRATE_TABLE { 115200 , 19200, 38400, 57600, 9600 }
ea8d989f	213
6d0f6bcf JCPV	214	#define CONFIG_SYS_PROMPT "U-Boot> " /* Monitor Command Prompt */
	215	#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
	216	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
ea8d989f	217	/* Print Buffer Size */
6d0f6bcf	218	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
ea8d989f	219
6d0f6bcf JCPV	220	#define CONFIG_SYS_HZ 1000
6d0f6bcf JCPV	221	#define CONFIG_SYS_HZ_CLOCK AT91C_MASTER_CLOCK/2
ea8d989f TT	222
	223	#define CONFIG_STACKSIZE (321024) / regular stack */
	224
	225	#ifdef CONFIG_USE_IRQ
	226	#error CONFIG_USE_IRQ not supported
	227	#endif
	228
	229	#endif