[people/ms/u-boot.git] / include / configs / makalu.h

/*
 * Copyright (c) 2008 Nuovation System Designs, LLC
 *   Grant Erickson <gerickson@nuovations.com>
 *
 * (C) Copyright 2007-2008
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/************************************************************************
 * makalu.h - configuration for AMCC Makalu (405EX)
 ***********************************************************************/

#ifndef __CONFIG_H
#define __CONFIG_H

/*-----------------------------------------------------------------------
 * High Level Configuration Options
 *----------------------------------------------------------------------*/
#define CONFIG_MAKALU		1		/* Board is Makalu	*/
#define CONFIG_4xx		1		/* ... PPC4xx family	*/
#define CONFIG_405EX		1		/* Specifc 405EX support*/
#define CONFIG_SYS_CLK_FREQ	33330000	/* ext frequency to pll	*/

/*
 * Include common defines/options for all AMCC eval boards
 */
#define CONFIG_HOSTNAME	makalu
#define CONFIG_ADDMISC	"addmisc=setenv bootargs ${bootargs} rtc-x1205.probe=0,0x6f\0"
#include "amcc-common.h"

#define CONFIG_BOARD_EARLY_INIT_F 1		/* Call board_early_init_f */
#define CONFIG_MISC_INIT_R	1		/* Call misc_init_r	*/

/*-----------------------------------------------------------------------
 * Base addresses -- Note these are effective addresses where the
 * actual resources get mapped (not physical addresses)
 *----------------------------------------------------------------------*/
#define CFG_FLASH_BASE		0xFC000000
#define CFG_FPGA_BASE		0xF0000000
#define CFG_PERIPHERAL_BASE	0xEF600000      /* internal peripherals*/

/*-----------------------------------------------------------------------
 * Initial RAM & Stack Pointer Configuration Options
 *
 *   There are traditionally three options for the primordial
 *   (i.e. initial) stack usage on the 405-series:
 *
 *      1) On-chip Memory (OCM) (i.e. SRAM)
 *      2) Data cache
 *      3) SDRAM
 *
 *   For the 405EX(r), there is no OCM, so we are left with (2) or (3)
 *   the latter of which is less than desireable since it requires
 *   setting up the SDRAM and ECC in assembly code.
 *
 *   To use (2), define 'CFG_INIT_DCACHE_CS' to be an unused chip
 *   select on the External Bus Controller (EBC) and then select a
 *   value for 'CFG_INIT_RAM_ADDR' outside of the range of valid,
 *   physical SDRAM. Otherwise, undefine 'CFG_INIT_DCACHE_CS' and
 *   select a value for 'CFG_INIT_RAM_ADDR' within the range of valid,
 *   physical SDRAM to use (3).
 *-----------------------------------------------------------------------*/

#define CFG_INIT_DCACHE_CS	4

#if defined(CFG_INIT_DCACHE_CS)
#define CFG_INIT_RAM_ADDR	(CFG_SDRAM_BASE + ( 1 << 30))	/*  1 GiB */
#else
#define CFG_INIT_RAM_ADDR	(CFG_SDRAM_BASE + (32 << 20))	/* 32 MiB */
#endif /* defined(CFG_INIT_DCACHE_CS) */

#define CFG_INIT_RAM_END        (4 << 10)			/*  4 KiB */
#define CFG_GBL_DATA_SIZE	256		/* num bytes initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)

/*
 * If the data cache is being used for the primordial stack and global
 * data area, the POST word must be placed somewhere else. The General
 * Purpose Timer (GPT) is unused by u-boot and the kernel and preserves
 * its compare and mask register contents across reset, so it is used
 * for the POST word.
 */

#if defined(CFG_INIT_DCACHE_CS)
# define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
# define CFG_POST_ALT_WORD_ADDR	(CFG_PERIPHERAL_BASE + GPT0_COMP6)
#else
# define CFG_INIT_EXTRA_SIZE	16
# define CFG_INIT_SP_OFFSET	(CFG_GBL_DATA_OFFSET - CFG_INIT_EXTRA_SIZE)
# define CFG_POST_WORD_ADDR	(CFG_GBL_DATA_OFFSET - 4)
# define CFG_OCM_DATA_ADDR	CFG_INIT_RAM_ADDR
#endif /* defined(CFG_INIT_DCACHE_CS) */

/*-----------------------------------------------------------------------
 * Serial Port
 *----------------------------------------------------------------------*/
#undef CFG_EXT_SERIAL_CLOCK			/* no ext. clk		*/
/* define this if you want console on UART1 */
#undef CONFIG_UART1_CONSOLE

/*-----------------------------------------------------------------------
 * Environment
 *----------------------------------------------------------------------*/
#define CFG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/

/*-----------------------------------------------------------------------
 * FLASH related
 *----------------------------------------------------------------------*/
#define CFG_FLASH_CFI			/* The flash is CFI compatible	*/
#define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver	*/

#define CFG_FLASH_BANKS_LIST    {CFG_FLASH_BASE}
#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CFG_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */

#ifdef CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE	0x20000	/* size of one complete sector	*/
#define CFG_ENV_ADDR		(CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
#define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/

/* Address and size of Redundant Environment Sector	*/
#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
#endif /* CFG_ENV_IS_IN_FLASH */

/*-----------------------------------------------------------------------
 * DDR SDRAM
 *----------------------------------------------------------------------*/
#define CFG_MBYTES_SDRAM        (256)		/* 256MB			*/

#define	CFG_SDRAM0_MB0CF_BASE	((  0 << 20) + CFG_SDRAM_BASE)
#define	CFG_SDRAM0_MB1CF_BASE	((128 << 20) + CFG_SDRAM_BASE)

/* DDR1/2 SDRAM Device Control Register Data Values */
#define CFG_SDRAM0_MB0CF	((CFG_SDRAM0_MB0CF_BASE >> 3)	| \
				 SDRAM_RXBAS_SDSZ_128MB 	| \
				 SDRAM_RXBAS_SDAM_MODE2 	| \
				 SDRAM_RXBAS_SDBE_ENABLE)
#define CFG_SDRAM0_MB1CF	((CFG_SDRAM0_MB1CF_BASE >> 3)	| \
				 SDRAM_RXBAS_SDSZ_128MB 	| \
				 SDRAM_RXBAS_SDAM_MODE2 	| \
				 SDRAM_RXBAS_SDBE_ENABLE)
#define CFG_SDRAM0_MB2CF	SDRAM_RXBAS_SDBE_DISABLE
#define CFG_SDRAM0_MB3CF	SDRAM_RXBAS_SDBE_DISABLE
#define CFG_SDRAM0_MCOPT1	0x04322000
#define CFG_SDRAM0_MCOPT2	0x00000000
#define CFG_SDRAM0_MODT0	0x01800000
#define CFG_SDRAM0_MODT1	0x00000000
#define CFG_SDRAM0_CODT		0x0080f837
#define CFG_SDRAM0_RTR		0x06180000
#define CFG_SDRAM0_INITPLR0	0xa8380000
#define CFG_SDRAM0_INITPLR1	0x81900400
#define CFG_SDRAM0_INITPLR2	0x81020000
#define CFG_SDRAM0_INITPLR3	0x81030000
#define CFG_SDRAM0_INITPLR4	0x81010404
#define CFG_SDRAM0_INITPLR5	0x81000542
#define CFG_SDRAM0_INITPLR6	0x81900400
#define CFG_SDRAM0_INITPLR7	0x8D080000
#define CFG_SDRAM0_INITPLR8	0x8D080000
#define CFG_SDRAM0_INITPLR9	0x8D080000
#define CFG_SDRAM0_INITPLR10	0x8D080000
#define CFG_SDRAM0_INITPLR11	0x81000442
#define CFG_SDRAM0_INITPLR12	0x81010780
#define CFG_SDRAM0_INITPLR13	0x81010400
#define CFG_SDRAM0_INITPLR14	0x00000000
#define CFG_SDRAM0_INITPLR15	0x00000000
#define CFG_SDRAM0_RQDC		0x80000038
#define CFG_SDRAM0_RFDC		0x00000209
#define CFG_SDRAM0_RDCC		0x40000000
#define CFG_SDRAM0_DLCR		0x030000a5
#define CFG_SDRAM0_CLKTR	0x80000000
#define CFG_SDRAM0_WRDTR	0x00000000
#define CFG_SDRAM0_SDTR1	0x80201000
#define CFG_SDRAM0_SDTR2	0x32204232
#define CFG_SDRAM0_SDTR3	0x080b0d1a
#define CFG_SDRAM0_MMODE	0x00000442
#define CFG_SDRAM0_MEMODE	0x00000404

/*-----------------------------------------------------------------------
 * I2C
 *----------------------------------------------------------------------*/
#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/

#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	6	/* 24C02 requires 5ms delay */
#define CFG_I2C_EEPROM_ADDR	0x52	/* I2C boot EEPROM (24C02BN)	*/
#define CFG_I2C_EEPROM_ADDR_LEN	1	/* Bytes of address		*/

/* Standard DTT sensor configuration */
#define CONFIG_DTT_DS1775	1
#define CONFIG_DTT_SENSORS	{ 0 }
#define CFG_I2C_DTT_ADDR	0x48

/* RTC configuration */
#define CONFIG_RTC_X1205	1
#define CFG_I2C_RTC_ADDR	0x6f

/*-----------------------------------------------------------------------
 * Ethernet
 *----------------------------------------------------------------------*/
#define CONFIG_M88E1111_PHY	1
#define CONFIG_IBM_EMAC4_V4	1
#define CONFIG_EMAC_PHY_MODE	EMAC_PHY_MODE_RGMII_RGMII
#define CONFIG_PHY_ADDR		6	/* PHY address, See schematics	*/

#define CONFIG_PHY_RESET	1	/* reset phy upon startup	*/
#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */

#define CONFIG_HAS_ETH0		1

#define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"   */
#define CONFIG_PHY1_ADDR	0

/*
 * Default environment variables
 */
#define	CONFIG_EXTRA_ENV_SETTINGS					\
	CONFIG_AMCC_DEF_ENV						\
	CONFIG_AMCC_DEF_ENV_POWERPC					\
	CONFIG_AMCC_DEF_ENV_PPC_OLD					\
	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
	"kernel_addr=fc000000\0"					\
	"fdt_addr=fc1e0000\0"						\
	"ramdisk_addr=fc200000\0"					\
	"pciconfighost=1\0"						\
	"pcie_mode=RP:RP\0"						\
	""

/*
 * Commands additional to the ones defined in amcc-common.h
 */
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DTT
#define CONFIG_CMD_LOG
#define CONFIG_CMD_PCI
#define CONFIG_CMD_SNTP

/* POST support */
#define CONFIG_POST		(CFG_POST_CACHE		| \
				 CFG_POST_CPU		| \
				 CFG_POST_ETHER		| \
				 CFG_POST_I2C		| \
				 CFG_POST_MEMORY	| \
				 CFG_POST_UART)

/* Define here the base-addresses of the UARTs to test in POST */
#define CFG_POST_UART_TABLE	{UART0_BASE, UART1_BASE}

#define CONFIG_LOGBUFFER
#define CFG_POST_CACHE_ADDR	0x00800000 /* free virtual address	*/

#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */

/*-----------------------------------------------------------------------
 * PCI stuff
 *----------------------------------------------------------------------*/
#define CONFIG_PCI			/* include pci support	        */
#define CONFIG_PCI_PNP		1	/* do pci plug-and-play		*/
#define CONFIG_PCI_SCAN_SHOW	1	/* show pci devices on startup	*/
#define CONFIG_PCI_CONFIG_HOST_BRIDGE

/*-----------------------------------------------------------------------
 * PCIe stuff
 *----------------------------------------------------------------------*/
#define CFG_PCIE_MEMBASE	0x90000000	/* mapped PCIe memory	*/
#define CFG_PCIE_MEMSIZE	0x08000000      /* 128 Meg, smallest incr per port */

#define	CFG_PCIE0_CFGBASE	0xa0000000      /* remote access */
#define	CFG_PCIE0_XCFGBASE	0xb0000000      /* local access */
#define	CFG_PCIE0_CFGMASK	0xe0000001      /* 512 Meg */

#define	CFG_PCIE1_CFGBASE	0xc0000000      /* remote access */
#define	CFG_PCIE1_XCFGBASE	0xd0000000      /* local access */
#define	CFG_PCIE1_CFGMASK	0xe0000001      /* 512 Meg */

#define	CFG_PCIE0_UTLBASE	0xef502000
#define	CFG_PCIE1_UTLBASE	0xef503000

/* base address of inbound PCIe window */
#define CFG_PCIE_INBOUND_BASE	0x0000000000000000ULL

/*-----------------------------------------------------------------------
 * External Bus Controller (EBC) Setup
 *----------------------------------------------------------------------*/
/* Memory Bank 0 (NOR-FLASH) initialization					*/
#define CFG_EBC_PB0AP		0x08033700
#define CFG_EBC_PB0CR		(CFG_FLASH_BASE | 0xda000)

/* Memory Bank 2 (CPLD) initialization						*/
#define CFG_EBC_PB2AP           0x9400C800
#define CFG_EBC_PB2CR           0xF0018000 /*  BAS=0x800,BS=1MB,BU=R/W,BW=8bit	*/

#define CFG_EBC_CFG		0x7FC00000 /*  EBC0_CFG */

/*-----------------------------------------------------------------------
 * GPIO Setup
 *----------------------------------------------------------------------*/
#define CFG_4xx_GPIO_TABLE { /*	  Out		  GPIO	Alternate1	Alternate2	Alternate3 */ \
{											\
/* GPIO Core 0 */									\
{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO0	EBC_DATA_PAR(0)			*/	\
{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO1	EBC_DATA_PAR(1)			*/	\
{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO2	EBC_DATA_PAR(2)			*/	\
{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO3	EBC_DATA_PAR(3)			*/	\
{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO4	EBC_DATA(20)	USB2_DATA(4)	*/	\
{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO5	EBC_DATA(21)	USB2_DATA(5)	*/	\
{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO6	EBC_DATA(22)	USB2_DATA(6)	*/	\
{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO7	EBC_DATA(23)	USB2_DATA(7)	*/	\
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8	CS(1)/NFCE(1)	IRQ(7)		*/	\
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9	CS(2)/NFCE(2)	IRQ(8)		*/	\
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 CS(3)/NFCE(3)	IRQ(9)		*/	\
{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 IRQ(6)				*/	\
{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO12 EBC_DATA(16)	USB2_DATA(0)	*/	\
{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO13 EBC_DATA(17)	USB2_DATA(1)	*/	\
{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO14 EBC_DATA(18)	USB2_DATA(2)	*/	\
{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO15 EBC_DATA(19)	USB2_DATA(3)	*/	\
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 UART0_DCD	UART1_CTS	*/	\
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 UART0_DSR	UART1_RTS	*/	\
{GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 UART0_CTS			*/	\
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 UART0_RTS			*/	\
{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO20 UART0_DTR	UART1_TX	*/	\
{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO21 UART0_RI	UART1_RX	*/	\
{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO22 EBC_HOLD_REQ	DMA_ACK2	*/	\
{GPIO0_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_0}, /* GPIO23 EBC_HOLD_ACK	DMA_REQ2	*/	\
{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO24 EBC_EXT_REQ	DMA_EOT2	IRQ(4) */ \
{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO25 EBC_EXT_ACK	DMA_ACK3	IRQ(3) */ \
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 EBC_ADDR(5)	DMA_EOT0	TS(3) */ \
{GPIO0_BASE, GPIO_IN,  GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EBC_BUS_REQ	DMA_EOT3	IRQ(5) */ \
{GPIO0_BASE, GPIO_IN,  GPIO_SEL , GPIO_OUT_0}, /* GPIO28				*/	\
{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO29 DMA_EOT1	IRQ(2)		*/	\
{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO30 DMA_REQ1	IRQ(1)		*/	\
{GPIO0_BASE, GPIO_IN,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO31 DMA_ACK1	IRQ(0)		*/	\
}												\
}

#define CFG_GPIO_PCIE_RST	23
#define CFG_GPIO_PCIE_CLKREQ	27
#define CFG_GPIO_PCIE_WAKE	28

#endif	/* __CONFIG_H */
Commit	Line	Data
211ea91a	1	/*
8a24c07b GE	2	* Copyright (c) 2008 Nuovation System Designs, LLC
	3	* Grant Erickson <gerickson@nuovations.com>
	4	*
869d14b4	5	* (C) Copyright 2007-2008
211ea91a SR	6	* Stefan Roese, DENX Software Engineering, sr@denx.de.
	7	*
	8	* See file CREDITS for list of people who contributed to this
	9	* project.
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	* MA 02111-1307 USA
	25	*/
	26
	27	/************************************************************************
	28	* makalu.h - configuration for AMCC Makalu (405EX)
	29	***********************************************************************/
	30
	31	#ifndef __CONFIG_H
	32	#define __CONFIG_H
	33
	34	/*-----------------------------------------------------------------------
	35	* High Level Configuration Options
	36	----------------------------------------------------------------------/
	37	#define CONFIG_MAKALU 1 /* Board is Makalu */
	38	#define CONFIG_4xx 1 /* ... PPC4xx family */
	39	#define CONFIG_405EX 1 /* Specifc 405EX support*/
	40	#define CONFIG_SYS_CLK_FREQ 33330000 /* ext frequency to pll */
	41
490f2040 SR	42	/*
	43	* Include common defines/options for all AMCC eval boards
	44	*/
	45	#define CONFIG_HOSTNAME makalu
	46	#define CONFIG_ADDMISC "addmisc=setenv bootargs ${bootargs} rtc-x1205.probe=0,0x6f\0"
	47	#include "amcc-common.h"
	48
211ea91a SR	49	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
	50	#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
	51
	52	/*-----------------------------------------------------------------------
	53	* Base addresses -- Note these are effective addresses where the
	54	* actual resources get mapped (not physical addresses)
	55	----------------------------------------------------------------------/
ecdcbd4f	56	#define CFG_FLASH_BASE 0xFC000000
211ea91a SR	57	#define CFG_FPGA_BASE 0xF0000000
211ea91a SR	58	#define CFG_PERIPHERAL_BASE 0xEF600000 /* internal peripherals*/
211ea91a SR	59
211ea91a SR	60	/*-----------------------------------------------------------------------
8a24c07b GE	61	* Initial RAM & Stack Pointer Configuration Options
	62	*
	63	* There are traditionally three options for the primordial
	64	* (i.e. initial) stack usage on the 405-series:
	65	*
	66	* 1) On-chip Memory (OCM) (i.e. SRAM)
	67	* 2) Data cache
	68	* 3) SDRAM
	69	*
	70	* For the 405EX(r), there is no OCM, so we are left with (2) or (3)
	71	* the latter of which is less than desireable since it requires
	72	* setting up the SDRAM and ECC in assembly code.
	73	*
	74	* To use (2), define 'CFG_INIT_DCACHE_CS' to be an unused chip
	75	* select on the External Bus Controller (EBC) and then select a
	76	* value for 'CFG_INIT_RAM_ADDR' outside of the range of valid,
	77	* physical SDRAM. Otherwise, undefine 'CFG_INIT_DCACHE_CS' and
	78	* select a value for 'CFG_INIT_RAM_ADDR' within the range of valid,
	79	* physical SDRAM to use (3).
	80	-----------------------------------------------------------------------/
	81
	82	#define CFG_INIT_DCACHE_CS 4
	83
	84	#if defined(CFG_INIT_DCACHE_CS)
	85	#define CFG_INIT_RAM_ADDR (CFG_SDRAM_BASE + ( 1 << 30)) /* 1 GiB */
	86	#else
	87	#define CFG_INIT_RAM_ADDR (CFG_SDRAM_BASE + (32 << 20)) /* 32 MiB */
	88	#endif /* defined(CFG_INIT_DCACHE_CS) */
	89
	90	#define CFG_INIT_RAM_END (4 << 10) /* 4 KiB */
211ea91a SR	91	#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
211ea91a SR	92	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
211ea91a	93
8a24c07b GE	94	/*
	95	* If the data cache is being used for the primordial stack and global
	96	* data area, the POST word must be placed somewhere else. The General
	97	* Purpose Timer (GPT) is unused by u-boot and the kernel and preserves
	98	* its compare and mask register contents across reset, so it is used
	99	* for the POST word.
	100	*/
	101
	102	#if defined(CFG_INIT_DCACHE_CS)
	103	# define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	104	# define CFG_POST_ALT_WORD_ADDR (CFG_PERIPHERAL_BASE + GPT0_COMP6)
	105	#else
	106	# define CFG_INIT_EXTRA_SIZE 16
	107	# define CFG_INIT_SP_OFFSET (CFG_GBL_DATA_OFFSET - CFG_INIT_EXTRA_SIZE)
	108	# define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 4)
	109	# define CFG_OCM_DATA_ADDR CFG_INIT_RAM_ADDR
	110	#endif /* defined(CFG_INIT_DCACHE_CS) */
211ea91a SR	111
	112	/*-----------------------------------------------------------------------
	113	* Serial Port
	114	----------------------------------------------------------------------/
	115	#undef CFG_EXT_SERIAL_CLOCK /* no ext. clk */
211ea91a SR	116	/* define this if you want console on UART1 */
	117	#undef CONFIG_UART1_CONSOLE
	118
211ea91a SR	119	/*-----------------------------------------------------------------------
	120	* Environment
	121	----------------------------------------------------------------------/
	122	#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
	123
	124	/*-----------------------------------------------------------------------
	125	* FLASH related
	126	----------------------------------------------------------------------/
	127	#define CFG_FLASH_CFI /* The flash is CFI compatible */
00b1883a	128	#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
211ea91a SR	129
	130	#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
	131	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
	132	#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
	133
	134	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
	135	#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
	136
	137	#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
	138	#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
	139
	140	#ifdef CFG_ENV_IS_IN_FLASH
53677ef1	141	#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
211ea91a SR	142	#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
	143	#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
	144
	145	/* Address and size of Redundant Environment Sector */
	146	#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
	147	#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
	148	#endif /* CFG_ENV_IS_IN_FLASH */
	149
	150	/*-----------------------------------------------------------------------
	151	* DDR SDRAM
	152	----------------------------------------------------------------------/
8a24c07b GE	153	#define CFG_MBYTES_SDRAM (256) /* 256MB */
	154
	155	#define CFG_SDRAM0_MB0CF_BASE (( 0 << 20) + CFG_SDRAM_BASE)
	156	#define CFG_SDRAM0_MB1CF_BASE ((128 << 20) + CFG_SDRAM_BASE)
	157
	158	/* DDR1/2 SDRAM Device Control Register Data Values */
	159	#define CFG_SDRAM0_MB0CF ((CFG_SDRAM0_MB0CF_BASE >> 3) \| \
	160	SDRAM_RXBAS_SDSZ_128MB \| \
	161	SDRAM_RXBAS_SDAM_MODE2 \| \
	162	SDRAM_RXBAS_SDBE_ENABLE)
	163	#define CFG_SDRAM0_MB1CF ((CFG_SDRAM0_MB1CF_BASE >> 3) \| \
	164	SDRAM_RXBAS_SDSZ_128MB \| \
	165	SDRAM_RXBAS_SDAM_MODE2 \| \
	166	SDRAM_RXBAS_SDBE_ENABLE)
	167	#define CFG_SDRAM0_MB2CF SDRAM_RXBAS_SDBE_DISABLE
	168	#define CFG_SDRAM0_MB3CF SDRAM_RXBAS_SDBE_DISABLE
	169	#define CFG_SDRAM0_MCOPT1 0x04322000
	170	#define CFG_SDRAM0_MCOPT2 0x00000000
	171	#define CFG_SDRAM0_MODT0 0x01800000
	172	#define CFG_SDRAM0_MODT1 0x00000000
	173	#define CFG_SDRAM0_CODT 0x0080f837
	174	#define CFG_SDRAM0_RTR 0x06180000
	175	#define CFG_SDRAM0_INITPLR0 0xa8380000
	176	#define CFG_SDRAM0_INITPLR1 0x81900400
	177	#define CFG_SDRAM0_INITPLR2 0x81020000
	178	#define CFG_SDRAM0_INITPLR3 0x81030000
	179	#define CFG_SDRAM0_INITPLR4 0x81010404
	180	#define CFG_SDRAM0_INITPLR5 0x81000542
	181	#define CFG_SDRAM0_INITPLR6 0x81900400
	182	#define CFG_SDRAM0_INITPLR7 0x8D080000
	183	#define CFG_SDRAM0_INITPLR8 0x8D080000
	184	#define CFG_SDRAM0_INITPLR9 0x8D080000
	185	#define CFG_SDRAM0_INITPLR10 0x8D080000
	186	#define CFG_SDRAM0_INITPLR11 0x81000442
	187	#define CFG_SDRAM0_INITPLR12 0x81010780
	188	#define CFG_SDRAM0_INITPLR13 0x81010400
	189	#define CFG_SDRAM0_INITPLR14 0x00000000
	190	#define CFG_SDRAM0_INITPLR15 0x00000000
	191	#define CFG_SDRAM0_RQDC 0x80000038
	192	#define CFG_SDRAM0_RFDC 0x00000209
	193	#define CFG_SDRAM0_RDCC 0x40000000
	194	#define CFG_SDRAM0_DLCR 0x030000a5
	195	#define CFG_SDRAM0_CLKTR 0x80000000
	196	#define CFG_SDRAM0_WRDTR 0x00000000
	197	#define CFG_SDRAM0_SDTR1 0x80201000
	198	#define CFG_SDRAM0_SDTR2 0x32204232
	199	#define CFG_SDRAM0_SDTR3 0x080b0d1a
	200	#define CFG_SDRAM0_MMODE 0x00000442
	201	#define CFG_SDRAM0_MEMODE 0x00000404
211ea91a SR	202
	203	/*-----------------------------------------------------------------------
	204	* I2C
	205	----------------------------------------------------------------------/
211ea91a	206	#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
211ea91a SR	207
	208	#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */
	209	#define CFG_I2C_EEPROM_ADDR 0x52 /* I2C boot EEPROM (24C02BN) */
	210	#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
	211
	212	/* Standard DTT sensor configuration */
	213	#define CONFIG_DTT_DS1775 1
	214	#define CONFIG_DTT_SENSORS { 0 }
	215	#define CFG_I2C_DTT_ADDR 0x48
	216
	217	/* RTC configuration */
	218	#define CONFIG_RTC_X1205 1
	219	#define CFG_I2C_RTC_ADDR 0x6f
	220
	221	/*-----------------------------------------------------------------------
	222	* Ethernet
	223	----------------------------------------------------------------------/
	224	#define CONFIG_M88E1111_PHY 1
	225	#define CONFIG_IBM_EMAC4_V4 1
1740c1bf	226	#define CONFIG_EMAC_PHY_MODE EMAC_PHY_MODE_RGMII_RGMII
211ea91a SR	227	#define CONFIG_PHY_ADDR 6 /* PHY address, See schematics */
	228
	229	#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
	230	#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
	231
	232	#define CONFIG_HAS_ETH0 1
	233
211ea91a	234	#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
ecdcbd4f	235	#define CONFIG_PHY1_ADDR 0
211ea91a	236
490f2040 SR	237	/*
	238	* Default environment variables
	239	*/
211ea91a	240	#define CONFIG_EXTRA_ENV_SETTINGS \
490f2040 SR	241	CONFIG_AMCC_DEF_ENV \
	242	CONFIG_AMCC_DEF_ENV_POWERPC \
	243	CONFIG_AMCC_DEF_ENV_PPC_OLD \
	244	CONFIG_AMCC_DEF_ENV_NOR_UPD \
ecdcbd4f	245	"kernel_addr=fc000000\0" \
869d14b4	246	"fdt_addr=fc1e0000\0" \
ecdcbd4f	247	"ramdisk_addr=fc200000\0" \
211ea91a SR	248	"pciconfighost=1\0" \
	249	"pcie_mode=RP:RP\0" \
	250	""
211ea91a SR	251
211ea91a SR	252	/*
490f2040	253	* Commands additional to the ones defined in amcc-common.h
211ea91a	254	*/
211ea91a	255	#define CONFIG_CMD_DATE
211ea91a	256	#define CONFIG_CMD_DTT
211ea91a	257	#define CONFIG_CMD_LOG
211ea91a	258	#define CONFIG_CMD_PCI
afe9fa59	259	#define CONFIG_CMD_SNTP
211ea91a SR	260
211ea91a SR	261	/* POST support */
8a24c07b	262	#define CONFIG_POST (CFG_POST_CACHE \| \
211ea91a SR	263	CFG_POST_CPU \| \
	264	CFG_POST_ETHER \| \
	265	CFG_POST_I2C \| \
	266	CFG_POST_MEMORY \| \
	267	CFG_POST_UART)
	268
	269	/* Define here the base-addresses of the UARTs to test in POST */
	270	#define CFG_POST_UART_TABLE {UART0_BASE, UART1_BASE}
	271
	272	#define CONFIG_LOGBUFFER
	273	#define CFG_POST_CACHE_ADDR 0x00800000 /* free virtual address */
	274
	275	#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
	276
211ea91a SR	277	/*-----------------------------------------------------------------------
	278	* PCI stuff
	279	----------------------------------------------------------------------/
	280	#define CONFIG_PCI /* include pci support */
	281	#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
	282	#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
	283	#define CONFIG_PCI_CONFIG_HOST_BRIDGE
	284
	285	/*-----------------------------------------------------------------------
	286	* PCIe stuff
	287	----------------------------------------------------------------------/
	288	#define CFG_PCIE_MEMBASE 0x90000000 /* mapped PCIe memory */
	289	#define CFG_PCIE_MEMSIZE 0x08000000 /* 128 Meg, smallest incr per port */
	290
	291	#define CFG_PCIE0_CFGBASE 0xa0000000 /* remote access */
	292	#define CFG_PCIE0_XCFGBASE 0xb0000000 /* local access */
	293	#define CFG_PCIE0_CFGMASK 0xe0000001 /* 512 Meg */
	294
	295	#define CFG_PCIE1_CFGBASE 0xc0000000 /* remote access */
	296	#define CFG_PCIE1_XCFGBASE 0xd0000000 /* local access */
	297	#define CFG_PCIE1_CFGMASK 0xe0000001 /* 512 Meg */
	298
	299	#define CFG_PCIE0_UTLBASE 0xef502000
	300	#define CFG_PCIE1_UTLBASE 0xef503000
	301
	302	/* base address of inbound PCIe window */
	303	#define CFG_PCIE_INBOUND_BASE 0x0000000000000000ULL
	304
211ea91a SR	305	/*-----------------------------------------------------------------------
	306	* External Bus Controller (EBC) Setup
	307	----------------------------------------------------------------------/
	308	/* Memory Bank 0 (NOR-FLASH) initialization */
63362cfc	309	#define CFG_EBC_PB0AP 0x08033700
ecdcbd4f	310	#define CFG_EBC_PB0CR (CFG_FLASH_BASE \| 0xda000)
211ea91a SR	311
	312	/* Memory Bank 2 (CPLD) initialization */
	313	#define CFG_EBC_PB2AP 0x9400C800
	314	#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0x800,BS=1MB,BU=R/W,BW=8bit */
	315
	316	#define CFG_EBC_CFG 0x7FC00000 /* EBC0_CFG */
	317
	318	/*-----------------------------------------------------------------------
	319	* GPIO Setup
	320	----------------------------------------------------------------------/
ecdcbd4f SR	321	#define CFG_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
	322	{ \
	323	/* GPIO Core 0 */ \
	324	{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO0 EBC_DATA_PAR(0) */ \
	325	{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO1 EBC_DATA_PAR(1) */ \
	326	{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO2 EBC_DATA_PAR(2) */ \
	327	{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO3 EBC_DATA_PAR(3) */ \
7cfc12a7 SR	328	{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO4 EBC_DATA(20) USB2_DATA(4) */ \
	329	{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO5 EBC_DATA(21) USB2_DATA(5) */ \
	330	{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO6 EBC_DATA(22) USB2_DATA(6) */ \
	331	{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO7 EBC_DATA(23) USB2_DATA(7) */ \
8be76090 SR	332	{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 CS(1)/NFCE(1) IRQ(7) */ \
	333	{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 CS(2)/NFCE(2) IRQ(8) */ \
	334	{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 CS(3)/NFCE(3) IRQ(9) */ \
ecdcbd4f	335	{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 IRQ(6) */ \
7cfc12a7 SR	336	{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO12 EBC_DATA(16) USB2_DATA(0) */ \
	337	{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO13 EBC_DATA(17) USB2_DATA(1) */ \
	338	{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO14 EBC_DATA(18) USB2_DATA(2) */ \
	339	{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO15 EBC_DATA(19) USB2_DATA(3) */ \
ecdcbd4f SR	340	{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 UART0_DCD UART1_CTS */ \
	341	{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 UART0_DSR UART1_RTS */ \
	342	{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 UART0_CTS */ \
	343	{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 UART0_RTS */ \
	344	{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO20 UART0_DTR UART1_TX */ \
	345	{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO21 UART0_RI UART1_RX */ \
	346	{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO22 EBC_HOLD_REQ DMA_ACK2 */ \
	347	{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_0}, /* GPIO23 EBC_HOLD_ACK DMA_REQ2 */ \
	348	{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO24 EBC_EXT_REQ DMA_EOT2 IRQ(4) */ \
	349	{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO25 EBC_EXT_ACK DMA_ACK3 IRQ(3) */ \
	350	{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 EBC_ADDR(5) DMA_EOT0 TS(3) */ \
	351	{GPIO0_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EBC_BUS_REQ DMA_EOT3 IRQ(5) */ \
	352	{GPIO0_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO28 */ \
8be76090 SR	353	{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO29 DMA_EOT1 IRQ(2) */ \
	354	{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO30 DMA_REQ1 IRQ(1) */ \
	355	{GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0}, /* GPIO31 DMA_ACK1 IRQ(0) */ \
ecdcbd4f SR	356	} \
	357	}
	358
	359	#define CFG_GPIO_PCIE_RST 23
	360	#define CFG_GPIO_PCIE_CLKREQ 27
	361	#define CFG_GPIO_PCIE_WAKE 28
211ea91a	362
211ea91a	363	#endif /* __CONFIG_H */