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a4884831 SR |
1 | /* |
2 | * Copyright (C) 2014 Stefan Roese <sr@denx.de> | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
6 | ||
7 | #ifndef _CONFIG_DB_MV7846MP_GP_H | |
8 | #define _CONFIG_DB_MV7846MP_GP_H | |
9 | ||
10 | /* | |
11 | * High Level Configuration Options (easy to change) | |
12 | */ | |
a4884831 SR |
13 | #define CONFIG_DISPLAY_BOARDINFO_LATE |
14 | ||
2923c2d2 SR |
15 | /* |
16 | * TEXT_BASE needs to be below 16MiB, since this area is scrubbed | |
17 | * for DDR ECC byte filling in the SPL before loading the main | |
18 | * U-Boot into it. | |
19 | */ | |
a4884831 SR |
20 | #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ |
21 | ||
22 | /* | |
23 | * Commands configuration | |
24 | */ | |
a4884831 SR |
25 | |
26 | /* I2C */ | |
27 | #define CONFIG_SYS_I2C | |
28 | #define CONFIG_SYS_I2C_MVTWSI | |
dd82242b | 29 | #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE |
a4884831 SR |
30 | #define CONFIG_SYS_I2C_SLAVE 0x0 |
31 | #define CONFIG_SYS_I2C_SPEED 100000 | |
32 | ||
33 | /* SPI NOR flash default params, used by sf commands */ | |
34 | #define CONFIG_SF_DEFAULT_SPEED 1000000 | |
35 | #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 | |
a4884831 SR |
36 | |
37 | /* Environment in SPI NOR flash */ | |
a4884831 SR |
38 | #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ |
39 | #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ | |
40 | #define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ | |
41 | ||
42 | #define CONFIG_PHY_MARVELL /* there is a marvell phy */ | |
a4884831 | 43 | #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ |
a4884831 | 44 | |
a4884831 SR |
45 | #define CONFIG_SYS_ALT_MEMTEST |
46 | ||
47 | /* | |
48 | * mv-common.h should be defined after CMD configs since it used them | |
49 | * to enable certain macros | |
50 | */ | |
51 | #include "mv-common.h" | |
52 | ||
e7778ec1 SR |
53 | /* |
54 | * Memory layout while starting into the bin_hdr via the | |
55 | * BootROM: | |
56 | * | |
57 | * 0x4000.4000 - 0x4003.4000 headers space (192KiB) | |
58 | * 0x4000.4030 bin_hdr start address | |
59 | * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) | |
60 | * 0x4007.fffc BootROM stack top | |
61 | * | |
62 | * The address space between 0x4007.fffc and 0x400f.fff is not locked in | |
63 | * L2 cache thus cannot be used. | |
64 | */ | |
65 | ||
66 | /* SPL */ | |
67 | /* Defines for SPL */ | |
e7778ec1 SR |
68 | #define CONFIG_SPL_TEXT_BASE 0x40004030 |
69 | #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) | |
70 | ||
71 | #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) | |
72 | #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) | |
73 | ||
6451223a SR |
74 | #ifdef CONFIG_SPL_BUILD |
75 | #define CONFIG_SYS_MALLOC_SIMPLE | |
76 | #endif | |
e7778ec1 SR |
77 | |
78 | #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) | |
79 | #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) | |
80 | ||
e7778ec1 | 81 | /* SPL related SPI defines */ |
e7778ec1 | 82 | #define CONFIG_SPL_SPI_LOAD |
e7778ec1 SR |
83 | #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 |
84 | ||
85 | /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ | |
e7778ec1 | 86 | #define CONFIG_DDR_FIXED_SIZE (1 << 20) /* 1GiB */ |
698ffab2 | 87 | #define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */ |
e7778ec1 | 88 | |
a4884831 | 89 | #endif /* _CONFIG_DB_MV7846MP_GP_H */ |