[people/ms/u-boot.git] / include / configs / meesc.h

/*
 * (C) Copyright 2007-2008
 * Stelian Pop <stelian@popies.net>
 * Lead Tech Design <www.leadtechdesign.com>
 *
 * (C) Copyright 2009-2015
 * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
 * esd electronic system design gmbh <www.esd.eu>
 *
 * Configuation settings for the esd MEESC board.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * SoC must be defined first, before hardware.h is included.
 * In this case SoC is defined in boards.cfg.
 */
#include <asm/hardware.h>

/*
 * Warning: changing CONFIG_SYS_TEXT_BASE requires
 * adapting the initial boot program.
 * Since the linker has to swallow that define, we must use a pure
 * hex number here!
 */

/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_SLOW_CLOCK	32768	/* 32.768 kHz crystal */
#define CONFIG_SYS_AT91_MAIN_CLOCK	16000000/* 16.0 MHz crystal */

/* Misc CPU related */
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_SERIAL_TAG
#define CONFIG_REVISION_TAG
#define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
#define CONFIG_MISC_INIT_R			/* Call misc_init_r */

#define CONFIG_PREBOOT				/* enable preboot variable */

/*
 * Hardware drivers
 */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE

/*
 * SDRAM: 1 bank, min 32, max 128 MB
 * Initialized before u-boot gets started.
 */
#define PHYS_SDRAM					ATMEL_BASE_CS1 /* 0x20000000 */
#define PHYS_SDRAM_SIZE				0x02000000     /* 32 MByte */

#define CONFIG_NR_DRAM_BANKS		1
#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
#define CONFIG_SYS_SDRAM_SIZE		PHYS_SDRAM_SIZE

#define CONFIG_SYS_MEMTEST_START	(CONFIG_SYS_SDRAM_BASE + 0x00100000)
#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x01E00000)
#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x00100000)

/*
 * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM,
 * leaving the correct space for initial global data structure above
 * that address while providing maximum stack area below.
 */
#define CONFIG_SYS_INIT_SP_ADDR \
	(ATMEL_BASE_SRAM0 + 16 * 1024 - GENERATED_GBL_DATA_SIZE)

/* NAND flash */
#ifdef CONFIG_CMD_NAND
# define CONFIG_NAND_ATMEL
# define CONFIG_SYS_MAX_NAND_DEVICE		1
# define CONFIG_SYS_NAND_BASE			ATMEL_BASE_CS3 /* 0x40000000 */
# define CONFIG_SYS_NAND_DBW_8
# define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
# define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
# define CONFIG_SYS_NAND_ENABLE_PIN		GPIO_PIN_PD(15)
# define CONFIG_SYS_NAND_READY_PIN		GPIO_PIN_PA(22)
#endif

/* Ethernet */
#define CONFIG_MACB
#define CONFIG_RMII
#define CONFIG_NET_RETRY_COUNT			20
#undef CONFIG_RESET_PHY_R

/* hw-controller addresses */
#define CONFIG_ET1100_BASE		0x70000000

#ifdef CONFIG_SYS_USE_DATAFLASH

/* bootstrap + u-boot + env in dataflash on CS0 */
#define CONFIG_ENV_OFFSET	0x4200
#define CONFIG_ENV_SIZE		0x4200
#define CONFIG_ENV_SECT_SIZE	0x210
#define CONFIG_ENV_SPI_MAX_HZ	15000000

#elif CONFIG_SYS_USE_NANDFLASH

/* bootstrap + u-boot + env + linux in nandflash */
# define CONFIG_ENV_OFFSET		0xC0000
# define CONFIG_ENV_SIZE		0x20000

#endif

#define CONFIG_SYS_CBSIZE		512

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN		ROUND(3 * CONFIG_ENV_SIZE + \
					128*1024, 0x1000)

#endif
Commit	Line	Data
33b1d3f4 DG	1	/*
33b1d3f4 DG	2	* (C) Copyright 2007-2008
c9e798d3	3	* Stelian Pop <stelian@popies.net>
33b1d3f4 DG	4	* Lead Tech Design <www.leadtechdesign.com>
33b1d3f4 DG	5	*
83bf0057	6	* (C) Copyright 2009-2015
33b1d3f4 DG	7	* Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
	8	* esd electronic system design gmbh <www.esd.eu>
	9	*
	10	* Configuation settings for the esd MEESC board.
	11	*
1a459660	12	* SPDX-License-Identifier: GPL-2.0+
33b1d3f4 DG	13	*/
	14
	15	#ifndef __CONFIG_H
	16	#define __CONFIG_H
	17
0cb77bfa MF	18	/*
	19	* SoC must be defined first, before hardware.h is included.
	20	* In this case SoC is defined in boards.cfg.
	21	*/
	22	#include <asm/hardware.h>
	23
	24	/*
	25	* Warning: changing CONFIG_SYS_TEXT_BASE requires
	26	* adapting the initial boot program.
	27	* Since the linker has to swallow that define, we must use a pure
	28	* hex number here!
	29	*/
0cb77bfa MF	30
	31	/* ARM asynchronous clock */
	32	#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* 32.768 kHz crystal */
9f07dede	33	#define CONFIG_SYS_AT91_MAIN_CLOCK 16000000/* 16.0 MHz crystal */
33b1d3f4	34
0cb77bfa	35	/* Misc CPU related */
33b1d3f4	36	#define CONFIG_SKIP_LOWLEVEL_INIT
0cb77bfa	37	#define CONFIG_ARCH_CPU_INIT
0cb77bfa MF	38	#define CONFIG_SETUP_MEMORY_TAGS
	39	#define CONFIG_INITRD_TAG
	40	#define CONFIG_SERIAL_TAG
	41	#define CONFIG_REVISION_TAG
	42	#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
a3f3897b	43	#define CONFIG_MISC_INIT_R /* Call misc_init_r */
33b1d3f4	44
0cb77bfa	45	#define CONFIG_PREBOOT /* enable preboot variable */
33b1d3f4 DG	46
	47	/*
	48	* Hardware drivers
	49	*/
	50
33b1d3f4 DG	51	/*
	52	* BOOTP options
	53	*/
0cb77bfa	54	#define CONFIG_BOOTP_BOOTFILESIZE
33b1d3f4	55
0cb77bfa MF	56	/*
	57	* SDRAM: 1 bank, min 32, max 128 MB
	58	* Initialized before u-boot gets started.
	59	*/
83bf0057 DG	60	#define PHYS_SDRAM ATMEL_BASE_CS1 /* 0x20000000 */
	61	#define PHYS_SDRAM_SIZE 0x02000000 /* 32 MByte */
	62
0cb77bfa	63	#define CONFIG_NR_DRAM_BANKS 1
83bf0057 DG	64	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
83bf0057 DG	65	#define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_SIZE
0cb77bfa MF	66
	67	#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x00100000)
	68	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01E00000)
	69	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x00100000)
	70
	71	/*
	72	* Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM,
	73	* leaving the correct space for initial global data structure above
	74	* that address while providing maximum stack area below.
	75	*/
	76	#define CONFIG_SYS_INIT_SP_ADDR \
a818704b	77	(ATMEL_BASE_SRAM0 + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
33b1d3f4	78
33b1d3f4 DG	79	/* NAND flash */
33b1d3f4 DG	80	#ifdef CONFIG_CMD_NAND
0cb77bfa MF	81	# define CONFIG_NAND_ATMEL
0cb77bfa MF	82	# define CONFIG_SYS_MAX_NAND_DEVICE 1
83bf0057	83	# define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 /* 0x40000000 */
0cb77bfa MF	84	# define CONFIG_SYS_NAND_DBW_8
	85	# define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
	86	# define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
ac45bb16 AB	87	# define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15)
ac45bb16 AB	88	# define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PA(22)
33b1d3f4 DG	89	#endif
	90
	91	/* Ethernet */
0cb77bfa MF	92	#define CONFIG_MACB
0cb77bfa MF	93	#define CONFIG_RMII
33b1d3f4 DG	94	#define CONFIG_NET_RETRY_COUNT 20
	95	#undef CONFIG_RESET_PHY_R
	96
a380279b	97	/* hw-controller addresses */
0cb77bfa MF	98	#define CONFIG_ET1100_BASE 0x70000000
	99
	100	#ifdef CONFIG_SYS_USE_DATAFLASH
a380279b DG	101
a380279b DG	102	/* bootstrap + u-boot + env in dataflash on CS0 */
a818704b WY	103	#define CONFIG_ENV_OFFSET 0x4200
	104	#define CONFIG_ENV_SIZE 0x4200
	105	#define CONFIG_ENV_SECT_SIZE 0x210
	106	#define CONFIG_ENV_SPI_MAX_HZ 15000000
33b1d3f4	107
0cb77bfa MF	108	#elif CONFIG_SYS_USE_NANDFLASH
	109
	110	/* bootstrap + u-boot + env + linux in nandflash */
0cb77bfa MF	111	# define CONFIG_ENV_OFFSET 0xC0000
	112	# define CONFIG_ENV_SIZE 0x20000
	113
	114	#endif
33b1d3f4	115
0cb77bfa	116	#define CONFIG_SYS_CBSIZE 512
33b1d3f4 DG	117
	118	/*
	119	* Size of malloc() pool
	120	*/
a380279b DG	121	#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + \
a380279b DG	122	128*1024, 0x1000)
33b1d3f4	123
33b1d3f4	124	#endif