[people/ms/u-boot.git] / include / configs / microblaze-generic.h

/*
 * (C) Copyright 2007-2010 Michal Simek
 *
 * Michal SIMEK <monstr@monstr.eu>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#include "../board/xilinx/microblaze-generic/xparameters.h"

/* MicroBlaze CPU */
#define	MICROBLAZE_V5		1

/* linear and spi flash memory */
#ifdef XILINX_FLASH_START
#define	FLASH
#undef	SPIFLASH
#undef	RAMENV	/* hold environment in flash */
#else
#ifdef XILINX_SPI_FLASH_BASEADDR
#undef	FLASH
#define	SPIFLASH
#undef	RAMENV	/* hold environment in flash */
#else
#undef	FLASH
#undef	SPIFLASH
#define	RAMENV	/* hold environment in RAM */
#endif
#endif

/* uart */
#ifdef XILINX_UARTLITE_BASEADDR
# define CONFIG_XILINX_UARTLITE
# define CONFIG_SERIAL_BASE	XILINX_UARTLITE_BASEADDR
# define CONFIG_BAUDRATE	XILINX_UARTLITE_BAUDRATE
# define CONFIG_SYS_BAUDRATE_TABLE	{ CONFIG_BAUDRATE }
# define CONSOLE_ARG	"console=console=ttyUL0,115200\0"
#elif XILINX_UART16550_BASEADDR
# define CONFIG_SYS_NS16550_SERIAL
# if defined(__MICROBLAZEEL__)
#  define CONFIG_SYS_NS16550_REG_SIZE	-4
# else
#  define CONFIG_SYS_NS16550_REG_SIZE	4
# endif
# define CONFIG_CONS_INDEX		1
# define CONFIG_SYS_NS16550_COM1 \
		((XILINX_UART16550_BASEADDR & ~0xF) + 0x1000)
# define CONFIG_SYS_NS16550_CLK	XILINX_UART16550_CLOCK_HZ
# define CONFIG_BAUDRATE	115200

/* The following table includes the supported baudrates */
# define CONFIG_SYS_BAUDRATE_TABLE \
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
# define CONSOLE_ARG	"console=console=ttyS0,115200\0"
#else
# error Undefined uart
#endif

/* setting reset address */
/*#define	CONFIG_SYS_RESET_ADDRESS	CONFIG_SYS_TEXT_BASE*/

/* ethernet */
#undef CONFIG_SYS_ENET
#if defined(XILINX_EMACLITE_BASEADDR) || defined(CONFIG_OF_CONTROL)
# define CONFIG_XILINX_EMACLITE	1
# define CONFIG_SYS_ENET
#endif
#if defined(XILINX_LLTEMAC_BASEADDR)
# define CONFIG_XILINX_LL_TEMAC	1
# define CONFIG_SYS_ENET
#endif
#if defined(XILINX_AXIEMAC_BASEADDR)
# define CONFIG_XILINX_AXIEMAC	1
# define CONFIG_SYS_ENET
#endif

#undef ET_DEBUG

/* gpio */
#ifdef XILINX_GPIO_BASEADDR
# define CONFIG_XILINX_GPIO
# define CONFIG_SYS_GPIO_0_ADDR		XILINX_GPIO_BASEADDR
#endif

/* interrupt controller */
#ifdef XILINX_INTC_BASEADDR
# define CONFIG_SYS_INTC_0_ADDR		XILINX_INTC_BASEADDR
# define CONFIG_SYS_INTC_0_NUM		XILINX_INTC_NUM_INTR_INPUTS
#endif

/* timer */
#if defined(XILINX_TIMER_BASEADDR) && defined(XILINX_TIMER_IRQ)
#  define CONFIG_SYS_TIMER_0_ADDR	XILINX_TIMER_BASEADDR
#  define CONFIG_SYS_TIMER_0_IRQ	XILINX_TIMER_IRQ
#endif

/* watchdog */
#if defined(XILINX_WATCHDOG_BASEADDR) && defined(XILINX_WATCHDOG_IRQ)
# define CONFIG_WATCHDOG_BASEADDR	XILINX_WATCHDOG_BASEADDR
# define CONFIG_WATCHDOG_IRQ		XILINX_WATCHDOG_IRQ
# define CONFIG_HW_WATCHDOG
# define CONFIG_XILINX_TB_WATCHDOG
#endif

#if !defined(CONFIG_OF_CONTROL) || \
	(defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_OF_CONTROL))
/* ddr sdram - main memory */
# define CONFIG_SYS_SDRAM_BASE	XILINX_RAM_START
# define CONFIG_SYS_SDRAM_SIZE	XILINX_RAM_SIZE
#endif

#define CONFIG_SYS_MALLOC_LEN	0xC0000
#ifndef CONFIG_SPL_BUILD
# define CONFIG_SYS_MALLOC_F_LEN	1024
#else
# define CONFIG_SYS_MALLOC_SIMPLE
# define CONFIG_SYS_MALLOC_F_LEN	0x150
#endif

/* Stack location before relocation */
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_TEXT_BASE

/*
 * CFI flash memory layout - Example
 * CONFIG_SYS_FLASH_BASE = 0x2200_0000;
 * CONFIG_SYS_FLASH_SIZE = 0x0080_0000;	  8MB
 *
 * SECT_SIZE = 0x20000;			128kB is one sector
 * CONFIG_ENV_SIZE = SECT_SIZE;		128kB environment store
 *
 * 0x2200_0000	CONFIG_SYS_FLASH_BASE
 *					FREE		256kB
 * 0x2204_0000	CONFIG_ENV_ADDR
 *					ENV_AREA	128kB
 * 0x2206_0000
 *					FREE
 * 0x2280_0000	CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE
 *
 */

#ifdef FLASH
# define CONFIG_SYS_FLASH_BASE		XILINX_FLASH_START
# define CONFIG_SYS_FLASH_SIZE		XILINX_FLASH_SIZE
# define CONFIG_SYS_FLASH_CFI		1
# define CONFIG_FLASH_CFI_DRIVER	1
/* ?empty sector */
# define CONFIG_SYS_FLASH_EMPTY_INFO	1
/* max number of memory banks */
# define CONFIG_SYS_MAX_FLASH_BANKS	1
/* max number of sectors on one chip */
# define CONFIG_SYS_MAX_FLASH_SECT	512
/* hardware flash protection */
# define CONFIG_SYS_FLASH_PROTECTION
/* use buffered writes (20x faster) */
# define	CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
# ifdef	RAMENV
#  define CONFIG_ENV_IS_NOWHERE	1
#  define CONFIG_ENV_SIZE	0x1000
#  define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)

# else	/* FLASH && !RAMENV */
#  define CONFIG_ENV_IS_IN_FLASH	1
/* 128K(one sector) for env */
#  define CONFIG_ENV_SECT_SIZE	0x20000
#  define CONFIG_ENV_ADDR \
			(CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
#  define CONFIG_ENV_SIZE	0x20000
# endif /* FLASH && !RAMBOOT */
#else /* !FLASH */

#ifdef SPIFLASH
# define CONFIG_SYS_NO_FLASH		1
# define CONFIG_SYS_SPI_BASE		XILINX_SPI_FLASH_BASEADDR
# define CONFIG_SPI			1
# define CONFIG_SF_DEFAULT_MODE		SPI_MODE_3
# define CONFIG_SF_DEFAULT_SPEED	XILINX_SPI_FLASH_MAX_FREQ
# define CONFIG_SF_DEFAULT_CS		XILINX_SPI_FLASH_CS

# ifdef	RAMENV
#  define CONFIG_ENV_IS_NOWHERE	1
#  define CONFIG_ENV_SIZE	0x1000
#  define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)

# else	/* SPIFLASH && !RAMENV */
#  define CONFIG_ENV_IS_IN_SPI_FLASH	1
#  define CONFIG_ENV_SPI_MODE		SPI_MODE_3
#  define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SF_DEFAULT_SPEED
#  define CONFIG_ENV_SPI_CS		CONFIG_SF_DEFAULT_CS
/* 128K(two sectors) for env */
#  define CONFIG_ENV_SECT_SIZE	0x10000
#  define CONFIG_ENV_SIZE	(2 * CONFIG_ENV_SECT_SIZE)
/* Warning: adjust the offset in respect of other flash content and size */
#  define CONFIG_ENV_OFFSET	(128 * CONFIG_ENV_SECT_SIZE) /* at 8MB */
# endif /* SPIFLASH && !RAMBOOT */
#else /* !SPIFLASH */

/* ENV in RAM */
# define CONFIG_SYS_NO_FLASH	1
# define CONFIG_ENV_IS_NOWHERE	1
# define CONFIG_ENV_SIZE	0x1000
# define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
#endif /* !SPIFLASH */
#endif /* !FLASH */

/* system ace */
#ifdef XILINX_SYSACE_BASEADDR
# define CONFIG_SYSTEMACE
/* #define DEBUG_SYSTEMACE */
# define SYSTEMACE_CONFIG_FPGA
# define CONFIG_SYS_SYSTEMACE_BASE	XILINX_SYSACE_BASEADDR
# define CONFIG_SYS_SYSTEMACE_WIDTH	XILINX_SYSACE_MEM_WIDTH
# define CONFIG_DOS_PARTITION
#endif

#if defined(XILINX_USE_ICACHE)
# define CONFIG_ICACHE
#else
# undef CONFIG_ICACHE
#endif

#if defined(XILINX_USE_DCACHE)
# define CONFIG_DCACHE
#else
# undef CONFIG_DCACHE
#endif

#ifndef XILINX_DCACHE_BYTE_SIZE
#define XILINX_DCACHE_BYTE_SIZE	32768
#endif

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/*
 * Command line configuration.
 */
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_MFSL

#if defined(CONFIG_DCACHE) || defined(CONFIG_ICACHE)
# define CONFIG_CMD_CACHE
#else
# undef CONFIG_CMD_CACHE
#endif

#ifdef CONFIG_SYS_ENET
# define CONFIG_CMD_PING
# define CONFIG_CMD_DHCP
# define CONFIG_CMD_TFTPPUT
#endif

#if defined(CONFIG_SYSTEMACE)
# define CONFIG_CMD_EXT2
# define CONFIG_CMD_FAT
#endif

#if defined(FLASH)
# define CONFIG_CMD_JFFS2
# define CONFIG_CMD_UBI
# undef CONFIG_CMD_UBIFS

# if !defined(RAMENV)
#  define CONFIG_CMD_SAVES
# endif

#else
#if defined(SPIFLASH)
# define CONFIG_CMD_SF

# if !defined(RAMENV)
#  define CONFIG_CMD_SAVES
# endif
#else
# undef CONFIG_CMD_JFFS2
# undef CONFIG_CMD_UBI
# undef CONFIG_CMD_UBIFS
#endif
#endif

#if defined(CONFIG_CMD_JFFS2)
# define CONFIG_MTD_PARTITIONS
#endif

#if defined(CONFIG_CMD_UBIFS)
# define CONFIG_CMD_UBI
# define CONFIG_LZO
#endif

#if defined(CONFIG_CMD_UBI)
# define CONFIG_MTD_PARTITIONS
# define CONFIG_RBTREE
#endif

#if defined(CONFIG_MTD_PARTITIONS)
/* MTD partitions */
#define CONFIG_CMD_MTDPARTS	/* mtdparts command line support */
#define CONFIG_MTD_DEVICE	/* needed for mtdparts commands */
#define CONFIG_FLASH_CFI_MTD
#define MTDIDS_DEFAULT		"nor0=flash-0"

/* default mtd partition table */
#define MTDPARTS_DEFAULT	"mtdparts=flash-0:256k(u-boot),"\
				"256k(env),3m(kernel),1m(romfs),"\
				"1m(cramfs),-(jffs2)"
#endif

/* size of console buffer */
#define	CONFIG_SYS_CBSIZE	512
 /* print buffer size */
#define	CONFIG_SYS_PBSIZE \
		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
/* max number of command args */
#define	CONFIG_SYS_MAXARGS	15
#define	CONFIG_SYS_LONGHELP
/* default load address */
#define	CONFIG_SYS_LOAD_ADDR	XILINX_RAM_START

#define	CONFIG_BOOTDELAY	-1	/* -1 disables auto-boot */
#define	CONFIG_BOOTARGS		"root=romfs"
#define	CONFIG_HOSTNAME		XILINX_BOARD_NAME
#define	CONFIG_BOOTCOMMAND	"base 0;tftp 11000000 image.img;bootm"
#define	CONFIG_IPADDR		192.168.0.3
#define	CONFIG_SERVERIP		192.168.0.5
#define	CONFIG_GATEWAYIP	192.168.0.1

/* architecture dependent code */
#define	CONFIG_SYS_USR_EXCEP	/* user exception */

#define	CONFIG_PREBOOT	"echo U-BOOT for ${hostname};setenv preboot;echo"

#define	CONFIG_EXTRA_ENV_SETTINGS	"unlock=yes\0" \
					"nor0=flash-0\0"\
					"mtdparts=mtdparts=flash-0:"\
					"256k(u-boot),256k(env),3m(kernel),"\
					"1m(romfs),1m(cramfs),-(jffs2)\0"\
					"nc=setenv stdout nc;"\
					"setenv stdin nc\0" \
					"serial=setenv stdout serial;"\
					"setenv stdin serial\0"

#define CONFIG_CMDLINE_EDITING

#define CONFIG_NETCONSOLE
#define CONFIG_SYS_CONSOLE_IS_IN_ENV

/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER

/* Enable flat device tree support */
#define CONFIG_LMB		1
#define CONFIG_FIT		1
#define CONFIG_OF_LIBFDT	1

#if defined(CONFIG_XILINX_LL_TEMAC) || defined(CONFIG_XILINX_AXIEMAC)
# define CONFIG_MII		1
# define CONFIG_CMD_MII		1
# define CONFIG_PHY_GIGE	1
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN	1
# define CONFIG_PHYLIB		1
# define CONFIG_PHY_ATHEROS	1
# define CONFIG_PHY_BROADCOM	1
# define CONFIG_PHY_DAVICOM	1
# define CONFIG_PHY_LXT		1
# define CONFIG_PHY_MARVELL	1
# define CONFIG_PHY_MICREL	1
# define CONFIG_PHY_NATSEMI	1
# define CONFIG_PHY_REALTEK	1
# define CONFIG_PHY_VITESSE	1
#else
# undef CONFIG_MII
# undef CONFIG_CMD_MII
# undef CONFIG_PHYLIB
#endif

/* SPL part */
#define CONFIG_CMD_SPL
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_BOARD_INIT

#define CONFIG_SPL_LDSCRIPT	"arch/microblaze/cpu/u-boot-spl.lds"

#define CONFIG_SPL_RAM_DEVICE
#ifdef CONFIG_SYS_FLASH_BASE
# define CONFIG_SPL_NOR_SUPPORT
# define CONFIG_SYS_UBOOT_BASE		CONFIG_SYS_FLASH_BASE
#endif

/* for booting directly linux */
#define CONFIG_SPL_OS_BOOT

#define CONFIG_SYS_OS_BASE		(CONFIG_SYS_FLASH_BASE + \
					 0x60000)
#define CONFIG_SYS_FDT_BASE		(CONFIG_SYS_FLASH_BASE + \
					 0x40000)
#define CONFIG_SYS_SPL_ARGS_ADDR	(CONFIG_SYS_TEXT_BASE + \
					 0x1000000)

/* SP location before relocation, must use scratch RAM */
/* BRAM start */
#define CONFIG_SYS_INIT_RAM_ADDR	0x0
/* BRAM size - will be generated */
#define CONFIG_SYS_INIT_RAM_SIZE	0x100000

# define CONFIG_SPL_STACK_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - \
					 CONFIG_SYS_MALLOC_F_LEN)

/* Just for sure that there is a space for stack */
#define CONFIG_SPL_STACK_SIZE		0x100

#define CONFIG_SYS_UBOOT_START		CONFIG_SYS_TEXT_BASE

#define CONFIG_SPL_MAX_FOOTPRINT	(CONFIG_SYS_INIT_RAM_SIZE - \
					 CONFIG_SYS_INIT_RAM_ADDR - \
					 CONFIG_SYS_MALLOC_F_LEN - \
					 CONFIG_SPL_STACK_SIZE)

#endif	/* __CONFIG_H */
Commit	Line	Data
76316a31	1	/*
4aecfb16	2	* (C) Copyright 2007-2010 Michal Simek
76316a31	3	*
cb1bc63b	4	* Michal SIMEK <monstr@monstr.eu>
76316a31	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
76316a31 MS	7	*/
	8
	9	#ifndef __CONFIG_H
	10	#define __CONFIG_H
	11
52a822ed	12	#include "../board/xilinx/microblaze-generic/xparameters.h"
76316a31	13
4aecfb16	14	/* MicroBlaze CPU */
1a50f164	15	#define MICROBLAZE_V5 1
76316a31	16
bcec8f49	17	/* linear and spi flash memory */
1fe7e8fa SL	18	#ifdef XILINX_FLASH_START
1fe7e8fa SL	19	#define FLASH
bcec8f49	20	#undef SPIFLASH
1fe7e8fa SL	21	#undef RAMENV /* hold environment in flash */
1fe7e8fa SL	22	#else
bcec8f49	23	#ifdef XILINX_SPI_FLASH_BASEADDR
1fe7e8fa	24	#undef FLASH
bcec8f49 SL	25	#define SPIFLASH
	26	#undef RAMENV /* hold environment in flash */
	27	#else
	28	#undef FLASH
	29	#undef SPIFLASH
1fe7e8fa SL	30	#define RAMENV /* hold environment in RAM */
1fe7e8fa SL	31	#endif
bcec8f49	32	#endif
1fe7e8fa	33
76316a31	34	/* uart */
af7ae1a4	35	#ifdef XILINX_UARTLITE_BASEADDR
4aecfb16 MS	36	# define CONFIG_XILINX_UARTLITE
	37	# define CONFIG_SERIAL_BASE XILINX_UARTLITE_BASEADDR
	38	# define CONFIG_BAUDRATE XILINX_UARTLITE_BAUDRATE
	39	# define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE }
	40	# define CONSOLE_ARG "console=console=ttyUL0,115200\0"
e7d591e8	41	#elif XILINX_UART16550_BASEADDR
4aecfb16	42	# define CONFIG_SYS_NS16550_SERIAL
1de55ef1 SL	43	# if defined(__MICROBLAZEEL__)
	44	# define CONFIG_SYS_NS16550_REG_SIZE -4
	45	# else
	46	# define CONFIG_SYS_NS16550_REG_SIZE 4
	47	# endif
4aecfb16 MS	48	# define CONFIG_CONS_INDEX 1
4aecfb16 MS	49	# define CONFIG_SYS_NS16550_COM1 \
1de55ef1	50	((XILINX_UART16550_BASEADDR & ~0xF) + 0x1000)
4aecfb16 MS	51	# define CONFIG_SYS_NS16550_CLK XILINX_UART16550_CLOCK_HZ
	52	# define CONFIG_BAUDRATE 115200
	53
	54	/* The following table includes the supported baudrates */
	55	# define CONFIG_SYS_BAUDRATE_TABLE \
	56	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
	57	# define CONSOLE_ARG "console=console=ttyS0,115200\0"
e7d591e8	58	#else
4aecfb16	59	# error Undefined uart
af7ae1a4	60	#endif
76316a31 MS	61
76316a31 MS	62	/* setting reset address */
14d0a02a	63	/#define CONFIG_SYS_RESET_ADDRESS CONFIG_SYS_TEXT_BASE/
76316a31	64
17980495	65	/* ethernet */
1252df06	66	#undef CONFIG_SYS_ENET
d1d37b5c	67	#if defined(XILINX_EMACLITE_BASEADDR) \|\| defined(CONFIG_OF_CONTROL)
8422a35e	68	# define CONFIG_XILINX_EMACLITE 1
4aecfb16	69	# define CONFIG_SYS_ENET
8422a35e SL	70	#endif
	71	#if defined(XILINX_LLTEMAC_BASEADDR)
	72	# define CONFIG_XILINX_LL_TEMAC 1
4aecfb16	73	# define CONFIG_SYS_ENET
e5845e21	74	#endif
e634138e MS	75	#if defined(XILINX_AXIEMAC_BASEADDR)
	76	# define CONFIG_XILINX_AXIEMAC 1
	77	# define CONFIG_SYS_ENET
	78	#endif
330e5545	79
e5845e21	80	#undef ET_DEBUG
17980495	81
76316a31	82	/* gpio */
4c6a6f02	83	#ifdef XILINX_GPIO_BASEADDR
4e779ad2	84	# define CONFIG_XILINX_GPIO
4aecfb16	85	# define CONFIG_SYS_GPIO_0_ADDR XILINX_GPIO_BASEADDR
4c6a6f02	86	#endif
76316a31 MS	87
76316a31 MS	88	/* interrupt controller */
4d49b280	89	#ifdef XILINX_INTC_BASEADDR
4aecfb16 MS	90	# define CONFIG_SYS_INTC_0_ADDR XILINX_INTC_BASEADDR
4aecfb16 MS	91	# define CONFIG_SYS_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS
4d49b280	92	#endif
76316a31 MS	93
76316a31 MS	94	/* timer */
bcbb046b	95	#if defined(XILINX_TIMER_BASEADDR) && defined(XILINX_TIMER_IRQ)
4aecfb16 MS	96	# define CONFIG_SYS_TIMER_0_ADDR XILINX_TIMER_BASEADDR
4aecfb16 MS	97	# define CONFIG_SYS_TIMER_0_IRQ XILINX_TIMER_IRQ
4d49b280	98	#endif
bcbb046b	99
0f21f98d MS	100	/* watchdog */
	101	#if defined(XILINX_WATCHDOG_BASEADDR) && defined(XILINX_WATCHDOG_IRQ)
	102	# define CONFIG_WATCHDOG_BASEADDR XILINX_WATCHDOG_BASEADDR
	103	# define CONFIG_WATCHDOG_IRQ XILINX_WATCHDOG_IRQ
	104	# define CONFIG_HW_WATCHDOG
	105	# define CONFIG_XILINX_TB_WATCHDOG
	106	#endif
	107
0f925822 MY	108	#if !defined(CONFIG_OF_CONTROL) \|\| \
0f925822 MY	109	(defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_OF_CONTROL))
76316a31	110	/* ddr sdram - main memory */
e945f6dc MS	111	# define CONFIG_SYS_SDRAM_BASE XILINX_RAM_START
	112	# define CONFIG_SYS_SDRAM_SIZE XILINX_RAM_SIZE
	113	#endif
	114
	115	#define CONFIG_SYS_MALLOC_LEN 0xC0000
ca7d2266 MS	116	#ifndef CONFIG_SPL_BUILD
	117	# define CONFIG_SYS_MALLOC_F_LEN 1024
	118	#else
	119	# define CONFIG_SYS_MALLOC_SIMPLE
	120	# define CONFIG_SYS_MALLOC_F_LEN 0x150
	121	#endif
e945f6dc MS	122
	123	/* Stack location before relocation */
	124	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_TEXT_BASE
76316a31	125
8f371b18 SL	126	/*
	127	* CFI flash memory layout - Example
	128	* CONFIG_SYS_FLASH_BASE = 0x2200_0000;
	129	* CONFIG_SYS_FLASH_SIZE = 0x0080_0000; 8MB
	130	*
	131	* SECT_SIZE = 0x20000; 128kB is one sector
	132	* CONFIG_ENV_SIZE = SECT_SIZE; 128kB environment store
	133	*
	134	* 0x2200_0000 CONFIG_SYS_FLASH_BASE
	135	* FREE 256kB
	136	* 0x2204_0000 CONFIG_ENV_ADDR
	137	* ENV_AREA 128kB
	138	* 0x2206_0000
	139	* FREE
	140	* 0x2280_0000 CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE
	141	*
	142	*/
	143
76316a31	144	#ifdef FLASH
4aecfb16 MS	145	# define CONFIG_SYS_FLASH_BASE XILINX_FLASH_START
	146	# define CONFIG_SYS_FLASH_SIZE XILINX_FLASH_SIZE
	147	# define CONFIG_SYS_FLASH_CFI 1
	148	# define CONFIG_FLASH_CFI_DRIVER 1
	149	/* ?empty sector */
	150	# define CONFIG_SYS_FLASH_EMPTY_INFO 1
	151	/* max number of memory banks */
	152	# define CONFIG_SYS_MAX_FLASH_BANKS 1
	153	/* max number of sectors on one chip */
	154	# define CONFIG_SYS_MAX_FLASH_SECT 512
	155	/* hardware flash protection */
	156	# define CONFIG_SYS_FLASH_PROTECTION
22ff7f4d MS	157	/* use buffered writes (20x faster) */
22ff7f4d MS	158	# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
4aecfb16 MS	159	# ifdef RAMENV
	160	# define CONFIG_ENV_IS_NOWHERE 1
	161	# define CONFIG_ENV_SIZE 0x1000
	162	# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
	163
bcec8f49	164	# else /* FLASH && !RAMENV */
4aecfb16 MS	165	# define CONFIG_ENV_IS_IN_FLASH 1
	166	/* 128K(one sector) for env */
	167	# define CONFIG_ENV_SECT_SIZE 0x20000
	168	# define CONFIG_ENV_ADDR \
	169	(CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
	170	# define CONFIG_ENV_SIZE 0x20000
bcec8f49	171	# endif /* FLASH && !RAMBOOT */
76316a31	172	#else /* !FLASH */
bcec8f49 SL	173
	174	#ifdef SPIFLASH
	175	# define CONFIG_SYS_NO_FLASH 1
	176	# define CONFIG_SYS_SPI_BASE XILINX_SPI_FLASH_BASEADDR
bcec8f49	177	# define CONFIG_SPI 1
bcec8f49 SL	178	# define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
	179	# define CONFIG_SF_DEFAULT_SPEED XILINX_SPI_FLASH_MAX_FREQ
	180	# define CONFIG_SF_DEFAULT_CS XILINX_SPI_FLASH_CS
	181
	182	# ifdef RAMENV
	183	# define CONFIG_ENV_IS_NOWHERE 1
	184	# define CONFIG_ENV_SIZE 0x1000
	185	# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
	186
	187	# else /* SPIFLASH && !RAMENV */
	188	# define CONFIG_ENV_IS_IN_SPI_FLASH 1
	189	# define CONFIG_ENV_SPI_MODE SPI_MODE_3
	190	# define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
	191	# define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
	192	/* 128K(two sectors) for env */
	193	# define CONFIG_ENV_SECT_SIZE 0x10000
	194	# define CONFIG_ENV_SIZE (2 * CONFIG_ENV_SECT_SIZE)
	195	/* Warning: adjust the offset in respect of other flash content and size */
	196	# define CONFIG_ENV_OFFSET (128 * CONFIG_ENV_SECT_SIZE) /* at 8MB */
	197	# endif /* SPIFLASH && !RAMBOOT */
	198	#else /* !SPIFLASH */
	199
4aecfb16 MS	200	/* ENV in RAM */
	201	# define CONFIG_SYS_NO_FLASH 1
	202	# define CONFIG_ENV_IS_NOWHERE 1
	203	# define CONFIG_ENV_SIZE 0x1000
	204	# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
bcec8f49	205	#endif /* !SPIFLASH */
76316a31 MS	206	#endif /* !FLASH */
76316a31 MS	207
853643d8 MS	208	/* system ace */
853643d8 MS	209	#ifdef XILINX_SYSACE_BASEADDR
4aecfb16 MS	210	# define CONFIG_SYSTEMACE
	211	/* #define DEBUG_SYSTEMACE */
	212	# define SYSTEMACE_CONFIG_FPGA
	213	# define CONFIG_SYS_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR
	214	# define CONFIG_SYS_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH
	215	# define CONFIG_DOS_PARTITION
853643d8 MS	216	#endif
853643d8 MS	217
e9b737de	218	#if defined(XILINX_USE_ICACHE)
4aecfb16	219	# define CONFIG_ICACHE
e9b737de	220	#else
4aecfb16	221	# undef CONFIG_ICACHE
e9b737de MS	222	#endif
	223
	224	#if defined(XILINX_USE_DCACHE)
4aecfb16	225	# define CONFIG_DCACHE
e9b737de	226	#else
4aecfb16	227	# undef CONFIG_DCACHE
e9b737de MS	228	#endif
e9b737de MS	229
5811830f MS	230	#ifndef XILINX_DCACHE_BYTE_SIZE
	231	#define XILINX_DCACHE_BYTE_SIZE 32768
	232	#endif
	233
079a136c JL	234	/*
	235	* BOOTP options
	236	*/
	237	#define CONFIG_BOOTP_BOOTFILESIZE
	238	#define CONFIG_BOOTP_BOOTPATH
	239	#define CONFIG_BOOTP_GATEWAY
	240	#define CONFIG_BOOTP_HOSTNAME
76316a31	241
5dc11a51 JL	242	/*
	243	* Command line configuration.
	244	*/
5dc11a51	245	#define CONFIG_CMD_ASKENV
5dc11a51	246	#define CONFIG_CMD_IRQ
5dc11a51	247	#define CONFIG_CMD_MFSL
4d49b280	248
e9b737de	249	#if defined(CONFIG_DCACHE) \|\| defined(CONFIG_ICACHE)
4aecfb16	250	# define CONFIG_CMD_CACHE
e9b737de	251	#else
4aecfb16	252	# undef CONFIG_CMD_CACHE
e9b737de MS	253	#endif
e9b737de MS	254
ef0f2f57	255	#ifdef CONFIG_SYS_ENET
4aecfb16 MS	256	# define CONFIG_CMD_PING
4aecfb16 MS	257	# define CONFIG_CMD_DHCP
4eb29cf0	258	# define CONFIG_CMD_TFTPPUT
4d49b280	259	#endif
853643d8 MS	260
853643d8 MS	261	#if defined(CONFIG_SYSTEMACE)
4aecfb16 MS	262	# define CONFIG_CMD_EXT2
4aecfb16 MS	263	# define CONFIG_CMD_FAT
853643d8	264	#endif
5dc11a51 JL	265
5dc11a51 JL	266	#if defined(FLASH)
4aecfb16	267	# define CONFIG_CMD_JFFS2
7cfb13a7 SL	268	# define CONFIG_CMD_UBI
7cfb13a7 SL	269	# undef CONFIG_CMD_UBIFS
4aecfb16	270
bcec8f49	271	# if !defined(RAMENV)
bcec8f49 SL	272	# define CONFIG_CMD_SAVES
	273	# endif
	274
	275	#else
	276	#if defined(SPIFLASH)
	277	# define CONFIG_CMD_SF
	278
4aecfb16	279	# if !defined(RAMENV)
4aecfb16 MS	280	# define CONFIG_CMD_SAVES
4aecfb16 MS	281	# endif
853643d8	282	#else
4aecfb16	283	# undef CONFIG_CMD_JFFS2
2cce2d32 SL	284	# undef CONFIG_CMD_UBI
2cce2d32 SL	285	# undef CONFIG_CMD_UBIFS
5dc11a51	286	#endif
bcec8f49	287	#endif
76316a31	288
5dc11a51	289	#if defined(CONFIG_CMD_JFFS2)
7cfb13a7 SL	290	# define CONFIG_MTD_PARTITIONS
	291	#endif
	292
	293	#if defined(CONFIG_CMD_UBIFS)
	294	# define CONFIG_CMD_UBI
	295	# define CONFIG_LZO
	296	#endif
	297
	298	#if defined(CONFIG_CMD_UBI)
	299	# define CONFIG_MTD_PARTITIONS
	300	# define CONFIG_RBTREE
	301	#endif
	302
	303	#if defined(CONFIG_MTD_PARTITIONS)
	304	/* MTD partitions */
68d7d651	305	#define CONFIG_CMD_MTDPARTS /* mtdparts command line support */
942556a9 SR	306	#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
942556a9 SR	307	#define CONFIG_FLASH_CFI_MTD
c82a541d	308	#define MTDIDS_DEFAULT "nor0=flash-0"
144876a3 MS	309
144876a3 MS	310	/* default mtd partition table */
c82a541d	311	#define MTDPARTS_DEFAULT "mtdparts=flash-0:256k(u-boot),"\
144876a3 MS	312	"256k(env),3m(kernel),1m(romfs),"\
	313	"1m(cramfs),-(jffs2)"
	314	#endif
	315
4aecfb16 MS	316	/* size of console buffer */
	317	#define CONFIG_SYS_CBSIZE 512
	318	/* print buffer size */
	319	#define CONFIG_SYS_PBSIZE \
	320	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
	321	/* max number of command args */
	322	#define CONFIG_SYS_MAXARGS 15
6d0f6bcf	323	#define CONFIG_SYS_LONGHELP
4aecfb16 MS	324	/* default load address */
4aecfb16 MS	325	#define CONFIG_SYS_LOAD_ADDR XILINX_RAM_START
76316a31	326
330e5545	327	#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */
76316a31	328	#define CONFIG_BOOTARGS "root=romfs"
330e5545	329	#define CONFIG_HOSTNAME XILINX_BOARD_NAME
853643d8	330	#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm"
76316a31	331	#define CONFIG_IPADDR 192.168.0.3
853643d8 MS	332	#define CONFIG_SERVERIP 192.168.0.5
853643d8 MS	333	#define CONFIG_GATEWAYIP 192.168.0.1
76316a31 MS	334
76316a31 MS	335	/* architecture dependent code */
6d0f6bcf	336	#define CONFIG_SYS_USR_EXCEP /* user exception */
76316a31	337
0900bee9	338	#define CONFIG_PREBOOT "echo U-BOOT for ${hostname};setenv preboot;echo"
144876a3	339
4aecfb16	340	#define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" \
c82a541d SL	341	"nor0=flash-0\0"\
c82a541d SL	342	"mtdparts=mtdparts=flash-0:"\
144876a3	343	"256k(u-boot),256k(env),3m(kernel),"\
78376452 MS	344	"1m(romfs),1m(cramfs),-(jffs2)\0"\
	345	"nc=setenv stdout nc;"\
	346	"setenv stdin nc\0" \
	347	"serial=setenv stdout serial;"\
	348	"setenv stdin serial\0"
144876a3	349
188dc16b	350	#define CONFIG_CMDLINE_EDITING
188dc16b	351
78376452 MS	352	#define CONFIG_NETCONSOLE
	353	#define CONFIG_SYS_CONSOLE_IS_IN_ENV
	354
0900bee9 MS	355	/* Use the HUSH parser */
0900bee9 MS	356	#define CONFIG_SYS_HUSH_PARSER
0900bee9	357
37e892d9 MS	358	/* Enable flat device tree support */
	359	#define CONFIG_LMB 1
	360	#define CONFIG_FIT 1
	361	#define CONFIG_OF_LIBFDT 1
	362
8422a35e	363	#if defined(CONFIG_XILINX_LL_TEMAC) \|\| defined(CONFIG_XILINX_AXIEMAC)
f5e5e1ff SL	364	# define CONFIG_MII 1
	365	# define CONFIG_CMD_MII 1
	366	# define CONFIG_PHY_GIGE 1
	367	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1
	368	# define CONFIG_PHYLIB 1
	369	# define CONFIG_PHY_ATHEROS 1
	370	# define CONFIG_PHY_BROADCOM 1
	371	# define CONFIG_PHY_DAVICOM 1
	372	# define CONFIG_PHY_LXT 1
	373	# define CONFIG_PHY_MARVELL 1
	374	# define CONFIG_PHY_MICREL 1
	375	# define CONFIG_PHY_NATSEMI 1
	376	# define CONFIG_PHY_REALTEK 1
	377	# define CONFIG_PHY_VITESSE 1
	378	#else
	379	# undef CONFIG_MII
	380	# undef CONFIG_CMD_MII
	381	# undef CONFIG_PHYLIB
	382	#endif
	383
9d242745	384	/* SPL part */
9d242745 MS	385	#define CONFIG_CMD_SPL
	386	#define CONFIG_SPL_FRAMEWORK
	387	#define CONFIG_SPL_LIBCOMMON_SUPPORT
	388	#define CONFIG_SPL_LIBGENERIC_SUPPORT
	389	#define CONFIG_SPL_SERIAL_SUPPORT
	390	#define CONFIG_SPL_BOARD_INIT
	391
	392	#define CONFIG_SPL_LDSCRIPT "arch/microblaze/cpu/u-boot-spl.lds"
	393
	394	#define CONFIG_SPL_RAM_DEVICE
4dd09742 MS	395	#ifdef CONFIG_SYS_FLASH_BASE
	396	# define CONFIG_SPL_NOR_SUPPORT
	397	# define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_FLASH_BASE
	398	#endif
9d242745 MS	399
	400	/* for booting directly linux */
	401	#define CONFIG_SPL_OS_BOOT
	402
	403	#define CONFIG_SYS_OS_BASE (CONFIG_SYS_FLASH_BASE + \
	404	0x60000)
	405	#define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + \
	406	0x40000)
	407	#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_TEXT_BASE + \
	408	0x1000000)
	409
	410	/* SP location before relocation, must use scratch RAM */
	411	/* BRAM start */
	412	#define CONFIG_SYS_INIT_RAM_ADDR 0x0
	413	/* BRAM size - will be generated */
ca7d2266	414	#define CONFIG_SYS_INIT_RAM_SIZE 0x100000
9d242745	415
ca7d2266 MS	416	# define CONFIG_SPL_STACK_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
	417	CONFIG_SYS_INIT_RAM_SIZE - \
	418	CONFIG_SYS_MALLOC_F_LEN)
9d242745 MS	419
	420	/* Just for sure that there is a space for stack */
	421	#define CONFIG_SPL_STACK_SIZE 0x100
	422
9d242745 MS	423	#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
	424
	425	#define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_INIT_RAM_SIZE - \
	426	CONFIG_SYS_INIT_RAM_ADDR - \
ca7d2266	427	CONFIG_SYS_MALLOC_F_LEN - \
9d242745 MS	428	CONFIG_SPL_STACK_SIZE)
9d242745 MS	429
76316a31	430	#endif /* __CONFIG_H */