[people/ms/u-boot.git] / include / configs / microblaze-generic.h

/*
 * (C) Copyright 2007-2010 Michal Simek
 *
 * Michal SIMEK <monstr@monstr.eu>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#include "../board/xilinx/microblaze-generic/xparameters.h"

/* MicroBlaze CPU */
#define	CONFIG_MICROBLAZE	1
#define	MICROBLAZE_V5		1

/* Open Firmware DTS */
#define CONFIG_OF_CONTROL	1
#define CONFIG_OF_EMBED		1
#define CONFIG_DEFAULT_DEVICE_TREE microblaze-generic

/* linear and spi flash memory */
#ifdef XILINX_FLASH_START
#define	FLASH
#undef	SPIFLASH
#undef	RAMENV	/* hold environment in flash */
#else
#ifdef XILINX_SPI_FLASH_BASEADDR
#undef	FLASH
#define	SPIFLASH
#undef	RAMENV	/* hold environment in flash */
#else
#undef	FLASH
#undef	SPIFLASH
#define	RAMENV	/* hold environment in RAM */
#endif
#endif

/* uart */
#ifdef XILINX_UARTLITE_BASEADDR
# define CONFIG_XILINX_UARTLITE
# define CONFIG_SERIAL_BASE	XILINX_UARTLITE_BASEADDR
# define CONFIG_BAUDRATE	XILINX_UARTLITE_BAUDRATE
# define CONFIG_SYS_BAUDRATE_TABLE	{ CONFIG_BAUDRATE }
# define CONSOLE_ARG	"console=console=ttyUL0,115200\0"
#elif XILINX_UART16550_BASEADDR
# define CONFIG_SYS_NS16550		1
# define CONFIG_SYS_NS16550_SERIAL
# if defined(__MICROBLAZEEL__)
#  define CONFIG_SYS_NS16550_REG_SIZE	-4
# else
#  define CONFIG_SYS_NS16550_REG_SIZE	4
# endif
# define CONFIG_CONS_INDEX		1
# define CONFIG_SYS_NS16550_COM1 \
		((XILINX_UART16550_BASEADDR & ~0xF) + 0x1000)
# define CONFIG_SYS_NS16550_CLK	XILINX_UART16550_CLOCK_HZ
# define CONFIG_BAUDRATE	115200

/* The following table includes the supported baudrates */
# define CONFIG_SYS_BAUDRATE_TABLE \
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
# define CONSOLE_ARG	"console=console=ttyS0,115200\0"
#else
# error Undefined uart
#endif

/* setting reset address */
/*#define	CONFIG_SYS_RESET_ADDRESS	CONFIG_SYS_TEXT_BASE*/

/* ethernet */
#undef CONFIG_SYS_ENET
#if defined(XILINX_EMACLITE_BASEADDR)
# define CONFIG_XILINX_EMACLITE	1
# define CONFIG_SYS_ENET
#endif
#if defined(XILINX_LLTEMAC_BASEADDR)
# define CONFIG_XILINX_LL_TEMAC	1
# define CONFIG_SYS_ENET
#endif
#if defined(XILINX_AXIEMAC_BASEADDR)
# define CONFIG_XILINX_AXIEMAC	1
# define CONFIG_SYS_ENET
#endif

#undef ET_DEBUG

/* gpio */
#ifdef XILINX_GPIO_BASEADDR
# define CONFIG_XILINX_GPIO
# define CONFIG_SYS_GPIO_0_ADDR		XILINX_GPIO_BASEADDR
#endif

/* interrupt controller */
#ifdef XILINX_INTC_BASEADDR
# define CONFIG_SYS_INTC_0_ADDR		XILINX_INTC_BASEADDR
# define CONFIG_SYS_INTC_0_NUM		XILINX_INTC_NUM_INTR_INPUTS
#endif

/* timer */
#if defined(XILINX_TIMER_BASEADDR) && defined(XILINX_TIMER_IRQ)
#  define CONFIG_SYS_TIMER_0_ADDR	XILINX_TIMER_BASEADDR
#  define CONFIG_SYS_TIMER_0_IRQ	XILINX_TIMER_IRQ
#endif

/* watchdog */
#if defined(XILINX_WATCHDOG_BASEADDR) && defined(XILINX_WATCHDOG_IRQ)
# define CONFIG_WATCHDOG_BASEADDR	XILINX_WATCHDOG_BASEADDR
# define CONFIG_WATCHDOG_IRQ		XILINX_WATCHDOG_IRQ
# define CONFIG_HW_WATCHDOG
# define CONFIG_XILINX_TB_WATCHDOG
#endif

/*
 * memory layout - Example
 * CONFIG_SYS_TEXT_BASE = 0x1200_0000;	defined in config.mk
 * CONFIG_SYS_SRAM_BASE = 0x1000_0000;
 * CONFIG_SYS_SRAM_SIZE = 0x0400_0000;	64MB
 *
 * CONFIG_SYS_MONITOR_LEN = 0x40000
 * CONFIG_SYS_MALLOC_LEN = 3 * CONFIG_SYS_MONITOR_LEN = 0xC0000
 *
 * CONFIG_SYS_GBL_DATA_OFFSET = 0x1000_0000 + 0x0400_0000 - 0x1000 = 0x13FF_F000
 * CONFIG_SYS_MONITOR_BASE = 0x13FF_F000 - CONFIG_SYS_MONITOR_LEN = 0x13FB_F000
 * CONFIG_SYS_MALLOC_BASE = 0x13FB_F000 - CONFIG_SYS_MALLOC_LEN = 0x13EF_F000
 *
 * 0x1000_0000	CONFIG_SYS_SDRAM_BASE
 *					MEMTEST_AREA	 64kB
 *					FREE
 * 0x1200_0000	CONFIG_SYS_TEXT_BASE
 *		U-BOOT code
 * 0x1202_0000
 *					FREE
 *
 *					STACK
 * 0x13EF_F000	CONFIG_SYS_MALLOC_BASE
 *					MALLOC_AREA	768kB	Alloc
 * 0x13FB_F000	CONFIG_SYS_MONITOR_BASE
 *					MONITOR_CODE	256kB	Env
 * 0x13FF_F000	CONFIG_SYS_GBL_DATA_OFFSET
 *					GLOBAL_DATA	4kB	bd, gd
 * 0x1400_0000	CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE
 */

/* ddr sdram - main memory */
#define	CONFIG_SYS_SDRAM_BASE		XILINX_RAM_START
#define	CONFIG_SYS_SDRAM_SIZE		XILINX_RAM_SIZE
#define	CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
#define	CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x1000)

/* global pointer */
/* start of global data */
#define	CONFIG_SYS_GBL_DATA_OFFSET \
		(CONFIG_SYS_SDRAM_SIZE - GENERATED_GBL_DATA_SIZE)

/* monitor code */
#define	SIZE				0x40000
#define	CONFIG_SYS_MONITOR_LEN		SIZE
#define	CONFIG_SYS_MONITOR_BASE	\
		(CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_GBL_DATA_OFFSET \
			- CONFIG_SYS_MONITOR_LEN - GENERATED_BD_INFO_SIZE)
#define	CONFIG_SYS_MONITOR_END \
			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define	CONFIG_SYS_MALLOC_LEN		(SIZE * 3)
#define	CONFIG_SYS_MALLOC_BASE \
			(CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)

/* stack */
#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_MALLOC_BASE

/*
 * CFI flash memory layout - Example
 * CONFIG_SYS_FLASH_BASE = 0x2200_0000;
 * CONFIG_SYS_FLASH_SIZE = 0x0080_0000;	  8MB
 *
 * SECT_SIZE = 0x20000;			128kB is one sector
 * CONFIG_ENV_SIZE = SECT_SIZE;		128kB environment store
 *
 * 0x2200_0000	CONFIG_SYS_FLASH_BASE
 *					FREE		256kB
 * 0x2204_0000	CONFIG_ENV_ADDR
 *					ENV_AREA	128kB
 * 0x2206_0000
 *					FREE
 * 0x2280_0000	CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE
 *
 */

#ifdef FLASH
# define CONFIG_SYS_FLASH_BASE		XILINX_FLASH_START
# define CONFIG_SYS_FLASH_SIZE		XILINX_FLASH_SIZE
# define CONFIG_SYS_FLASH_CFI		1
# define CONFIG_FLASH_CFI_DRIVER	1
/* ?empty sector */
# define CONFIG_SYS_FLASH_EMPTY_INFO	1
/* max number of memory banks */
# define CONFIG_SYS_MAX_FLASH_BANKS	1
/* max number of sectors on one chip */
# define CONFIG_SYS_MAX_FLASH_SECT	512
/* hardware flash protection */
# define CONFIG_SYS_FLASH_PROTECTION
/* use buffered writes (20x faster) */
# define	CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
# ifdef	RAMENV
#  define CONFIG_ENV_IS_NOWHERE	1
#  define CONFIG_ENV_SIZE	0x1000
#  define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)

# else	/* FLASH && !RAMENV */
#  define CONFIG_ENV_IS_IN_FLASH	1
/* 128K(one sector) for env */
#  define CONFIG_ENV_SECT_SIZE	0x20000
#  define CONFIG_ENV_ADDR \
			(CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
#  define CONFIG_ENV_SIZE	0x20000
# endif /* FLASH && !RAMBOOT */
#else /* !FLASH */

#ifdef SPIFLASH
# define CONFIG_SYS_NO_FLASH		1
# define CONFIG_SYS_SPI_BASE		XILINX_SPI_FLASH_BASEADDR
# define CONFIG_XILINX_SPI		1
# define CONFIG_SPI			1
# define CONFIG_SPI_FLASH		1
# define CONFIG_SPI_FLASH_STMICRO	1
# define CONFIG_SF_DEFAULT_MODE		SPI_MODE_3
# define CONFIG_SF_DEFAULT_SPEED	XILINX_SPI_FLASH_MAX_FREQ
# define CONFIG_SF_DEFAULT_CS		XILINX_SPI_FLASH_CS

# ifdef	RAMENV
#  define CONFIG_ENV_IS_NOWHERE	1
#  define CONFIG_ENV_SIZE	0x1000
#  define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)

# else	/* SPIFLASH && !RAMENV */
#  define CONFIG_ENV_IS_IN_SPI_FLASH	1
#  define CONFIG_ENV_SPI_MODE		SPI_MODE_3
#  define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SF_DEFAULT_SPEED
#  define CONFIG_ENV_SPI_CS		CONFIG_SF_DEFAULT_CS
/* 128K(two sectors) for env */
#  define CONFIG_ENV_SECT_SIZE	0x10000
#  define CONFIG_ENV_SIZE	(2 * CONFIG_ENV_SECT_SIZE)
/* Warning: adjust the offset in respect of other flash content and size */
#  define CONFIG_ENV_OFFSET	(128 * CONFIG_ENV_SECT_SIZE) /* at 8MB */
# endif /* SPIFLASH && !RAMBOOT */
#else /* !SPIFLASH */

/* ENV in RAM */
# define CONFIG_SYS_NO_FLASH	1
# define CONFIG_ENV_IS_NOWHERE	1
# define CONFIG_ENV_SIZE	0x1000
# define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
#endif /* !SPIFLASH */
#endif /* !FLASH */

/* system ace */
#ifdef XILINX_SYSACE_BASEADDR
# define CONFIG_SYSTEMACE
/* #define DEBUG_SYSTEMACE */
# define SYSTEMACE_CONFIG_FPGA
# define CONFIG_SYS_SYSTEMACE_BASE	XILINX_SYSACE_BASEADDR
# define CONFIG_SYS_SYSTEMACE_WIDTH	XILINX_SYSACE_MEM_WIDTH
# define CONFIG_DOS_PARTITION
#endif

#if defined(XILINX_USE_ICACHE)
# define CONFIG_ICACHE
#else
# undef CONFIG_ICACHE
#endif

#if defined(XILINX_USE_DCACHE)
# define CONFIG_DCACHE
#else
# undef CONFIG_DCACHE
#endif

#ifndef XILINX_DCACHE_BYTE_SIZE
#define XILINX_DCACHE_BYTE_SIZE	32768
#endif

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_MFSL
#define CONFIG_CMD_ECHO
#define CONFIG_CMD_GPIO

#if defined(CONFIG_DCACHE) || defined(CONFIG_ICACHE)
# define CONFIG_CMD_CACHE
#else
# undef CONFIG_CMD_CACHE
#endif

#ifndef CONFIG_SYS_ENET
# undef CONFIG_CMD_NET
# undef CONFIG_CMD_NFS
#else
# define CONFIG_CMD_PING
# define CONFIG_CMD_DHCP
# define CONFIG_CMD_TFTPPUT
#endif

#if defined(CONFIG_SYSTEMACE)
# define CONFIG_CMD_EXT2
# define CONFIG_CMD_FAT
#endif

#if defined(FLASH)
# define CONFIG_CMD_ECHO
# define CONFIG_CMD_FLASH
# define CONFIG_CMD_IMLS
# define CONFIG_CMD_JFFS2
# define CONFIG_CMD_UBI
# undef CONFIG_CMD_UBIFS

# if !defined(RAMENV)
#  define CONFIG_CMD_SAVEENV
#  define CONFIG_CMD_SAVES
# endif

#else
#if defined(SPIFLASH)
# define CONFIG_CMD_SF

# if !defined(RAMENV)
#  define CONFIG_CMD_SAVEENV
#  define CONFIG_CMD_SAVES
# endif
#else
# undef CONFIG_CMD_IMLS
# undef CONFIG_CMD_FLASH
# undef CONFIG_CMD_JFFS2
# undef CONFIG_CMD_UBI
# undef CONFIG_CMD_UBIFS
#endif
#endif

#if defined(CONFIG_CMD_JFFS2)
# define CONFIG_MTD_PARTITIONS
#endif

#if defined(CONFIG_CMD_UBIFS)
# define CONFIG_CMD_UBI
# define CONFIG_LZO
#endif

#if defined(CONFIG_CMD_UBI)
# define CONFIG_MTD_PARTITIONS
# define CONFIG_RBTREE
#endif

#if defined(CONFIG_MTD_PARTITIONS)
/* MTD partitions */
#define CONFIG_CMD_MTDPARTS	/* mtdparts command line support */
#define CONFIG_MTD_DEVICE	/* needed for mtdparts commands */
#define CONFIG_FLASH_CFI_MTD
#define MTDIDS_DEFAULT		"nor0=flash-0"

/* default mtd partition table */
#define MTDPARTS_DEFAULT	"mtdparts=flash-0:256k(u-boot),"\
				"256k(env),3m(kernel),1m(romfs),"\
				"1m(cramfs),-(jffs2)"
#endif

/* Miscellaneous configurable options */
#define	CONFIG_SYS_PROMPT	"U-Boot-mONStR> "
/* size of console buffer */
#define	CONFIG_SYS_CBSIZE	512
 /* print buffer size */
#define	CONFIG_SYS_PBSIZE \
		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
/* max number of command args */
#define	CONFIG_SYS_MAXARGS	15
#define	CONFIG_SYS_LONGHELP
/* default load address */
#define	CONFIG_SYS_LOAD_ADDR	XILINX_RAM_START

#define	CONFIG_BOOTDELAY	-1	/* -1 disables auto-boot */
#define	CONFIG_BOOTARGS		"root=romfs"
#define	CONFIG_HOSTNAME		XILINX_BOARD_NAME
#define	CONFIG_BOOTCOMMAND	"base 0;tftp 11000000 image.img;bootm"
#define	CONFIG_IPADDR		192.168.0.3
#define	CONFIG_SERVERIP		192.168.0.5
#define	CONFIG_GATEWAYIP	192.168.0.1
#define	CONFIG_ETHADDR		00:E0:0C:00:00:FD

/* architecture dependent code */
#define	CONFIG_SYS_USR_EXCEP	/* user exception */

#define	CONFIG_PREBOOT	"echo U-BOOT for ${hostname};setenv preboot;echo"

#define	CONFIG_EXTRA_ENV_SETTINGS	"unlock=yes\0" \
					"nor0=flash-0\0"\
					"mtdparts=mtdparts=flash-0:"\
					"256k(u-boot),256k(env),3m(kernel),"\
					"1m(romfs),1m(cramfs),-(jffs2)\0"\
					"nc=setenv stdout nc;"\
					"setenv stdin nc\0" \
					"serial=setenv stdout serial;"\
					"setenv stdin serial\0"

#define CONFIG_CMDLINE_EDITING

#define CONFIG_NETCONSOLE
#define CONFIG_SYS_CONSOLE_IS_IN_ENV

/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER

/* Enable flat device tree support */
#define CONFIG_LMB		1
#define CONFIG_FIT		1
#define CONFIG_OF_LIBFDT	1

#if defined(CONFIG_XILINX_LL_TEMAC) || defined(CONFIG_XILINX_AXIEMAC)
# define CONFIG_MII		1
# define CONFIG_CMD_MII		1
# define CONFIG_PHY_GIGE	1
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN	1
# define CONFIG_PHYLIB		1
# define CONFIG_PHY_ATHEROS	1
# define CONFIG_PHY_BROADCOM	1
# define CONFIG_PHY_DAVICOM	1
# define CONFIG_PHY_LXT		1
# define CONFIG_PHY_MARVELL	1
# define CONFIG_PHY_MICREL	1
# define CONFIG_PHY_NATSEMI	1
# define CONFIG_PHY_REALTEK	1
# define CONFIG_PHY_VITESSE	1
#else
# undef CONFIG_MII
# undef CONFIG_CMD_MII
# undef CONFIG_PHYLIB
#endif

/* SPL part */
#define CONFIG_SPL
#define CONFIG_CMD_SPL
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_BOARD_INIT

#define CONFIG_SPL_LDSCRIPT	"arch/microblaze/cpu/u-boot-spl.lds"

#define CONFIG_SPL_RAM_DEVICE
#define CONFIG_SPL_NOR_SUPPORT

/* for booting directly linux */
#define CONFIG_SPL_OS_BOOT

#define CONFIG_SYS_OS_BASE		(CONFIG_SYS_FLASH_BASE + \
					 0x60000)
#define CONFIG_SYS_FDT_BASE		(CONFIG_SYS_FLASH_BASE + \
					 0x40000)
#define CONFIG_SYS_SPL_ARGS_ADDR	(CONFIG_SYS_TEXT_BASE + \
					 0x1000000)

/* SP location before relocation, must use scratch RAM */
/* BRAM start */
#define CONFIG_SYS_INIT_RAM_ADDR	0x0
/* BRAM size - will be generated */
#define CONFIG_SYS_INIT_RAM_SIZE	0x10000
/* Stack pointer prior relocation, must situated at on-chip RAM */
#define CONFIG_SYS_SPL_MALLOC_END	(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - \
					 GENERATED_GBL_DATA_SIZE)

#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100

/*
 * The main reason to do it in this way is that MALLOC_START
 * can't be defined - common/spl/spl.c
 */
#if (CONFIG_SYS_SPL_MALLOC_SIZE != 0)
# define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SYS_SPL_MALLOC_END - \
					 CONFIG_SYS_SPL_MALLOC_SIZE)
# define CONFIG_SPL_STACK_ADDR		CONFIG_SYS_SPL_MALLOC_START
#else
# define CONFIG_SPL_STACK_ADDR		CONFIG_SYS_SPL_MALLOC_END
#endif

/* Just for sure that there is a space for stack */
#define CONFIG_SPL_STACK_SIZE		0x100

#define CONFIG_SYS_UBOOT_BASE		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_UBOOT_START		CONFIG_SYS_TEXT_BASE

#define CONFIG_SPL_MAX_FOOTPRINT	(CONFIG_SYS_INIT_RAM_SIZE - \
					 CONFIG_SYS_INIT_RAM_ADDR - \
					 GENERATED_GBL_DATA_SIZE - \
					 CONFIG_SYS_SPL_MALLOC_SIZE - \
					 CONFIG_SPL_STACK_SIZE)

#endif	/* __CONFIG_H */
Commit	Line	Data
76316a31	1	/*
4aecfb16	2	* (C) Copyright 2007-2010 Michal Simek
76316a31	3	*
cb1bc63b	4	* Michal SIMEK <monstr@monstr.eu>
76316a31	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
76316a31 MS	7	*/
	8
	9	#ifndef __CONFIG_H
	10	#define __CONFIG_H
	11
52a822ed	12	#include "../board/xilinx/microblaze-generic/xparameters.h"
76316a31	13
4aecfb16 MS	14	/* MicroBlaze CPU */
4aecfb16 MS	15	#define CONFIG_MICROBLAZE 1
1a50f164	16	#define MICROBLAZE_V5 1
76316a31	17
920c3587 SL	18	/* Open Firmware DTS */
	19	#define CONFIG_OF_CONTROL 1
	20	#define CONFIG_OF_EMBED 1
6697d558	21	#define CONFIG_DEFAULT_DEVICE_TREE microblaze-generic
920c3587	22
bcec8f49	23	/* linear and spi flash memory */
1fe7e8fa SL	24	#ifdef XILINX_FLASH_START
1fe7e8fa SL	25	#define FLASH
bcec8f49	26	#undef SPIFLASH
1fe7e8fa SL	27	#undef RAMENV /* hold environment in flash */
1fe7e8fa SL	28	#else
bcec8f49	29	#ifdef XILINX_SPI_FLASH_BASEADDR
1fe7e8fa	30	#undef FLASH
bcec8f49 SL	31	#define SPIFLASH
	32	#undef RAMENV /* hold environment in flash */
	33	#else
	34	#undef FLASH
	35	#undef SPIFLASH
1fe7e8fa SL	36	#define RAMENV /* hold environment in RAM */
1fe7e8fa SL	37	#endif
bcec8f49	38	#endif
1fe7e8fa	39
76316a31	40	/* uart */
af7ae1a4	41	#ifdef XILINX_UARTLITE_BASEADDR
4aecfb16 MS	42	# define CONFIG_XILINX_UARTLITE
	43	# define CONFIG_SERIAL_BASE XILINX_UARTLITE_BASEADDR
	44	# define CONFIG_BAUDRATE XILINX_UARTLITE_BAUDRATE
	45	# define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE }
	46	# define CONSOLE_ARG "console=console=ttyUL0,115200\0"
e7d591e8	47	#elif XILINX_UART16550_BASEADDR
4aecfb16 MS	48	# define CONFIG_SYS_NS16550 1
4aecfb16 MS	49	# define CONFIG_SYS_NS16550_SERIAL
1de55ef1 SL	50	# if defined(__MICROBLAZEEL__)
	51	# define CONFIG_SYS_NS16550_REG_SIZE -4
	52	# else
	53	# define CONFIG_SYS_NS16550_REG_SIZE 4
	54	# endif
4aecfb16 MS	55	# define CONFIG_CONS_INDEX 1
4aecfb16 MS	56	# define CONFIG_SYS_NS16550_COM1 \
1de55ef1	57	((XILINX_UART16550_BASEADDR & ~0xF) + 0x1000)
4aecfb16 MS	58	# define CONFIG_SYS_NS16550_CLK XILINX_UART16550_CLOCK_HZ
	59	# define CONFIG_BAUDRATE 115200
	60
	61	/* The following table includes the supported baudrates */
	62	# define CONFIG_SYS_BAUDRATE_TABLE \
	63	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
	64	# define CONSOLE_ARG "console=console=ttyS0,115200\0"
e7d591e8	65	#else
4aecfb16	66	# error Undefined uart
af7ae1a4	67	#endif
76316a31 MS	68
76316a31 MS	69	/* setting reset address */
14d0a02a	70	/#define CONFIG_SYS_RESET_ADDRESS CONFIG_SYS_TEXT_BASE/
76316a31	71
17980495	72	/* ethernet */
1252df06	73	#undef CONFIG_SYS_ENET
8422a35e SL	74	#if defined(XILINX_EMACLITE_BASEADDR)
8422a35e SL	75	# define CONFIG_XILINX_EMACLITE 1
4aecfb16	76	# define CONFIG_SYS_ENET
8422a35e SL	77	#endif
	78	#if defined(XILINX_LLTEMAC_BASEADDR)
	79	# define CONFIG_XILINX_LL_TEMAC 1
4aecfb16	80	# define CONFIG_SYS_ENET
e5845e21	81	#endif
e634138e MS	82	#if defined(XILINX_AXIEMAC_BASEADDR)
	83	# define CONFIG_XILINX_AXIEMAC 1
	84	# define CONFIG_SYS_ENET
	85	#endif
330e5545	86
e5845e21	87	#undef ET_DEBUG
17980495	88
76316a31	89	/* gpio */
4c6a6f02	90	#ifdef XILINX_GPIO_BASEADDR
4e779ad2	91	# define CONFIG_XILINX_GPIO
4aecfb16	92	# define CONFIG_SYS_GPIO_0_ADDR XILINX_GPIO_BASEADDR
4c6a6f02	93	#endif
76316a31 MS	94
76316a31 MS	95	/* interrupt controller */
4d49b280	96	#ifdef XILINX_INTC_BASEADDR
4aecfb16 MS	97	# define CONFIG_SYS_INTC_0_ADDR XILINX_INTC_BASEADDR
4aecfb16 MS	98	# define CONFIG_SYS_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS
4d49b280	99	#endif
76316a31 MS	100
76316a31 MS	101	/* timer */
bcbb046b	102	#if defined(XILINX_TIMER_BASEADDR) && defined(XILINX_TIMER_IRQ)
4aecfb16 MS	103	# define CONFIG_SYS_TIMER_0_ADDR XILINX_TIMER_BASEADDR
4aecfb16 MS	104	# define CONFIG_SYS_TIMER_0_IRQ XILINX_TIMER_IRQ
4d49b280	105	#endif
bcbb046b	106
0f21f98d MS	107	/* watchdog */
	108	#if defined(XILINX_WATCHDOG_BASEADDR) && defined(XILINX_WATCHDOG_IRQ)
	109	# define CONFIG_WATCHDOG_BASEADDR XILINX_WATCHDOG_BASEADDR
	110	# define CONFIG_WATCHDOG_IRQ XILINX_WATCHDOG_IRQ
	111	# define CONFIG_HW_WATCHDOG
	112	# define CONFIG_XILINX_TB_WATCHDOG
	113	#endif
	114
76316a31 MS	115	/*
76316a31 MS	116	* memory layout - Example
8f371b18	117	* CONFIG_SYS_TEXT_BASE = 0x1200_0000; defined in config.mk
6d0f6bcf	118	* CONFIG_SYS_SRAM_BASE = 0x1000_0000;
8f371b18 SL	119	* CONFIG_SYS_SRAM_SIZE = 0x0400_0000; 64MB
	120	*
	121	* CONFIG_SYS_MONITOR_LEN = 0x40000
	122	* CONFIG_SYS_MALLOC_LEN = 3 * CONFIG_SYS_MONITOR_LEN = 0xC0000
76316a31	123	*
6d0f6bcf	124	* CONFIG_SYS_GBL_DATA_OFFSET = 0x1000_0000 + 0x0400_0000 - 0x1000 = 0x13FF_F000
8f371b18 SL	125	* CONFIG_SYS_MONITOR_BASE = 0x13FF_F000 - CONFIG_SYS_MONITOR_LEN = 0x13FB_F000
8f371b18 SL	126	* CONFIG_SYS_MALLOC_BASE = 0x13FB_F000 - CONFIG_SYS_MALLOC_LEN = 0x13EF_F000
76316a31	127	*
6d0f6bcf	128	* 0x1000_0000 CONFIG_SYS_SDRAM_BASE
8f371b18	129	* MEMTEST_AREA 64kB
76316a31	130	* FREE
14d0a02a	131	* 0x1200_0000 CONFIG_SYS_TEXT_BASE
76316a31 MS	132	* U-BOOT code
	133	* 0x1202_0000
	134	* FREE
	135	*
	136	* STACK
8f371b18 SL	137	* 0x13EF_F000 CONFIG_SYS_MALLOC_BASE
	138	* MALLOC_AREA 768kB Alloc
	139	* 0x13FB_F000 CONFIG_SYS_MONITOR_BASE
17980495	140	* MONITOR_CODE 256kB Env
6d0f6bcf	141	* 0x13FF_F000 CONFIG_SYS_GBL_DATA_OFFSET
853643d8	142	* GLOBAL_DATA 4kB bd, gd
6d0f6bcf	143	* 0x1400_0000 CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE
76316a31 MS	144	*/
	145
	146	/* ddr sdram - main memory */
6d0f6bcf JCPV	147	#define CONFIG_SYS_SDRAM_BASE XILINX_RAM_START
	148	#define CONFIG_SYS_SDRAM_SIZE XILINX_RAM_SIZE
	149	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
	150	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x1000)
76316a31 MS	151
76316a31 MS	152	/* global pointer */
32556443	153	/* start of global data */
4aecfb16	154	#define CONFIG_SYS_GBL_DATA_OFFSET \
1020286e	155	(CONFIG_SYS_SDRAM_SIZE - GENERATED_GBL_DATA_SIZE)
76316a31 MS	156
76316a31 MS	157	/* monitor code */
4aecfb16	158	#define SIZE 0x40000
1020286e	159	#define CONFIG_SYS_MONITOR_LEN SIZE
4aecfb16	160	#define CONFIG_SYS_MONITOR_BASE \
1020286e MS	161	(CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_GBL_DATA_OFFSET \
1020286e MS	162	- CONFIG_SYS_MONITOR_LEN - GENERATED_BD_INFO_SIZE)
4aecfb16 MS	163	#define CONFIG_SYS_MONITOR_END \
4aecfb16 MS	164	(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
7cfb13a7	165	#define CONFIG_SYS_MALLOC_LEN (SIZE * 3)
4aecfb16 MS	166	#define CONFIG_SYS_MALLOC_BASE \
4aecfb16 MS	167	(CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
76316a31 MS	168
76316a31 MS	169	/* stack */
8fe7b29f	170	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_MALLOC_BASE
76316a31	171
8f371b18 SL	172	/*
	173	* CFI flash memory layout - Example
	174	* CONFIG_SYS_FLASH_BASE = 0x2200_0000;
	175	* CONFIG_SYS_FLASH_SIZE = 0x0080_0000; 8MB
	176	*
	177	* SECT_SIZE = 0x20000; 128kB is one sector
	178	* CONFIG_ENV_SIZE = SECT_SIZE; 128kB environment store
	179	*
	180	* 0x2200_0000 CONFIG_SYS_FLASH_BASE
	181	* FREE 256kB
	182	* 0x2204_0000 CONFIG_ENV_ADDR
	183	* ENV_AREA 128kB
	184	* 0x2206_0000
	185	* FREE
	186	* 0x2280_0000 CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE
	187	*
	188	*/
	189
76316a31	190	#ifdef FLASH
4aecfb16 MS	191	# define CONFIG_SYS_FLASH_BASE XILINX_FLASH_START
	192	# define CONFIG_SYS_FLASH_SIZE XILINX_FLASH_SIZE
	193	# define CONFIG_SYS_FLASH_CFI 1
	194	# define CONFIG_FLASH_CFI_DRIVER 1
	195	/* ?empty sector */
	196	# define CONFIG_SYS_FLASH_EMPTY_INFO 1
	197	/* max number of memory banks */
	198	# define CONFIG_SYS_MAX_FLASH_BANKS 1
	199	/* max number of sectors on one chip */
	200	# define CONFIG_SYS_MAX_FLASH_SECT 512
	201	/* hardware flash protection */
	202	# define CONFIG_SYS_FLASH_PROTECTION
22ff7f4d MS	203	/* use buffered writes (20x faster) */
22ff7f4d MS	204	# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
4aecfb16 MS	205	# ifdef RAMENV
	206	# define CONFIG_ENV_IS_NOWHERE 1
	207	# define CONFIG_ENV_SIZE 0x1000
	208	# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
	209
bcec8f49	210	# else /* FLASH && !RAMENV */
4aecfb16 MS	211	# define CONFIG_ENV_IS_IN_FLASH 1
	212	/* 128K(one sector) for env */
	213	# define CONFIG_ENV_SECT_SIZE 0x20000
	214	# define CONFIG_ENV_ADDR \
	215	(CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
	216	# define CONFIG_ENV_SIZE 0x20000
bcec8f49	217	# endif /* FLASH && !RAMBOOT */
76316a31	218	#else /* !FLASH */
bcec8f49 SL	219
	220	#ifdef SPIFLASH
	221	# define CONFIG_SYS_NO_FLASH 1
	222	# define CONFIG_SYS_SPI_BASE XILINX_SPI_FLASH_BASEADDR
	223	# define CONFIG_XILINX_SPI 1
	224	# define CONFIG_SPI 1
	225	# define CONFIG_SPI_FLASH 1
	226	# define CONFIG_SPI_FLASH_STMICRO 1
	227	# define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
	228	# define CONFIG_SF_DEFAULT_SPEED XILINX_SPI_FLASH_MAX_FREQ
	229	# define CONFIG_SF_DEFAULT_CS XILINX_SPI_FLASH_CS
	230
	231	# ifdef RAMENV
	232	# define CONFIG_ENV_IS_NOWHERE 1
	233	# define CONFIG_ENV_SIZE 0x1000
	234	# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
	235
	236	# else /* SPIFLASH && !RAMENV */
	237	# define CONFIG_ENV_IS_IN_SPI_FLASH 1
	238	# define CONFIG_ENV_SPI_MODE SPI_MODE_3
	239	# define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
	240	# define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
	241	/* 128K(two sectors) for env */
	242	# define CONFIG_ENV_SECT_SIZE 0x10000
	243	# define CONFIG_ENV_SIZE (2 * CONFIG_ENV_SECT_SIZE)
	244	/* Warning: adjust the offset in respect of other flash content and size */
	245	# define CONFIG_ENV_OFFSET (128 * CONFIG_ENV_SECT_SIZE) /* at 8MB */
	246	# endif /* SPIFLASH && !RAMBOOT */
	247	#else /* !SPIFLASH */
	248
4aecfb16 MS	249	/* ENV in RAM */
	250	# define CONFIG_SYS_NO_FLASH 1
	251	# define CONFIG_ENV_IS_NOWHERE 1
	252	# define CONFIG_ENV_SIZE 0x1000
	253	# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
bcec8f49	254	#endif /* !SPIFLASH */
76316a31 MS	255	#endif /* !FLASH */
76316a31 MS	256
853643d8 MS	257	/* system ace */
853643d8 MS	258	#ifdef XILINX_SYSACE_BASEADDR
4aecfb16 MS	259	# define CONFIG_SYSTEMACE
	260	/* #define DEBUG_SYSTEMACE */
	261	# define SYSTEMACE_CONFIG_FPGA
	262	# define CONFIG_SYS_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR
	263	# define CONFIG_SYS_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH
	264	# define CONFIG_DOS_PARTITION
853643d8 MS	265	#endif
853643d8 MS	266
e9b737de	267	#if defined(XILINX_USE_ICACHE)
4aecfb16	268	# define CONFIG_ICACHE
e9b737de	269	#else
4aecfb16	270	# undef CONFIG_ICACHE
e9b737de MS	271	#endif
	272
	273	#if defined(XILINX_USE_DCACHE)
4aecfb16	274	# define CONFIG_DCACHE
e9b737de	275	#else
4aecfb16	276	# undef CONFIG_DCACHE
e9b737de MS	277	#endif
e9b737de MS	278
5811830f MS	279	#ifndef XILINX_DCACHE_BYTE_SIZE
	280	#define XILINX_DCACHE_BYTE_SIZE 32768
	281	#endif
	282
079a136c JL	283	/*
	284	* BOOTP options
	285	*/
	286	#define CONFIG_BOOTP_BOOTFILESIZE
	287	#define CONFIG_BOOTP_BOOTPATH
	288	#define CONFIG_BOOTP_GATEWAY
	289	#define CONFIG_BOOTP_HOSTNAME
76316a31	290
5dc11a51 JL	291	/*
	292	* Command line configuration.
	293	*/
	294	#include <config_cmd_default.h>
	295
	296	#define CONFIG_CMD_ASKENV
5dc11a51	297	#define CONFIG_CMD_IRQ
5dc11a51	298	#define CONFIG_CMD_MFSL
330e5545	299	#define CONFIG_CMD_ECHO
4e779ad2	300	#define CONFIG_CMD_GPIO
4d49b280	301
e9b737de	302	#if defined(CONFIG_DCACHE) \|\| defined(CONFIG_ICACHE)
4aecfb16	303	# define CONFIG_CMD_CACHE
e9b737de	304	#else
4aecfb16	305	# undef CONFIG_CMD_CACHE
e9b737de MS	306	#endif
e9b737de MS	307
6d0f6bcf	308	#ifndef CONFIG_SYS_ENET
4aecfb16	309	# undef CONFIG_CMD_NET
1252df06	310	# undef CONFIG_CMD_NFS
4d49b280	311	#else
4aecfb16 MS	312	# define CONFIG_CMD_PING
4aecfb16 MS	313	# define CONFIG_CMD_DHCP
4eb29cf0	314	# define CONFIG_CMD_TFTPPUT
4d49b280	315	#endif
853643d8 MS	316
853643d8 MS	317	#if defined(CONFIG_SYSTEMACE)
4aecfb16 MS	318	# define CONFIG_CMD_EXT2
4aecfb16 MS	319	# define CONFIG_CMD_FAT
853643d8	320	#endif
5dc11a51 JL	321
5dc11a51 JL	322	#if defined(FLASH)
4aecfb16 MS	323	# define CONFIG_CMD_ECHO
	324	# define CONFIG_CMD_FLASH
	325	# define CONFIG_CMD_IMLS
	326	# define CONFIG_CMD_JFFS2
7cfb13a7 SL	327	# define CONFIG_CMD_UBI
7cfb13a7 SL	328	# undef CONFIG_CMD_UBIFS
4aecfb16	329
bcec8f49 SL	330	# if !defined(RAMENV)
	331	# define CONFIG_CMD_SAVEENV
	332	# define CONFIG_CMD_SAVES
	333	# endif
	334
	335	#else
	336	#if defined(SPIFLASH)
	337	# define CONFIG_CMD_SF
	338
4aecfb16 MS	339	# if !defined(RAMENV)
	340	# define CONFIG_CMD_SAVEENV
	341	# define CONFIG_CMD_SAVES
	342	# endif
853643d8	343	#else
4aecfb16 MS	344	# undef CONFIG_CMD_IMLS
	345	# undef CONFIG_CMD_FLASH
	346	# undef CONFIG_CMD_JFFS2
2cce2d32 SL	347	# undef CONFIG_CMD_UBI
2cce2d32 SL	348	# undef CONFIG_CMD_UBIFS
5dc11a51	349	#endif
bcec8f49	350	#endif
76316a31	351
5dc11a51	352	#if defined(CONFIG_CMD_JFFS2)
7cfb13a7 SL	353	# define CONFIG_MTD_PARTITIONS
	354	#endif
	355
	356	#if defined(CONFIG_CMD_UBIFS)
	357	# define CONFIG_CMD_UBI
	358	# define CONFIG_LZO
	359	#endif
	360
	361	#if defined(CONFIG_CMD_UBI)
	362	# define CONFIG_MTD_PARTITIONS
	363	# define CONFIG_RBTREE
	364	#endif
	365
	366	#if defined(CONFIG_MTD_PARTITIONS)
	367	/* MTD partitions */
68d7d651	368	#define CONFIG_CMD_MTDPARTS /* mtdparts command line support */
942556a9 SR	369	#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
942556a9 SR	370	#define CONFIG_FLASH_CFI_MTD
c82a541d	371	#define MTDIDS_DEFAULT "nor0=flash-0"
144876a3 MS	372
144876a3 MS	373	/* default mtd partition table */
c82a541d	374	#define MTDPARTS_DEFAULT "mtdparts=flash-0:256k(u-boot),"\
144876a3 MS	375	"256k(env),3m(kernel),1m(romfs),"\
	376	"1m(cramfs),-(jffs2)"
	377	#endif
	378
76316a31	379	/* Miscellaneous configurable options */
6d0f6bcf	380	#define CONFIG_SYS_PROMPT "U-Boot-mONStR> "
4aecfb16 MS	381	/* size of console buffer */
	382	#define CONFIG_SYS_CBSIZE 512
	383	/* print buffer size */
	384	#define CONFIG_SYS_PBSIZE \
	385	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
	386	/* max number of command args */
	387	#define CONFIG_SYS_MAXARGS 15
6d0f6bcf	388	#define CONFIG_SYS_LONGHELP
4aecfb16 MS	389	/* default load address */
4aecfb16 MS	390	#define CONFIG_SYS_LOAD_ADDR XILINX_RAM_START
76316a31	391
330e5545	392	#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */
76316a31	393	#define CONFIG_BOOTARGS "root=romfs"
330e5545	394	#define CONFIG_HOSTNAME XILINX_BOARD_NAME
853643d8	395	#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm"
76316a31	396	#define CONFIG_IPADDR 192.168.0.3
853643d8 MS	397	#define CONFIG_SERVERIP 192.168.0.5
853643d8 MS	398	#define CONFIG_GATEWAYIP 192.168.0.1
76316a31 MS	399	#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
	400
	401	/* architecture dependent code */
6d0f6bcf	402	#define CONFIG_SYS_USR_EXCEP /* user exception */
76316a31	403
0900bee9	404	#define CONFIG_PREBOOT "echo U-BOOT for ${hostname};setenv preboot;echo"
144876a3	405
4aecfb16	406	#define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" \
c82a541d SL	407	"nor0=flash-0\0"\
c82a541d SL	408	"mtdparts=mtdparts=flash-0:"\
144876a3	409	"256k(u-boot),256k(env),3m(kernel),"\
78376452 MS	410	"1m(romfs),1m(cramfs),-(jffs2)\0"\
	411	"nc=setenv stdout nc;"\
	412	"setenv stdin nc\0" \
	413	"serial=setenv stdout serial;"\
	414	"setenv stdin serial\0"
144876a3	415
188dc16b	416	#define CONFIG_CMDLINE_EDITING
188dc16b	417
78376452 MS	418	#define CONFIG_NETCONSOLE
	419	#define CONFIG_SYS_CONSOLE_IS_IN_ENV
	420
0900bee9 MS	421	/* Use the HUSH parser */
0900bee9 MS	422	#define CONFIG_SYS_HUSH_PARSER
0900bee9	423
37e892d9 MS	424	/* Enable flat device tree support */
	425	#define CONFIG_LMB 1
	426	#define CONFIG_FIT 1
	427	#define CONFIG_OF_LIBFDT 1
	428
8422a35e	429	#if defined(CONFIG_XILINX_LL_TEMAC) \|\| defined(CONFIG_XILINX_AXIEMAC)
f5e5e1ff SL	430	# define CONFIG_MII 1
	431	# define CONFIG_CMD_MII 1
	432	# define CONFIG_PHY_GIGE 1
	433	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1
	434	# define CONFIG_PHYLIB 1
	435	# define CONFIG_PHY_ATHEROS 1
	436	# define CONFIG_PHY_BROADCOM 1
	437	# define CONFIG_PHY_DAVICOM 1
	438	# define CONFIG_PHY_LXT 1
	439	# define CONFIG_PHY_MARVELL 1
	440	# define CONFIG_PHY_MICREL 1
	441	# define CONFIG_PHY_NATSEMI 1
	442	# define CONFIG_PHY_REALTEK 1
	443	# define CONFIG_PHY_VITESSE 1
	444	#else
	445	# undef CONFIG_MII
	446	# undef CONFIG_CMD_MII
	447	# undef CONFIG_PHYLIB
	448	#endif
	449
9d242745 MS	450	/* SPL part */
	451	#define CONFIG_SPL
	452	#define CONFIG_CMD_SPL
	453	#define CONFIG_SPL_FRAMEWORK
	454	#define CONFIG_SPL_LIBCOMMON_SUPPORT
	455	#define CONFIG_SPL_LIBGENERIC_SUPPORT
	456	#define CONFIG_SPL_SERIAL_SUPPORT
	457	#define CONFIG_SPL_BOARD_INIT
	458
	459	#define CONFIG_SPL_LDSCRIPT "arch/microblaze/cpu/u-boot-spl.lds"
	460
	461	#define CONFIG_SPL_RAM_DEVICE
	462	#define CONFIG_SPL_NOR_SUPPORT
	463
	464	/* for booting directly linux */
	465	#define CONFIG_SPL_OS_BOOT
	466
	467	#define CONFIG_SYS_OS_BASE (CONFIG_SYS_FLASH_BASE + \
	468	0x60000)
	469	#define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + \
	470	0x40000)
	471	#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_TEXT_BASE + \
	472	0x1000000)
	473
	474	/* SP location before relocation, must use scratch RAM */
	475	/* BRAM start */
	476	#define CONFIG_SYS_INIT_RAM_ADDR 0x0
	477	/* BRAM size - will be generated */
	478	#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
	479	/* Stack pointer prior relocation, must situated at on-chip RAM */
	480	#define CONFIG_SYS_SPL_MALLOC_END (CONFIG_SYS_INIT_RAM_ADDR + \
	481	CONFIG_SYS_INIT_RAM_SIZE - \
	482	GENERATED_GBL_DATA_SIZE)
	483
	484	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100
	485
	486	/*
	487	* The main reason to do it in this way is that MALLOC_START
	488	* can't be defined - common/spl/spl.c
	489	*/
	490	#if (CONFIG_SYS_SPL_MALLOC_SIZE != 0)
	491	# define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_SPL_MALLOC_END - \
	492	CONFIG_SYS_SPL_MALLOC_SIZE)
	493	# define CONFIG_SPL_STACK_ADDR CONFIG_SYS_SPL_MALLOC_START
	494	#else
	495	# define CONFIG_SPL_STACK_ADDR CONFIG_SYS_SPL_MALLOC_END
	496	#endif
	497
	498	/* Just for sure that there is a space for stack */
	499	#define CONFIG_SPL_STACK_SIZE 0x100
	500
	501	#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_FLASH_BASE
	502	#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
	503
	504	#define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_INIT_RAM_SIZE - \
	505	CONFIG_SYS_INIT_RAM_ADDR - \
	506	GENERATED_GBL_DATA_SIZE - \
	507	CONFIG_SYS_SPL_MALLOC_SIZE - \
	508	CONFIG_SPL_STACK_SIZE)
	509
76316a31	510	#endif /* __CONFIG_H */