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8993e54b | 1 | /* |
3b74e7ec | 2 | * (C) Copyright 2007-2009 DENX Software Engineering |
8993e54b | 3 | * |
3765b3e7 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
8993e54b RJ |
5 | */ |
6 | ||
7 | /* | |
72601d04 | 8 | * MPC5121ADS board configuration file |
8993e54b RJ |
9 | */ |
10 | ||
11 | #ifndef __CONFIG_H | |
12 | #define __CONFIG_H | |
13 | ||
72601d04 | 14 | #define CONFIG_MPC5121ADS 1 |
10e99d8f | 15 | |
8993e54b | 16 | /* |
72601d04 | 17 | * Memory map for the MPC5121ADS board: |
8993e54b RJ |
18 | * |
19 | * 0x0000_0000 - 0x0FFF_FFFF DDR RAM (256 MB) | |
20 | * 0x3000_0000 - 0x3001_FFFF SRAM (128 KB) | |
21 | * 0x8000_0000 - 0x803F_FFFF IMMR (4 MB) | |
22 | * 0x8200_0000 - 0x8200_001F CPLD (32 B) | |
5f91db7f JR |
23 | * 0x8400_0000 - 0x82FF_FFFF PCI I/O space (16 MB) |
24 | * 0xA000_0000 - 0xAFFF_FFFF PCI memory space (256 MB) | |
25 | * 0xB000_0000 - 0xBFFF_FFFF PCI memory mapped I/O space (256 MB) | |
8993e54b RJ |
26 | * 0xFC00_0000 - 0xFFFF_FFFF NOR Boot FLASH (64 MB) |
27 | */ | |
28 | ||
29 | /* | |
30 | * High Level Configuration Options | |
31 | */ | |
32 | #define CONFIG_E300 1 /* E300 Family */ | |
0e1bad47 | 33 | |
2ae18241 WD |
34 | #define CONFIG_SYS_TEXT_BASE 0xFFF00000 |
35 | ||
0e1bad47 | 36 | /* video */ |
7d3053fb TT |
37 | #ifdef CONFIG_FSL_DIU_FB |
38 | #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_IMMR + 0x2100) | |
e69e520f TT |
39 | #define CONFIG_VIDEO_LOGO |
40 | #define CONFIG_VIDEO_BMP_LOGO | |
0e1bad47 | 41 | #endif |
8993e54b | 42 | |
5f91db7f | 43 | /* CONFIG_PCI is defined at config time */ |
8993e54b | 44 | |
72601d04 | 45 | #ifdef CONFIG_MPC5121ADS_REV2 |
6d0f6bcf | 46 | #define CONFIG_SYS_MPC512X_CLKIN 66000000 /* in Hz */ |
f31c49db | 47 | #else |
6d0f6bcf | 48 | #define CONFIG_SYS_MPC512X_CLKIN 33333333 /* in Hz */ |
f31c49db | 49 | #endif |
8993e54b | 50 | |
0e1bad47 | 51 | #define CONFIG_MISC_INIT_R |
8993e54b | 52 | |
6d0f6bcf | 53 | #define CONFIG_SYS_IMMR 0x80000000 |
8993e54b | 54 | |
6d0f6bcf JCPV |
55 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ |
56 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
8993e54b RJ |
57 | |
58 | /* | |
59 | * DDR Setup - manually set all parameters as there's no SPD etc. | |
60 | */ | |
72601d04 | 61 | #ifdef CONFIG_MPC5121ADS_REV2 |
6d0f6bcf | 62 | #define CONFIG_SYS_DDR_SIZE 256 /* MB */ |
f31c49db | 63 | #else |
6d0f6bcf | 64 | #define CONFIG_SYS_DDR_SIZE 512 /* MB */ |
f31c49db | 65 | #endif |
6d0f6bcf JCPV |
66 | #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ |
67 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
b9947bbb | 68 | #define CONFIG_SYS_MAX_RAM_SIZE 0x20000000 |
8993e54b | 69 | |
5d937e8b AG |
70 | #define CONFIG_SYS_IOCTRL_MUX_DDR 0x00000036 |
71 | ||
8993e54b | 72 | /* DDR Controller Configuration |
b1b54e35 WD |
73 | * |
74 | * SYS_CFG: | |
75 | * [31:31] MDDRC Soft Reset: Diabled | |
76 | * [30:30] DRAM CKE pin: Enabled | |
77 | * [29:29] DRAM CLK: Enabled | |
78 | * [28:28] Command Mode: Enabled (For initialization only) | |
79 | * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10] | |
80 | * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10] | |
81 | * [20:19] Read Test: DON'T USE | |
82 | * [18:18] Self Refresh: Enabled | |
83 | * [17:17] 16bit Mode: Disabled | |
84 | * [16:13] Ready Delay: 2 | |
85 | * [12:12] Half DQS Delay: Disabled | |
86 | * [11:11] Quarter DQS Delay: Disabled | |
87 | * [10:08] Write Delay: 2 | |
88 | * [07:07] Early ODT: Disabled | |
89 | * [06:06] On DIE Termination: Disabled | |
90 | * [05:05] FIFO Overflow Clear: DON'T USE here | |
91 | * [04:04] FIFO Underflow Clear: DON'T USE here | |
92 | * [03:03] FIFO Overflow Pending: DON'T USE here | |
93 | * [02:02] FIFO Underlfow Pending: DON'T USE here | |
94 | * [01:01] FIFO Overlfow Enabled: Enabled | |
95 | * [00:00] FIFO Underflow Enabled: Enabled | |
96 | * TIME_CFG0 | |
97 | * [31:16] DRAM Refresh Time: 0 CSB clocks | |
98 | * [15:8] DRAM Command Time: 0 CSB clocks | |
99 | * [07:00] DRAM Precharge Time: 0 CSB clocks | |
100 | * TIME_CFG1 | |
101 | * [31:26] DRAM tRFC: | |
102 | * [25:21] DRAM tWR1: | |
103 | * [20:17] DRAM tWRT1: | |
104 | * [16:11] DRAM tDRR: | |
105 | * [10:05] DRAM tRC: | |
106 | * [04:00] DRAM tRAS: | |
107 | * TIME_CFG2 | |
108 | * [31:28] DRAM tRCD: | |
109 | * [27:23] DRAM tFAW: | |
110 | * [22:19] DRAM tRTW1: | |
111 | * [18:15] DRAM tCCD: | |
112 | * [14:10] DRAM tRTP: | |
113 | * [09:05] DRAM tRP: | |
114 | * [04:00] DRAM tRPA | |
115 | */ | |
72601d04 | 116 | #ifdef CONFIG_MPC5121ADS_REV2 |
054197ba | 117 | #define CONFIG_SYS_MDDRC_SYS_CFG 0xE8604A00 |
6d0f6bcf JCPV |
118 | #define CONFIG_SYS_MDDRC_TIME_CFG1 0x54EC1168 |
119 | #define CONFIG_SYS_MDDRC_TIME_CFG2 0x35210864 | |
f31c49db | 120 | #else |
054197ba MS |
121 | #define CONFIG_SYS_MDDRC_SYS_CFG 0xEA804A00 |
122 | #define CONFIG_SYS_MDDRC_TIME_CFG1 0x68EC1168 | |
123 | #define CONFIG_SYS_MDDRC_TIME_CFG2 0x34310864 | |
f31c49db | 124 | #endif |
054197ba | 125 | #define CONFIG_SYS_MDDRC_TIME_CFG0 0x06183D2E |
6d0f6bcf | 126 | |
a5aa3998 MS |
127 | #define CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA 0xEA802B00 |
128 | #define CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA 0x690e1189 | |
129 | #define CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA 0x35310864 | |
130 | ||
054197ba MS |
131 | #define CONFIG_SYS_DDRCMD_NOP 0x01380000 |
132 | #define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400 | |
133 | #define CONFIG_SYS_DDRCMD_EM2 0x01020000 | |
134 | #define CONFIG_SYS_DDRCMD_EM3 0x01030000 | |
135 | #define CONFIG_SYS_DDRCMD_EN_DLL 0x01010000 | |
136 | #define CONFIG_SYS_DDRCMD_RFSH 0x01080000 | |
a5aa3998 MS |
137 | |
138 | #define DDRCMD_EMR_OCD(pr, ohm) ( \ | |
139 | (1 << 24) | /* MDDRC Command Request */ \ | |
140 | (1 << 16) | /* MODE Reg BA[2:0] */ \ | |
141 | (0 << 12) | /* Outputs 0=Enabled */ \ | |
142 | (0 << 11) | /* RDQS */ \ | |
143 | (1 << 10) | /* DQS# */ \ | |
144 | (pr << 7) | /* OCD prog 7=deflt,0=exit */ \ | |
145 | /* ODT Rtt[1:0] 0=0,1=75,2=150,3=50 */ \ | |
146 | ((ohm & 0x2) << 5)| /* Rtt1 */ \ | |
147 | (0 << 3) | /* additive posted CAS# */ \ | |
148 | ((ohm & 0x1) << 2)| /* Rtt0 */ \ | |
149 | (0 << 0) | /* Output Drive Strength */ \ | |
150 | (0 << 0)) /* DLL Enable 0=Normal */ | |
151 | ||
152 | #define CONFIG_SYS_DDRCMD_OCD_DEFAULT DDRCMD_EMR_OCD(7, 0) | |
153 | #define CONFIG_SYS_ELPIDA_OCD_EXIT DDRCMD_EMR_OCD(0, 0) | |
154 | ||
155 | #define DDRCMD_MODE_REG(cas, wr) ( \ | |
156 | (1 << 24) | /* MDDRC Command Request */ \ | |
157 | (0 << 16) | /* MODE Reg BA[2:0] */ \ | |
158 | ((wr-1) << 9)| /* Write Recovery */ \ | |
159 | (cas << 4) | /* CAS */ \ | |
160 | (0 << 3) | /* Burst Type:0=Sequential,1=Interleaved */ \ | |
161 | (2 << 0)) /* 4 or 8 Burst Length:0x2=4 0x3=8 */ | |
162 | ||
163 | #define CONFIG_SYS_MICRON_INIT_DEV_OP DDRCMD_MODE_REG(3, 3) | |
164 | #define CONFIG_SYS_ELPIDA_INIT_DEV_OP DDRCMD_MODE_REG(4, 4) | |
165 | #define CONFIG_SYS_ELPIDA_RES_DLL (DDRCMD_MODE_REG(4, 4) | (1 << 8)) | |
8993e54b RJ |
166 | |
167 | /* DDR Priority Manager Configuration */ | |
6d0f6bcf JCPV |
168 | #define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777 |
169 | #define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000 | |
170 | #define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001 | |
171 | #define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC | |
172 | #define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA | |
173 | #define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666 | |
174 | #define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555 | |
175 | #define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444 | |
176 | #define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444 | |
177 | #define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555 | |
178 | #define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558 | |
179 | #define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111 | |
180 | #define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122 | |
181 | #define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa | |
182 | #define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa | |
183 | #define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666 | |
184 | #define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666 | |
185 | #define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111 | |
186 | #define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111 | |
187 | #define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111 | |
188 | #define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111 | |
189 | #define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111 | |
190 | #define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111 | |
8993e54b RJ |
191 | |
192 | /* | |
193 | * NOR FLASH on the Local Bus | |
194 | */ | |
f31c49db | 195 | #undef CONFIG_BKUP_FLASH |
6d0f6bcf | 196 | #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ |
00b1883a | 197 | #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ |
f31c49db | 198 | #ifdef CONFIG_BKUP_FLASH |
6d0f6bcf JCPV |
199 | #define CONFIG_SYS_FLASH_BASE 0xFF800000 /* start of FLASH */ |
200 | #define CONFIG_SYS_FLASH_SIZE 0x00800000 /* max flash size in bytes */ | |
f31c49db | 201 | #else |
6d0f6bcf JCPV |
202 | #define CONFIG_SYS_FLASH_BASE 0xFC000000 /* start of FLASH */ |
203 | #define CONFIG_SYS_FLASH_SIZE 0x04000000 /* max flash size in bytes */ | |
f31c49db | 204 | #endif |
6d0f6bcf JCPV |
205 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
206 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
207 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} | |
208 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ | |
8993e54b | 209 | |
6d0f6bcf | 210 | #undef CONFIG_SYS_FLASH_CHECKSUM |
8993e54b | 211 | |
229549a5 SR |
212 | /* |
213 | * NAND FLASH | |
13946925 | 214 | * drivers/mtd/nand/mpc5121_nfc.c (rev 2 silicon only) |
229549a5 | 215 | */ |
7d4450a9 WD |
216 | #define CONFIG_CMD_NAND /* enable NAND support */ |
217 | #define CONFIG_JFFS2_NAND /* with JFFS2 on it */ | |
229549a5 SR |
218 | #define CONFIG_NAND_MPC5121_NFC |
219 | #define CONFIG_SYS_NAND_BASE 0x40000000 | |
220 | ||
221 | #define CONFIG_SYS_MAX_NAND_DEVICE 2 | |
229549a5 SR |
222 | #define CONFIG_SYS_NAND_SELECT_DEVICE /* driver supports mutipl. chips */ |
223 | ||
224 | /* | |
225 | * Configuration parameters for MPC5121 NAND driver | |
226 | */ | |
227 | #define CONFIG_FSL_NFC_WIDTH 1 | |
228 | #define CONFIG_FSL_NFC_WRITE_SIZE 2048 | |
229 | #define CONFIG_FSL_NFC_SPARE_SIZE 64 | |
230 | #define CONFIG_FSL_NFC_CHIPS CONFIG_SYS_MAX_NAND_DEVICE | |
231 | ||
8993e54b RJ |
232 | /* |
233 | * CPLD registers area is really only 32 bytes in size, but the smallest possible LP | |
234 | * window is 64KB | |
235 | */ | |
6d0f6bcf JCPV |
236 | #define CONFIG_SYS_CPLD_BASE 0x82000000 |
237 | #define CONFIG_SYS_CPLD_SIZE 0x00010000 /* 64 KB */ | |
676c6691 AG |
238 | #define CONFIG_SYS_CS2_START CONFIG_SYS_CPLD_BASE |
239 | #define CONFIG_SYS_CS2_SIZE CONFIG_SYS_CPLD_SIZE | |
8993e54b | 240 | |
6d0f6bcf JCPV |
241 | #define CONFIG_SYS_SRAM_BASE 0x30000000 |
242 | #define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */ | |
8993e54b | 243 | |
6d0f6bcf JCPV |
244 | #define CONFIG_SYS_CS0_CFG 0x05059310 /* ALE active low, data size 4bytes */ |
245 | #define CONFIG_SYS_CS2_CFG 0x05059010 /* ALE active low, data size 1byte */ | |
246 | #define CONFIG_SYS_CS_ALETIMING 0x00000005 /* Use alternative CS timing for CS0 and CS2 */ | |
8993e54b RJ |
247 | |
248 | /* Use SRAM for initial stack */ | |
6d0f6bcf | 249 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE /* Initial RAM address */ |
553f0982 | 250 | #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_SRAM_SIZE /* Size of used area in RAM */ |
8993e54b | 251 | |
25ddd1fb | 252 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 253 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
8993e54b | 254 | |
14d0a02a | 255 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Start of monitor */ |
229549a5 | 256 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ |
0e1bad47 | 257 | #ifdef CONFIG_FSL_DIU_FB |
6d0f6bcf | 258 | #define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */ |
0e1bad47 | 259 | #else |
6d0f6bcf | 260 | #define CONFIG_SYS_MALLOC_LEN (512 * 1024) |
0e1bad47 | 261 | #endif |
8993e54b RJ |
262 | |
263 | /* | |
264 | * Serial Port | |
265 | */ | |
266 | #define CONFIG_CONS_INDEX 1 | |
8993e54b RJ |
267 | |
268 | /* | |
269 | * Serial console configuration | |
270 | */ | |
271 | #define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 */ | |
bfb31279 | 272 | #define CONFIG_SYS_PSC3 |
8993e54b RJ |
273 | #if CONFIG_PSC_CONSOLE != 3 |
274 | #error CONFIG_PSC_CONSOLE must be 3 | |
275 | #endif | |
6d0f6bcf | 276 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
8993e54b RJ |
277 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
278 | ||
279 | #define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE | |
280 | #define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR | |
281 | #define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE | |
282 | #define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR | |
283 | ||
284 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ | |
8993e54b | 285 | |
e5f53864 AG |
286 | /* |
287 | * Clocks in use | |
288 | */ | |
289 | #define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \ | |
290 | CLOCK_SCCR1_DDR_EN | \ | |
291 | CLOCK_SCCR1_FEC_EN | \ | |
292 | CLOCK_SCCR1_LPC_EN | \ | |
293 | CLOCK_SCCR1_NFC_EN | \ | |
294 | CLOCK_SCCR1_PATA_EN | \ | |
295 | CLOCK_SCCR1_PCI_EN | \ | |
296 | CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \ | |
297 | CLOCK_SCCR1_PSCFIFO_EN | \ | |
298 | CLOCK_SCCR1_TPR_EN) | |
299 | ||
300 | #define SCCR2_CLOCKS_EN (CLOCK_SCCR2_DIU_EN | \ | |
301 | CLOCK_SCCR2_I2C_EN | \ | |
302 | CLOCK_SCCR2_MEM_EN | \ | |
303 | CLOCK_SCCR2_SPDIF_EN | \ | |
304 | CLOCK_SCCR2_USB1_EN | \ | |
305 | CLOCK_SCCR2_USB2_EN) | |
306 | ||
5f91db7f JR |
307 | /* |
308 | * PCI | |
309 | */ | |
310 | #ifdef CONFIG_PCI | |
842033e6 | 311 | #define CONFIG_PCI_INDIRECT_BRIDGE |
5f91db7f JR |
312 | |
313 | /* | |
314 | * General PCI | |
315 | */ | |
6d0f6bcf JCPV |
316 | #define CONFIG_SYS_PCI_MEM_BASE 0xA0000000 |
317 | #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE | |
318 | #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ | |
319 | #define CONFIG_SYS_PCI_MMIO_BASE (CONFIG_SYS_PCI_MEM_BASE + CONFIG_SYS_PCI_MEM_SIZE) | |
320 | #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE | |
321 | #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ | |
322 | #define CONFIG_SYS_PCI_IO_BASE 0x00000000 | |
323 | #define CONFIG_SYS_PCI_IO_PHYS 0x84000000 | |
324 | #define CONFIG_SYS_PCI_IO_SIZE 0x01000000 /* 16M */ | |
5f91db7f | 325 | |
5f91db7f JR |
326 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
327 | ||
328 | #endif | |
329 | ||
abfbd0ae MM |
330 | /* |
331 | * IIM - IC Identification Module | |
332 | */ | |
83306927 | 333 | #undef CONFIG_FSL_IIM |
abfbd0ae | 334 | |
8993e54b RJ |
335 | /* |
336 | * Ethernet configuration | |
337 | */ | |
338 | #define CONFIG_MPC512x_FEC 1 | |
8993e54b RJ |
339 | #define CONFIG_PHY_ADDR 0x1 |
340 | #define CONFIG_MII 1 /* MII PHY management */ | |
f31c49db | 341 | #define CONFIG_FEC_AN_TIMEOUT 1 |
ef11df6b | 342 | #define CONFIG_HAS_ETH0 |
8993e54b | 343 | |
8993e54b RJ |
344 | /* |
345 | * Configure on-board RTC | |
346 | */ | |
f31c49db | 347 | #define CONFIG_RTC_M41T62 /* use M41T62 rtc via i2 */ |
6d0f6bcf | 348 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ |
8993e54b | 349 | |
29c6fbe0 DD |
350 | /* |
351 | * USB Support | |
352 | */ | |
29c6fbe0 DD |
353 | |
354 | #if defined(CONFIG_CMD_USB) | |
29c6fbe0 DD |
355 | #define CONFIG_USB_EHCI_FSL /* On a FSL platform */ |
356 | #define CONFIG_EHCI_MMIO_BIG_ENDIAN /* With big-endian regs */ | |
357 | #define CONFIG_EHCI_DESC_BIG_ENDIAN | |
358 | #define CONFIG_EHCI_IS_TDI | |
29c6fbe0 DD |
359 | #endif |
360 | ||
8993e54b RJ |
361 | /* |
362 | * Environment | |
363 | */ | |
5a1aceb0 | 364 | #define CONFIG_ENV_IS_IN_FLASH 1 |
8993e54b | 365 | /* This has to be a multiple of the Flash sector size */ |
6d0f6bcf | 366 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) |
0e8d1586 | 367 | #define CONFIG_ENV_SIZE 0x2000 |
f31c49db | 368 | #ifdef CONFIG_BKUP_FLASH |
0e8d1586 | 369 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* one sector (256K) for env */ |
f31c49db | 370 | #else |
0e8d1586 | 371 | #define CONFIG_ENV_SECT_SIZE 0x40000 /* one sector (256K) for env */ |
f31c49db | 372 | #endif |
8993e54b RJ |
373 | |
374 | /* Address and size of Redundant Environment Sector */ | |
0e8d1586 JCPV |
375 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) |
376 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
8993e54b RJ |
377 | |
378 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 379 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
8993e54b | 380 | |
e27f3a6e | 381 | #define CONFIG_CMD_REGINFO |
7d4450a9 | 382 | |
8993e54b | 383 | #if defined(CONFIG_PCI) |
e27f3a6e | 384 | #define CONFIG_CMD_PCI |
8993e54b RJ |
385 | #endif |
386 | ||
7d4450a9 WD |
387 | /* |
388 | * Dynamic MTD partition support | |
389 | */ | |
390 | #define CONFIG_CMD_MTDPARTS | |
391 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ | |
392 | #define CONFIG_FLASH_CFI_MTD | |
393 | #define MTDIDS_DEFAULT "nor0=fc000000.flash,nand0=mpc5121.nand" | |
394 | ||
395 | /* | |
396 | * NOR flash layout: | |
397 | * | |
398 | * FC000000 - FEABFFFF 42.75 MiB User Data | |
399 | * FEAC0000 - FFABFFFF 16 MiB Root File System | |
400 | * FFAC0000 - FFEBFFFF 4 MiB Linux Kernel | |
401 | * FFEC0000 - FFEFFFFF 256 KiB Device Tree | |
402 | * FFF00000 - FFFFFFFF 1 MiB U-Boot (up to 512 KiB) and 2 x * env | |
403 | * | |
404 | * NAND flash layout: one big partition | |
405 | */ | |
406 | #define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:43776k(user)," \ | |
407 | "16m(rootfs)," \ | |
408 | "4m(kernel)," \ | |
409 | "256k(dtb)," \ | |
410 | "1m(u-boot);" \ | |
411 | "mpc5121.nand:-(data)" | |
412 | ||
fc843a02 | 413 | #if defined(CONFIG_IDE) || defined(CONFIG_CMD_EXT2) || defined(CONFIG_CMD_USB) |
29c6fbe0 DD |
414 | #define CONFIG_SUPPORT_VFAT |
415 | ||
fc843a02 | 416 | #endif /* defined(CONFIG_IDE) */ |
70a4da45 | 417 | |
8993e54b | 418 | /* |
6d0f6bcf JCPV |
419 | * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock. |
420 | * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE is set | |
8993e54b RJ |
421 | * to 0xFFFF, watchdog timeouts after about 64s. For details refer |
422 | * to chapter 36 of the MPC5121e Reference Manual. | |
423 | */ | |
66ffb188 | 424 | /* #define CONFIG_WATCHDOG */ /* enable watchdog */ |
6d0f6bcf | 425 | #define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF |
8993e54b RJ |
426 | |
427 | /* | |
428 | * Miscellaneous configurable options | |
429 | */ | |
6d0f6bcf JCPV |
430 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
431 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
8993e54b | 432 | |
e27f3a6e | 433 | #ifdef CONFIG_CMD_KGDB |
6d0f6bcf | 434 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
8993e54b | 435 | #else |
6d0f6bcf | 436 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
8993e54b RJ |
437 | #endif |
438 | ||
6d0f6bcf JCPV |
439 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */ |
440 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
441 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
8993e54b RJ |
442 | |
443 | /* | |
444 | * For booting Linux, the board info and command line data | |
9f530d59 | 445 | * have to be in the first 256 MB of memory, since this is |
8993e54b RJ |
446 | * the maximum mapped by the Linux kernel during initialization. |
447 | */ | |
9f530d59 | 448 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/ |
8993e54b RJ |
449 | |
450 | /* Cache Configuration */ | |
6d0f6bcf JCPV |
451 | #define CONFIG_SYS_DCACHE_SIZE 32768 |
452 | #define CONFIG_SYS_CACHELINE_SIZE 32 | |
e27f3a6e | 453 | #ifdef CONFIG_CMD_KGDB |
6d0f6bcf | 454 | #define CONFIG_SYS_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ |
8993e54b RJ |
455 | #endif |
456 | ||
6d0f6bcf | 457 | #define CONFIG_SYS_HID0_INIT 0x000000000 |
e2b66fe4 | 458 | #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | HID0_ICE) |
6d0f6bcf | 459 | #define CONFIG_SYS_HID2 HID2_HBE |
8993e54b | 460 | |
31d82672 BB |
461 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
462 | ||
e27f3a6e | 463 | #ifdef CONFIG_CMD_KGDB |
8993e54b | 464 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ |
8993e54b RJ |
465 | #endif |
466 | ||
467 | /* | |
468 | * Environment Configuration | |
469 | */ | |
66ffb188 | 470 | #define CONFIG_TIMESTAMP |
8993e54b | 471 | |
72601d04 | 472 | #define CONFIG_HOSTNAME mpc5121ads |
b3f44c21 | 473 | #define CONFIG_BOOTFILE "mpc5121ads/uImage" |
8b3637c6 | 474 | #define CONFIG_ROOTPATH "/opt/eldk/ppc_6xx" |
8993e54b | 475 | |
8d103071 | 476 | #define CONFIG_LOADADDR 400000 /* default location for tftp and bootm */ |
8993e54b | 477 | |
8993e54b RJ |
478 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ |
479 | ||
8993e54b | 480 | #define CONFIG_PREBOOT "echo;" \ |
5b0b2b6f | 481 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
8993e54b RJ |
482 | "echo" |
483 | ||
484 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
8d103071 | 485 | "u-boot_addr_r=200000\0" \ |
51e46e28 WD |
486 | "kernel_addr_r=600000\0" \ |
487 | "fdt_addr_r=880000\0" \ | |
488 | "ramdisk_addr_r=900000\0" \ | |
8d103071 | 489 | "u-boot_addr=FFF00000\0" \ |
7d4450a9 | 490 | "kernel_addr=FFAC0000\0" \ |
51e46e28 | 491 | "fdt_addr=FFEC0000\0" \ |
7d4450a9 | 492 | "ramdisk_addr=FEAC0000\0" \ |
72601d04 WD |
493 | "ramdiskfile=mpc5121ads/uRamdisk\0" \ |
494 | "u-boot=mpc5121ads/u-boot.bin\0" \ | |
495 | "bootfile=mpc5121ads/uImage\0" \ | |
496 | "fdtfile=mpc5121ads/mpc5121ads.dtb\0" \ | |
51e46e28 | 497 | "rootpath=/opt/eldk/ppc_6xx\n" \ |
8993e54b | 498 | "netdev=eth0\0" \ |
8d103071 | 499 | "consdev=ttyPSC0\0" \ |
8993e54b RJ |
500 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
501 | "nfsroot=${serverip}:${rootpath}\0" \ | |
502 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
503 | "addip=setenv bootargs ${bootargs} " \ | |
504 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
505 | ":${hostname}:${netdev}:off panic=1\0" \ | |
8d103071 WD |
506 | "addtty=setenv bootargs ${bootargs} " \ |
507 | "console=${consdev},${baudrate}\0" \ | |
8993e54b | 508 | "flash_nfs=run nfsargs addip addtty;" \ |
a99715b8 | 509 | "bootm ${kernel_addr} - ${fdt_addr}\0" \ |
8993e54b | 510 | "flash_self=run ramargs addip addtty;" \ |
8d103071 WD |
511 | "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ |
512 | "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ | |
513 | "tftp ${fdt_addr_r} ${fdtfile};" \ | |
514 | "run nfsargs addip addtty;" \ | |
515 | "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ | |
516 | "net_self=tftp ${kernel_addr_r} ${bootfile};" \ | |
517 | "tftp ${ramdisk_addr_r} ${ramdiskfile};" \ | |
a99715b8 | 518 | "tftp ${fdt_addr_r} ${fdtfile};" \ |
8d103071 | 519 | "run ramargs addip addtty;" \ |
5b0b2b6f | 520 | "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\ |
a99715b8 | 521 | "load=tftp ${u-boot_addr_r} ${u-boot}\0" \ |
8d103071 WD |
522 | "update=protect off ${u-boot_addr} +${filesize};" \ |
523 | "era ${u-boot_addr} +${filesize};" \ | |
524 | "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \ | |
525 | "upd=run load update\0" \ | |
8993e54b RJ |
526 | "" |
527 | ||
8993e54b RJ |
528 | #define CONFIG_BOOTCOMMAND "run flash_self" |
529 | ||
ef11df6b | 530 | #define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES 1 |
281ff9a4 GB |
531 | |
532 | #define OF_CPU "PowerPC,5121@0" | |
ef11df6b | 533 | #define OF_SOC_COMPAT "fsl,mpc5121-immr" |
281ff9a4 | 534 | #define OF_TBCLK (bd->bi_busfreq / 4) |
ac915283 | 535 | #define OF_STDOUT_PATH "/soc@80000000/serial@11300" |
281ff9a4 | 536 | |
70a4da45 RK |
537 | /*----------------------------------------------------------------------- |
538 | * IDE/ATA stuff | |
539 | *----------------------------------------------------------------------- | |
540 | */ | |
541 | ||
542 | #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ | |
543 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ | |
544 | #undef CONFIG_IDE_LED /* LED for IDE not supported */ | |
545 | ||
546 | #define CONFIG_IDE_RESET /* reset for IDE supported */ | |
547 | #define CONFIG_IDE_PREINIT | |
548 | ||
549 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ | |
550 | #define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */ | |
551 | ||
552 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 | |
3b74e7ec | 553 | #define CONFIG_SYS_ATA_BASE_ADDR get_pata_base() |
70a4da45 RK |
554 | |
555 | /* Offset for data I/O RefMan MPC5121EE Table 28-10 */ | |
556 | #define CONFIG_SYS_ATA_DATA_OFFSET (0x00A0) | |
557 | ||
558 | /* Offset for normal register accesses */ | |
559 | #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) | |
560 | ||
561 | /* Offset for alternate registers RefMan MPC5121EE Table 28-23 */ | |
562 | #define CONFIG_SYS_ATA_ALT_OFFSET (0x00D8) | |
563 | ||
564 | /* Interval between registers */ | |
565 | #define CONFIG_SYS_ATA_STRIDE 4 | |
566 | ||
3b74e7ec | 567 | #define ATA_BASE_ADDR get_pata_base() |
70a4da45 RK |
568 | |
569 | /* | |
570 | * Control register bit definitions | |
571 | */ | |
572 | #define FSL_ATA_CTRL_FIFO_RST_B 0x80000000 | |
573 | #define FSL_ATA_CTRL_ATA_RST_B 0x40000000 | |
574 | #define FSL_ATA_CTRL_FIFO_TX_EN 0x20000000 | |
575 | #define FSL_ATA_CTRL_FIFO_RCV_EN 0x10000000 | |
576 | #define FSL_ATA_CTRL_DMA_PENDING 0x08000000 | |
577 | #define FSL_ATA_CTRL_DMA_ULTRA 0x04000000 | |
578 | #define FSL_ATA_CTRL_DMA_WRITE 0x02000000 | |
579 | #define FSL_ATA_CTRL_IORDY_EN 0x01000000 | |
580 | ||
8993e54b | 581 | #endif /* __CONFIG_H */ |