[people/ms/u-boot.git] / include / configs / mpc8308_p1m.h

/*
 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
 * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
 *
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_E300		1 /* E300 family */
#define CONFIG_MPC83xx		1 /* MPC83xx family */
#define CONFIG_MPC8308		1 /* MPC8308 CPU specific */
#define CONFIG_MPC8308_P1M	1 /* mpc8308_p1m board specific */

#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE	0xFC000000
#endif

/*
 * On-board devices
 *
 * TSECs
 */
#define CONFIG_TSEC1
#define CONFIG_TSEC2

/*
 * System Clock Setup
 */
#define CONFIG_83XX_CLKIN	33333333 /* in Hz */
#define CONFIG_SYS_CLK_FREQ	CONFIG_83XX_CLKIN

/*
 * Hardware Reset Configuration Word
 * if CLKIN is 66.66MHz, then
 * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
 * We choose the A type silicon as default, so the core is 400Mhz.
 */
#define CONFIG_SYS_HRCW_LOW (\
	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
	HRCWL_DDR_TO_SCB_CLK_2X1 |\
	HRCWL_SVCOD_DIV_2 |\
	HRCWL_CSB_TO_CLKIN_4X1 |\
	HRCWL_CORE_TO_CSB_3X1)
/*
 * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
 * in 8308's HRCWH according to the manual, but original Freescale's
 * code has them and I've expirienced some problems using the board
 * with BDI3000 attached when I've tried to set these bits to zero
 * (UART doesn't work after the 'reset run' command).
 */
#define CONFIG_SYS_HRCW_HIGH (\
	HRCWH_PCI_HOST |\
	HRCWH_PCI1_ARBITER_ENABLE |\
	HRCWH_CORE_ENABLE |\
	HRCWH_FROM_0X00000100 |\
	HRCWH_BOOTSEQ_DISABLE |\
	HRCWH_SW_WATCHDOG_DISABLE |\
	HRCWH_ROM_LOC_LOCAL_16BIT |\
	HRCWH_RL_EXT_LEGACY |\
	HRCWH_TSEC1M_IN_MII |\
	HRCWH_TSEC2M_IN_MII |\
	HRCWH_BIG_ENDIAN)

/*
 * System IO Config
 */
#define CONFIG_SYS_SICRH (\
	SICRH_ESDHC_A_GPIO |\
	SICRH_ESDHC_B_GPIO |\
	SICRH_ESDHC_C_GTM |\
	SICRH_GPIO_A_TSEC2 |\
	SICRH_GPIO_B_TSEC2_TX_CLK |\
	SICRH_IEEE1588_A_GPIO |\
	SICRH_USB |\
	SICRH_GTM_GPIO |\
	SICRH_IEEE1588_B_GPIO |\
	SICRH_ETSEC2_CRS |\
	SICRH_GPIOSEL_1 |\
	SICRH_TMROBI_V3P3 |\
	SICRH_TSOBI1_V3P3 |\
	SICRH_TSOBI2_V3P3)	/* 0xf577d100 */
#define CONFIG_SYS_SICRL (\
	SICRL_SPI_PF0 |\
	SICRL_UART_PF0 |\
	SICRL_IRQ_PF0 |\
	SICRL_I2C2_PF0 |\
	SICRL_ETSEC1_TX_CLK)	/* 0x00000000 */

#define CONFIG_SYS_GPIO1_PRELIM
/* GPIO Default input/output settings */
#define CONFIG_SYS_GPIO1_DIR        0x7AAF8C00
/*
 * Default GPIO values:
 * LED#1 enabled; WLAN enabled; Both COM LED on (orange)
 */
#define CONFIG_SYS_GPIO1_DAT        0x08008C00

/*
 * IMMR new address
 */
#define CONFIG_SYS_IMMR		0xE0000000

/*
 * SERDES
 */
#define CONFIG_FSL_SERDES
#define CONFIG_FSL_SERDES1	0xe3000

/*
 * Arbiter Setup
 */
#define CONFIG_SYS_ACR_PIPE_DEP	3 /* Arbiter pipeline depth is 4 */
#define CONFIG_SYS_ACR_RPTCNT	3 /* Arbiter repeat count is 4 */
#define CONFIG_SYS_SPCR_TSECEP	3 /* eTSEC emergency priority is highest */

/*
 * DDR Setup
 */
#define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory */
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
#define CONFIG_SYS_DDRCDR_VALUE	(DDRCDR_EN \
				| DDRCDR_PZ_LOZ \
				| DDRCDR_NZ_LOZ \
				| DDRCDR_ODT \
				| DDRCDR_Q_DRN)
				/* 0x7b880001 */
/*
 * Manually set up DDR parameters
 * consist of two chips HY5PS12621BFP-C4 from HYNIX
 */

#define CONFIG_SYS_DDR_SIZE		128 /* MB */

#define CONFIG_SYS_DDR_CS0_BNDS	0x00000007
#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
				| 0x00010000  /* ODT_WR to CSn */ \
				| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
				/* 0x80010102 */
#define CONFIG_SYS_DDR_TIMING_3	0x00000000
#define CONFIG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
				| (0 << TIMING_CFG0_WRT_SHIFT) \
				| (0 << TIMING_CFG0_RRT_SHIFT) \
				| (0 << TIMING_CFG0_WWT_SHIFT) \
				| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
				| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
				| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
				| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
				/* 0x00220802 */
#define CONFIG_SYS_DDR_TIMING_1	((2 << TIMING_CFG1_PRETOACT_SHIFT) \
				| (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
				| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
				| (5 << TIMING_CFG1_CASLAT_SHIFT) \
				| (6 << TIMING_CFG1_REFREC_SHIFT) \
				| (2 << TIMING_CFG1_WRREC_SHIFT) \
				| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
				| (2 << TIMING_CFG1_WRTORD_SHIFT))
				/* 0x27256222 */
#define CONFIG_SYS_DDR_TIMING_2	((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
				| (4 << TIMING_CFG2_CPO_SHIFT) \
				| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
				| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
				| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
				| (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
				/* 0x121048c5 */
#define CONFIG_SYS_DDR_INTERVAL	((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
				| (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
				/* 0x03600100 */
#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SREN \
				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
				| SDRAM_CFG_32_BE)
				/* 0x43080000 */

#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000 /* 1 posted refresh */
#define CONFIG_SYS_DDR_MODE		((0x0448 << SDRAM_MODE_ESD_SHIFT) \
				| (0x0232 << SDRAM_MODE_SD_SHIFT))
				/* ODT 150ohm CL=3, AL=1 on SDRAM */
#define CONFIG_SYS_DDR_MODE2		0x00000000

/*
 * Memory test
 */
#define CONFIG_SYS_MEMTEST_START	0x00001000 /* memtest region */
#define CONFIG_SYS_MEMTEST_END		0x07f00000

/*
 * The reserved memory
 */
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE /* start of monitor */

#define CONFIG_SYS_MONITOR_LEN	(384 * 1024) /* Reserve 384 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN	(512 * 1024) /* Reserved for malloc */

/*
 * Initial RAM Base Address Setup
 */
#define CONFIG_SYS_INIT_RAM_LOCK	1
#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE		0x1000 /* Size of used area in RAM */
#define CONFIG_SYS_GBL_DATA_SIZE	0x100 /* num bytes initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET	\
	(CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE)

/*
 * Local Bus Configuration & Clock Setup
 */
#define CONFIG_SYS_LCRR_DBYP		LCRR_DBYP
#define CONFIG_SYS_LCRR_CLKDIV		LCRR_CLKDIV_2
#define CONFIG_SYS_LBC_LBCR		0x00040000

/*
 * FLASH on the Local Bus
 */
#define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
#define CONFIG_FLASH_CFI_DRIVER		/* use the CFI driver */
#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT

#define CONFIG_SYS_FLASH_BASE		0xFC000000 /* FLASH base address */
#define CONFIG_SYS_FLASH_SIZE		64 /* FLASH size is 64M */
#define CONFIG_SYS_FLASH_PROTECTION	1 /* Use h/w Flash protection. */

/* Window base at flash base */
#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_64MB)

#define CONFIG_SYS_BR0_PRELIM	(\
		CONFIG_SYS_FLASH_BASE	/* Flash Base address */	|\
		(2 << BR_PS_SHIFT)	/* 16 bit port size */		|\
		BR_V)			/* valid */
#define CONFIG_SYS_OR0_PRELIM	((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
				| OR_UPM_XAM \
				| OR_GPCM_CSNT \
				| OR_GPCM_ACS_DIV2 \
				| OR_GPCM_XACS \
				| OR_GPCM_SCY_4 \
				| OR_GPCM_TRLX \
				| OR_GPCM_EHTR \
				| OR_GPCM_EAD)

#define CONFIG_SYS_MAX_FLASH_BANKS	1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	512

/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_ERASE_TOUT	(1000 * 1024)
/* Flash Write Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	(500 * 1024)

/*
 * SJA1000 CAN controller on Local Bus
 */
#define CONFIG_SYS_SJA1000_BASE		0xFBFF0000
#define CONFIG_SYS_BR1_PRELIM	( CONFIG_SYS_SJA1000_BASE \
				| (1 << BR_PS_SHIFT)	/* 8 bit port size */ \
				| BR_V )		/* valid */
#define CONFIG_SYS_OR1_PRELIM	( 0xFFFF8000		/* length 32K */ \
				| OR_GPCM_SCY_5 \
				| OR_GPCM_EHTR)
				/* 0xFFFF8052 */

#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_SJA1000_BASE
#define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_32KB)

/*
 * CPLD on Local Bus
 */
#define CONFIG_SYS_CPLD_BASE		0xFBFF8000
#define CONFIG_SYS_BR2_PRELIM	( CONFIG_SYS_CPLD_BASE \
				| (1 << BR_PS_SHIFT)	/* 8 bit port size */ \
				| BR_V )		/* valid */
#define CONFIG_SYS_OR2_PRELIM	( 0xFFFF8000		/* length 32K */ \
				| OR_GPCM_SCY_4 \
				| OR_GPCM_EHTR)
				/* 0xFFFF8042 */

#define CONFIG_SYS_LBLAWBAR2_PRELIM	CONFIG_SYS_CPLD_BASE
#define CONFIG_SYS_LBLAWAR2_PRELIM	(LBLAWAR_EN | LBLAWAR_32KB)

/*
 * Serial Port
 */
#define CONFIG_CONS_INDEX	1
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#define CONFIG_SYS_BAUDRATE_TABLE  \
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR + 0x4500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR + 0x4600)

/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "

/* Pass open firmware flat tree */
#define CONFIG_OF_LIBFDT	1
#define CONFIG_OF_BOARD_SETUP	1
#define CONFIG_OF_STDOUT_VIA_ALIAS	1

/* I2C */
#define CONFIG_HARD_I2C		/* I2C with hardware support */
#define CONFIG_FSL_I2C
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_SYS_I2C_SPEED	400000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE	0x7F
#define CONFIG_SYS_I2C_OFFSET	0x3000
#define CONFIG_SYS_I2C2_OFFSET	0x3100

/*
 * General PCI
 * Addresses are mapped 1-1.
 */
#define CONFIG_SYS_PCIE1_BASE		0xA0000000
#define CONFIG_SYS_PCIE1_MEM_BASE	0xA0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS	0xA0000000
#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000
#define CONFIG_SYS_PCIE1_CFG_BASE	0xB0000000
#define CONFIG_SYS_PCIE1_CFG_SIZE	0x01000000
#define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS	0xB1000000
#define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000

/* enable PCIE clock */
#define CONFIG_SYS_SCCR_PCIEXP1CM	1

#define CONFIG_PCI
#define CONFIG_PCIE

#define CONFIG_PCI_PNP		/* do pci plug-and-play */

#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1

/*
 * TSEC
 */
#define CONFIG_NET_MULTI
#define CONFIG_TSEC_ENET	/* TSEC ethernet support */
#define CONFIG_SYS_TSEC1_OFFSET	0x24000
#define CONFIG_SYS_TSEC1	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
#define CONFIG_SYS_TSEC2_OFFSET	0x25000
#define CONFIG_SYS_TSEC2	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)

/*
 * TSEC ethernet configuration
 */
#define CONFIG_MII		1 /* MII PHY management */
#define CONFIG_TSEC1_NAME	"eTSEC0"
#define CONFIG_TSEC2_NAME	"eTSEC1"
#define TSEC1_PHY_ADDR		1
#define TSEC2_PHY_ADDR		2
#define TSEC1_PHYIDX		0
#define TSEC2_PHYIDX		0
#define TSEC1_FLAGS		0
#define TSEC2_FLAGS		0

/* Options are: eTSEC[0-1] */
#define CONFIG_ETHPRIME		"eTSEC0"

/*
 * Environment
 */
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + \
				 CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K(one sector) for env */
#define CONFIG_ENV_SIZE		0x2000
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_DHCP
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING

#define CONFIG_CMDLINE_EDITING	1	/* add command line history */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_SYS_LOAD_ADDR		0x2000000 /* default load address */
#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt */

#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size */

/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
#define CONFIG_SYS_HZ		1000	/* decrementer freq: 1ms ticks */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(256 << 20) /* Initial Memory map for Linux */

/*
 * Core HID Setup
 */
#define CONFIG_SYS_HID0_INIT	0x000000000
#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
				 HID0_ENABLE_INSTRUCTION_CACHE | \
				 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
#define CONFIG_SYS_HID2		HID2_HBE

/*
 * MMU Setup
 */

/* DDR: cache cacheable */
#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \
					BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
					BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U

/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_IMMR | BATL_PP_10 | \
			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
					BATU_VP)
#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U

/* FLASH: icache cacheable, but dcache-inhibit and guarded */
#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
					BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
					BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT2L	(CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
					BATL_CACHEINHIBIT | \
					BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U

/* Stack in dcache: cacheable, no memory coherence */
#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
					BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U

/*
 * Environment Configuration
 */

#define CONFIG_ENV_OVERWRITE

#if defined(CONFIG_TSEC_ENET)
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#endif

#define CONFIG_BAUDRATE 115200

#define CONFIG_LOADADDR	800000	/* default location for tftp and bootm */

#define CONFIG_BOOTDELAY	5	/* -1 disables auto-boot */

#define xstr(s)	str(s)
#define str(s)	#s

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"consoledev=ttyS0\0"						\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"addtty=setenv bootargs ${bootargs}"				\
		" console=${consoledev},${baudrate}\0"			\
	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
	"addmisc=setenv bootargs ${bootargs}\0"				\
	"kernel_addr=FC0A0000\0"					\
	"fdt_addr=FC2A0000\0"						\
	"ramdisk_addr=FC2C0000\0"					\
	"u-boot=mpc8308_p1m/u-boot.bin\0"				\
	"kernel_addr_r=1000000\0"					\
	"fdt_addr_r=C00000\0"						\
	"hostname=mpc8308_p1m\0"					\
	"bootfile=mpc8308_p1m/uImage\0"					\
	"fdtfile=mpc8308_p1m/mpc8308_p1m.dtb\0"				\
	"rootpath=/opt/eldk-4.2/ppc_6xx\0"				\
	"flash_self=run ramargs addip addtty addmtd addmisc;"		\
		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
	"flash_nfs=run nfsargs addip addtty addmtd addmisc;"		\
		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
		"tftp ${fdt_addr_r} ${fdtfile};"			\
		"run nfsargs addip addtty addmtd addmisc;"		\
		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
	"bootcmd=run flash_self\0"					\
	"load=tftp ${loadaddr} ${u-boot}\0"				\
	"update=protect off " xstr(CONFIG_SYS_MONITOR_BASE)		\
		" +${filesize};era " xstr(CONFIG_SYS_MONITOR_BASE)	\
		" +${filesize};cp.b ${fileaddr} "			\
		xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"		\
	"upd=run load update\0"						\

#endif	/* __CONFIG_H */
Commit	Line	Data
bc8f8c26 IY	1	/*
	2	* Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
	3	* Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
	4	*
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	#ifndef __CONFIG_H
	26	#define __CONFIG_H
	27
	28	/*
	29	* High Level Configuration Options
	30	*/
	31	#define CONFIG_E300 1 /* E300 family */
	32	#define CONFIG_MPC83xx 1 /* MPC83xx family */
	33	#define CONFIG_MPC8308 1 /* MPC8308 CPU specific */
	34	#define CONFIG_MPC8308_P1M 1 /* mpc8308_p1m board specific */
	35
2ae18241 WD	36	#ifndef CONFIG_SYS_TEXT_BASE
	37	#define CONFIG_SYS_TEXT_BASE 0xFC000000
	38	#endif
	39
bc8f8c26 IY	40	/*
	41	* On-board devices
	42	*
	43	* TSECs
	44	*/
	45	#define CONFIG_TSEC1
	46	#define CONFIG_TSEC2
	47
	48	/*
	49	* System Clock Setup
	50	*/
	51	#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
	52	#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
	53
	54	/*
	55	* Hardware Reset Configuration Word
	56	* if CLKIN is 66.66MHz, then
	57	* CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
	58	* We choose the A type silicon as default, so the core is 400Mhz.
	59	*/
	60	#define CONFIG_SYS_HRCW_LOW (\
	61	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 \|\
	62	HRCWL_DDR_TO_SCB_CLK_2X1 \|\
	63	HRCWL_SVCOD_DIV_2 \|\
	64	HRCWL_CSB_TO_CLKIN_4X1 \|\
	65	HRCWL_CORE_TO_CSB_3X1)
	66	/*
	67	* There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
	68	* in 8308's HRCWH according to the manual, but original Freescale's
	69	* code has them and I've expirienced some problems using the board
	70	* with BDI3000 attached when I've tried to set these bits to zero
	71	* (UART doesn't work after the 'reset run' command).
	72	*/
	73	#define CONFIG_SYS_HRCW_HIGH (\
	74	HRCWH_PCI_HOST \|\
	75	HRCWH_PCI1_ARBITER_ENABLE \|\
	76	HRCWH_CORE_ENABLE \|\
	77	HRCWH_FROM_0X00000100 \|\
	78	HRCWH_BOOTSEQ_DISABLE \|\
	79	HRCWH_SW_WATCHDOG_DISABLE \|\
	80	HRCWH_ROM_LOC_LOCAL_16BIT \|\
	81	HRCWH_RL_EXT_LEGACY \|\
	82	HRCWH_TSEC1M_IN_MII \|\
	83	HRCWH_TSEC2M_IN_MII \|\
	84	HRCWH_BIG_ENDIAN)
	85
	86	/*
	87	* System IO Config
	88	*/
	89	#define CONFIG_SYS_SICRH (\
	90	SICRH_ESDHC_A_GPIO \|\
	91	SICRH_ESDHC_B_GPIO \|\
	92	SICRH_ESDHC_C_GTM \|\
	93	SICRH_GPIO_A_TSEC2 \|\
	94	SICRH_GPIO_B_TSEC2_TX_CLK \|\
	95	SICRH_IEEE1588_A_GPIO \|\
	96	SICRH_USB \|\
	97	SICRH_GTM_GPIO \|\
	98	SICRH_IEEE1588_B_GPIO \|\
	99	SICRH_ETSEC2_CRS \|\
	100	SICRH_GPIOSEL_1 \|\
	101	SICRH_TMROBI_V3P3 \|\
	102	SICRH_TSOBI1_V3P3 \|\
	103	SICRH_TSOBI2_V3P3) /* 0xf577d100 */
104	#define CONFIG_SYS_SICRL (\
105	SICRL_SPI_PF0 \|\
106	SICRL_UART_PF0 \|\
107	SICRL_IRQ_PF0 \|\
108	SICRL_I2C2_PF0 \|\
109	SICRL_ETSEC1_TX_CLK) /* 0x00000000 */
110
111	#define CONFIG_SYS_GPIO1_PRELIM
112	/* GPIO Default input/output settings */
113	#define CONFIG_SYS_GPIO1_DIR 0x7AAF8C00
114	/*
115	* Default GPIO values:
116	* LED#1 enabled; WLAN enabled; Both COM LED on (orange)
117	*/
118	#define CONFIG_SYS_GPIO1_DAT 0x08008C00
119
120	/*
121	* IMMR new address
122	*/
123	#define CONFIG_SYS_IMMR 0xE0000000
124
125	/*
126	* SERDES
127	*/
128	#define CONFIG_FSL_SERDES
129	#define CONFIG_FSL_SERDES1 0xe3000
130
131	/*
132	* Arbiter Setup
133	*/
134	#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
135	#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
136	#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
137
138	/*
139	* DDR Setup
140	*/
141	#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
142	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
143	#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
144	#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
145	#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
146	\| DDRCDR_PZ_LOZ \
147	\| DDRCDR_NZ_LOZ \
148	\| DDRCDR_ODT \
149	\| DDRCDR_Q_DRN)
150	/* 0x7b880001 */
151	/*
152	* Manually set up DDR parameters
153	* consist of two chips HY5PS12621BFP-C4 from HYNIX
154	*/
155
156	#define CONFIG_SYS_DDR_SIZE 128 /* MB */
157
158	#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
159	#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
160	\| 0x00010000 /* ODT_WR to CSn */ \
161	\| CSCONFIG_ROW_BIT_13 \| CSCONFIG_COL_BIT_10)
162	/* 0x80010102 */
163	#define CONFIG_SYS_DDR_TIMING_3 0x00000000
164	#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
165	\| (0 << TIMING_CFG0_WRT_SHIFT) \
166	\| (0 << TIMING_CFG0_RRT_SHIFT) \
167	\| (0 << TIMING_CFG0_WWT_SHIFT) \
168	\| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
169	\| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
170	\| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
171	\| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
172	/* 0x00220802 */
173	#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
174	\| (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
175	\| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
176	\| (5 << TIMING_CFG1_CASLAT_SHIFT) \
177	\| (6 << TIMING_CFG1_REFREC_SHIFT) \
178	\| (2 << TIMING_CFG1_WRREC_SHIFT) \
179	\| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
180	\| (2 << TIMING_CFG1_WRTORD_SHIFT))
181	/* 0x27256222 */
182	#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
183	\| (4 << TIMING_CFG2_CPO_SHIFT) \
184	\| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
185	\| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
186	\| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
187	\| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
188	\| (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
189	/* 0x121048c5 */
190	#define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
191	\| (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
192	/* 0x03600100 */
193	#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
194	\| SDRAM_CFG_SDRAM_TYPE_DDR2 \
195	\| SDRAM_CFG_32_BE)
196	/* 0x43080000 */
197
198	#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
199	#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
200	\| (0x0232 << SDRAM_MODE_SD_SHIFT))
201	/* ODT 150ohm CL=3, AL=1 on SDRAM */
202	#define CONFIG_SYS_DDR_MODE2 0x00000000
203
204	/*
205	* Memory test
206	*/
207	#define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */
208	#define CONFIG_SYS_MEMTEST_END 0x07f00000
209
210	/*
211	* The reserved memory
212	*/
14d0a02a	213	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
bc8f8c26 IY	214
	215	#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
	216	#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
	217
	218	/*
	219	* Initial RAM Base Address Setup
	220	*/
	221	#define CONFIG_SYS_INIT_RAM_LOCK 1
	222	#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
553f0982	223	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
bc8f8c26 IY	224	#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
bc8f8c26 IY	225	#define CONFIG_SYS_GBL_DATA_OFFSET \
553f0982	226	(CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE)
bc8f8c26 IY	227
	228	/*
	229	* Local Bus Configuration & Clock Setup
	230	*/
	231	#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
	232	#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
	233	#define CONFIG_SYS_LBC_LBCR 0x00040000
	234
	235	/*
	236	* FLASH on the Local Bus
	237	*/
	238	#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
	239	#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
	240	#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
	241
	242	#define CONFIG_SYS_FLASH_BASE 0xFC000000 /* FLASH base address */
	243	#define CONFIG_SYS_FLASH_SIZE 64 /* FLASH size is 64M */
	244	#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
	245
	246	/* Window base at flash base */
	247	#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
	248	#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN \| LBLAWAR_64MB)
	249
	250	#define CONFIG_SYS_BR0_PRELIM (\
	251	CONFIG_SYS_FLASH_BASE /* Flash Base address */ \|\
	252	(2 << BR_PS_SHIFT) /* 16 bit port size */ \|\
	253	BR_V) /* valid */
	254	#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
	255	\| OR_UPM_XAM \
	256	\| OR_GPCM_CSNT \
	257	\| OR_GPCM_ACS_DIV2 \
	258	\| OR_GPCM_XACS \
	259	\| OR_GPCM_SCY_4 \
	260	\| OR_GPCM_TRLX \
	261	\| OR_GPCM_EHTR \
	262	\| OR_GPCM_EAD)
	263
	264	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
	265	#define CONFIG_SYS_MAX_FLASH_SECT 512
	266
	267	/* Flash Erase Timeout (ms) */
	268	#define CONFIG_SYS_FLASH_ERASE_TOUT (1000 * 1024)
	269	/* Flash Write Timeout (ms) */
	270	#define CONFIG_SYS_FLASH_WRITE_TOUT (500 * 1024)
	271
	272	/*
	273	* SJA1000 CAN controller on Local Bus
	274	*/
	275	#define CONFIG_SYS_SJA1000_BASE 0xFBFF0000
	276	#define CONFIG_SYS_BR1_PRELIM ( CONFIG_SYS_SJA1000_BASE \
	277	\| (1 << BR_PS_SHIFT) /* 8 bit port size */ \
	278	\| BR_V ) /* valid */
	279	#define CONFIG_SYS_OR1_PRELIM ( 0xFFFF8000 /* length 32K */ \
	280	\| OR_GPCM_SCY_5 \
	281	\| OR_GPCM_EHTR)
	282	/* 0xFFFF8052 */
	283
	284	#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_SJA1000_BASE
	285	#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN \| LBLAWAR_32KB)
	286
	287	/*
	288	* CPLD on Local Bus
	289	*/
	290	#define CONFIG_SYS_CPLD_BASE 0xFBFF8000
291	#define CONFIG_SYS_BR2_PRELIM ( CONFIG_SYS_CPLD_BASE \
292	\| (1 << BR_PS_SHIFT) /* 8 bit port size */ \
293	\| BR_V ) /* valid */
294	#define CONFIG_SYS_OR2_PRELIM ( 0xFFFF8000 /* length 32K */ \
295	\| OR_GPCM_SCY_4 \
296	\| OR_GPCM_EHTR)
297	/* 0xFFFF8042 */
298
299	#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_CPLD_BASE
300	#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN \| LBLAWAR_32KB)
301
302	/*
303	* Serial Port
304	*/
305	#define CONFIG_CONS_INDEX 1
306	#undef CONFIG_SERIAL_SOFTWARE_FIFO
307	#define CONFIG_SYS_NS16550
308	#define CONFIG_SYS_NS16550_SERIAL
309	#define CONFIG_SYS_NS16550_REG_SIZE 1
310	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
311
312	#define CONFIG_SYS_BAUDRATE_TABLE \
313	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
314
315	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
316	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
317
318	/* Use the HUSH parser */
319	#define CONFIG_SYS_HUSH_PARSER
320	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
321
322	/* Pass open firmware flat tree */
323	#define CONFIG_OF_LIBFDT 1
324	#define CONFIG_OF_BOARD_SETUP 1
325	#define CONFIG_OF_STDOUT_VIA_ALIAS 1
326
327	/* I2C */
328	#define CONFIG_HARD_I2C /* I2C with hardware support */
329	#define CONFIG_FSL_I2C
330	#define CONFIG_I2C_MULTI_BUS
331	#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
332	#define CONFIG_SYS_I2C_SLAVE 0x7F
333	#define CONFIG_SYS_I2C_OFFSET 0x3000
334	#define CONFIG_SYS_I2C2_OFFSET 0x3100
335
336	/*
337	* General PCI
338	* Addresses are mapped 1-1.
339	*/
340	#define CONFIG_SYS_PCIE1_BASE 0xA0000000
341	#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
342	#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
343	#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
344	#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
345	#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
346	#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
347	#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
348	#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
349
350	/* enable PCIE clock */
351	#define CONFIG_SYS_SCCR_PCIEXP1CM 1
352
353	#define CONFIG_PCI
354	#define CONFIG_PCIE
355
356	#define CONFIG_PCI_PNP /* do pci plug-and-play */
357
358	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
359	#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
360
361	/*
362	* TSEC
363	*/
364	#define CONFIG_NET_MULTI
365	#define CONFIG_TSEC_ENET /* TSEC ethernet support */
366	#define CONFIG_SYS_TSEC1_OFFSET 0x24000
367	#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
368	#define CONFIG_SYS_TSEC2_OFFSET 0x25000
369	#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
370
371	/*
372	* TSEC ethernet configuration
373	*/
374	#define CONFIG_MII 1 /* MII PHY management */
375	#define CONFIG_TSEC1_NAME "eTSEC0"
376	#define CONFIG_TSEC2_NAME "eTSEC1"
377	#define TSEC1_PHY_ADDR 1
378	#define TSEC2_PHY_ADDR 2
379	#define TSEC1_PHYIDX 0
380	#define TSEC2_PHYIDX 0
381	#define TSEC1_FLAGS 0
382	#define TSEC2_FLAGS 0
383
384	/* Options are: eTSEC[0-1] */
385	#define CONFIG_ETHPRIME "eTSEC0"
386
387	/*
388	* Environment
389	*/
390	#define CONFIG_ENV_IS_IN_FLASH 1
391	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
392	CONFIG_SYS_MONITOR_LEN)
393	#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
394	#define CONFIG_ENV_SIZE 0x2000
395	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
396	#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
397
398	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
399	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
400
401	/*
402	* BOOTP options
403	*/
404	#define CONFIG_BOOTP_BOOTFILESIZE
405	#define CONFIG_BOOTP_BOOTPATH
406	#define CONFIG_BOOTP_GATEWAY
407	#define CONFIG_BOOTP_HOSTNAME
408
409	/*
410	* Command line configuration.
411	*/
412	#include <config_cmd_default.h>
413
414	#define CONFIG_CMD_DHCP
415	#define CONFIG_CMD_I2C
416	#define CONFIG_CMD_MII
417	#define CONFIG_CMD_NET
418	#define CONFIG_CMD_PCI
419	#define CONFIG_CMD_PING
420
421	#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
422
423	/*
424	* Miscellaneous configurable options
425	*/
426	#define CONFIG_SYS_LONGHELP /* undef to save memory */
427	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
428	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
429
430	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
431
432	/* Print Buffer Size */
433	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
434	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
435	/* Boot Argument Buffer Size */
436	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
437	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
438
439	/*
440	* For booting Linux, the board info and command line data
441	* have to be in the first 8 MB of memory, since this is
442	* the maximum mapped by the Linux kernel during initialization.
443	*/
9eda770b	444	#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
bc8f8c26 IY	445
	446	/*
	447	* Core HID Setup
	448	*/
	449	#define CONFIG_SYS_HID0_INIT 0x000000000
	450	#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \| \
	451	HID0_ENABLE_INSTRUCTION_CACHE \| \
	452	HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
	453	#define CONFIG_SYS_HID2 HID2_HBE
	454
	455	/*
	456	* MMU Setup
	457	*/
	458
	459	/* DDR: cache cacheable */
	460	#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \| BATL_PP_10 \| \
	461	BATL_MEMCOHERENCE)
	462	#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \| BATU_BL_128M \| \
	463	BATU_VS \| BATU_VP)
	464	#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
	465	#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
	466
	467	/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
	468	#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \| BATL_PP_10 \| \
	469	BATL_CACHEINHIBIT \| BATL_GUARDEDSTORAGE)
	470	#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \| BATU_BL_8M \| BATU_VS \| \
	471	BATU_VP)
	472	#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
	473	#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
	474
	475	/* FLASH: icache cacheable, but dcache-inhibit and guarded */
	476	#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE \| BATL_PP_10 \| \
	477	BATL_MEMCOHERENCE)
	478	#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE \| BATU_BL_8M \| \
	479	BATU_VS \| BATU_VP)
	480	#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE \| BATL_PP_10 \| \
	481	BATL_CACHEINHIBIT \| \
	482	BATL_GUARDEDSTORAGE)
	483	#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
	484
	485	/* Stack in dcache: cacheable, no memory coherence */
	486	#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR \| BATL_PP_10)
	487	#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR \| BATU_BL_128K \| \
	488	BATU_VS \| BATU_VP)
	489	#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
	490	#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
	491
bc8f8c26 IY	492	/*
	493	* Environment Configuration
	494	*/
	495
	496	#define CONFIG_ENV_OVERWRITE
	497
	498	#if defined(CONFIG_TSEC_ENET)
	499	#define CONFIG_HAS_ETH0
	500	#define CONFIG_HAS_ETH1
	501	#endif
	502
	503	#define CONFIG_BAUDRATE 115200
	504
	505	#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
	506
	507	#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
	508
	509	#define xstr(s) str(s)
	510	#define str(s) #s
	511
	512	#define CONFIG_EXTRA_ENV_SETTINGS \
	513	"netdev=eth0\0" \
	514	"consoledev=ttyS0\0" \
	515	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	516	"nfsroot=${serverip}:${rootpath}\0" \
	517	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	518	"addip=setenv bootargs ${bootargs} " \
	519	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	520	":${hostname}:${netdev}:off panic=1\0" \
	521	"addtty=setenv bootargs ${bootargs}" \
	522	" console=${consoledev},${baudrate}\0" \
	523	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
	524	"addmisc=setenv bootargs ${bootargs}\0" \
	525	"kernel_addr=FC0A0000\0" \
	526	"fdt_addr=FC2A0000\0" \
	527	"ramdisk_addr=FC2C0000\0" \
	528	"u-boot=mpc8308_p1m/u-boot.bin\0" \
	529	"kernel_addr_r=1000000\0" \
	530	"fdt_addr_r=C00000\0" \
	531	"hostname=mpc8308_p1m\0" \
	532	"bootfile=mpc8308_p1m/uImage\0" \
	533	"fdtfile=mpc8308_p1m/mpc8308_p1m.dtb\0" \
	534	"rootpath=/opt/eldk-4.2/ppc_6xx\0" \
	535	"flash_self=run ramargs addip addtty addmtd addmisc;" \
	536	"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
	537	"flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
	538	"bootm ${kernel_addr} - ${fdt_addr}\0" \
	539	"net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
	540	"tftp ${fdt_addr_r} ${fdtfile};" \
	541	"run nfsargs addip addtty addmtd addmisc;" \
	542	"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
	543	"bootcmd=run flash_self\0" \
	544	"load=tftp ${loadaddr} ${u-boot}\0" \
	545	"update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) \
	546	" +${filesize};era " xstr(CONFIG_SYS_MONITOR_BASE) \
	547	" +${filesize};cp.b ${fileaddr} " \
	548	xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
	549	"upd=run load update\0" \
	550
	551	#endif /* __CONFIG_H */