[people/ms/u-boot.git] / include / configs / mpc8308_p1m.h

/*
 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
 * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
 *
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_E300		1 /* E300 family */
#define CONFIG_MPC830x		1 /* MPC830x family */
#define CONFIG_MPC8308		1 /* MPC8308 CPU specific */

/*
 * On-board devices
 *
 * TSECs
 */
#define CONFIG_TSEC1
#define CONFIG_TSEC2

/*
 * System Clock Setup
 */
#define CONFIG_83XX_CLKIN	33333333 /* in Hz */
#define CONFIG_SYS_CLK_FREQ	CONFIG_83XX_CLKIN

/*
 * Hardware Reset Configuration Word
 * if CLKIN is 66.66MHz, then
 * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
 * We choose the A type silicon as default, so the core is 400Mhz.
 */
#define CONFIG_SYS_HRCW_LOW (\
	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
	HRCWL_DDR_TO_SCB_CLK_2X1 |\
	HRCWL_SVCOD_DIV_2 |\
	HRCWL_CSB_TO_CLKIN_4X1 |\
	HRCWL_CORE_TO_CSB_3X1)
/*
 * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
 * in 8308's HRCWH according to the manual, but original Freescale's
 * code has them and I've expirienced some problems using the board
 * with BDI3000 attached when I've tried to set these bits to zero
 * (UART doesn't work after the 'reset run' command).
 */
#define CONFIG_SYS_HRCW_HIGH (\
	HRCWH_PCI_HOST |\
	HRCWH_PCI1_ARBITER_ENABLE |\
	HRCWH_CORE_ENABLE |\
	HRCWH_FROM_0X00000100 |\
	HRCWH_BOOTSEQ_DISABLE |\
	HRCWH_SW_WATCHDOG_DISABLE |\
	HRCWH_ROM_LOC_LOCAL_16BIT |\
	HRCWH_RL_EXT_LEGACY |\
	HRCWH_TSEC1M_IN_MII |\
	HRCWH_TSEC2M_IN_MII |\
	HRCWH_BIG_ENDIAN)

/*
 * System IO Config
 */
#define CONFIG_SYS_SICRH (\
	SICRH_ESDHC_A_GPIO |\
	SICRH_ESDHC_B_GPIO |\
	SICRH_ESDHC_C_GTM |\
	SICRH_GPIO_A_TSEC2 |\
	SICRH_GPIO_B_TSEC2_TX_CLK |\
	SICRH_IEEE1588_A_GPIO |\
	SICRH_USB |\
	SICRH_GTM_GPIO |\
	SICRH_IEEE1588_B_GPIO |\
	SICRH_ETSEC2_CRS |\
	SICRH_GPIOSEL_1 |\
	SICRH_TMROBI_V3P3 |\
	SICRH_TSOBI1_V3P3 |\
	SICRH_TSOBI2_V3P3)	/* 0xf577d100 */
#define CONFIG_SYS_SICRL (\
	SICRL_SPI_PF0 |\
	SICRL_UART_PF0 |\
	SICRL_IRQ_PF0 |\
	SICRL_I2C2_PF0 |\
	SICRL_ETSEC1_TX_CLK)	/* 0x00000000 */

#define CONFIG_SYS_GPIO1_PRELIM
/* GPIO Default input/output settings */
#define CONFIG_SYS_GPIO1_DIR        0x7AAF8C00
/*
 * Default GPIO values:
 * LED#1 enabled; WLAN enabled; Both COM LED on (orange)
 */
#define CONFIG_SYS_GPIO1_DAT        0x08008C00

/*
 * IMMR new address
 */
#define CONFIG_SYS_IMMR		0xE0000000

/*
 * SERDES
 */
#define CONFIG_FSL_SERDES
#define CONFIG_FSL_SERDES1	0xe3000

/*
 * Arbiter Setup
 */
#define CONFIG_SYS_ACR_PIPE_DEP	3 /* Arbiter pipeline depth is 4 */
#define CONFIG_SYS_ACR_RPTCNT	3 /* Arbiter repeat count is 4 */
#define CONFIG_SYS_SPCR_TSECEP	3 /* eTSEC emergency priority is highest */

/*
 * DDR Setup
 */
#define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory */
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
#define CONFIG_SYS_DDRCDR_VALUE	(DDRCDR_EN \
				| DDRCDR_PZ_LOZ \
				| DDRCDR_NZ_LOZ \
				| DDRCDR_ODT \
				| DDRCDR_Q_DRN)
				/* 0x7b880001 */
/*
 * Manually set up DDR parameters
 * consist of two chips HY5PS12621BFP-C4 from HYNIX
 */

#define CONFIG_SYS_DDR_SIZE		128 /* MB */

#define CONFIG_SYS_DDR_CS0_BNDS	0x00000007
#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
					| CSCONFIG_ODT_RD_NEVER \
					| CSCONFIG_ODT_WR_ONLY_CURRENT \
					| CSCONFIG_ROW_BIT_13 \
					| CSCONFIG_COL_BIT_10)
					/* 0x80010102 */
#define CONFIG_SYS_DDR_TIMING_3	0x00000000
#define CONFIG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
				| (0 << TIMING_CFG0_WRT_SHIFT) \
				| (0 << TIMING_CFG0_RRT_SHIFT) \
				| (0 << TIMING_CFG0_WWT_SHIFT) \
				| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
				| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
				| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
				| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
				/* 0x00220802 */
#define CONFIG_SYS_DDR_TIMING_1	((2 << TIMING_CFG1_PRETOACT_SHIFT) \
				| (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
				| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
				| (5 << TIMING_CFG1_CASLAT_SHIFT) \
				| (6 << TIMING_CFG1_REFREC_SHIFT) \
				| (2 << TIMING_CFG1_WRREC_SHIFT) \
				| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
				| (2 << TIMING_CFG1_WRTORD_SHIFT))
				/* 0x27256222 */
#define CONFIG_SYS_DDR_TIMING_2	((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
				| (4 << TIMING_CFG2_CPO_SHIFT) \
				| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
				| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
				| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
				| (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
				/* 0x121048c5 */
#define CONFIG_SYS_DDR_INTERVAL	((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
				| (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
				/* 0x03600100 */
#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SREN \
				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
				| SDRAM_CFG_DBW_32)
				/* 0x43080000 */

#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000 /* 1 posted refresh */
#define CONFIG_SYS_DDR_MODE		((0x0448 << SDRAM_MODE_ESD_SHIFT) \
				| (0x0232 << SDRAM_MODE_SD_SHIFT))
				/* ODT 150ohm CL=3, AL=1 on SDRAM */
#define CONFIG_SYS_DDR_MODE2		0x00000000

/*
 * Memory test
 */
#define CONFIG_SYS_MEMTEST_START	0x00001000 /* memtest region */
#define CONFIG_SYS_MEMTEST_END		0x07f00000

/*
 * The reserved memory
 */
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE /* start of monitor */

#define CONFIG_SYS_MONITOR_LEN	(384 * 1024) /* Reserve 384 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN	(512 * 1024) /* Reserved for malloc */

/*
 * Initial RAM Base Address Setup
 */
#define CONFIG_SYS_INIT_RAM_LOCK	1
#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM */
#define CONFIG_SYS_GBL_DATA_OFFSET	\
	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)

/*
 * Local Bus Configuration & Clock Setup
 */
#define CONFIG_SYS_LCRR_DBYP		LCRR_DBYP
#define CONFIG_SYS_LCRR_CLKDIV		LCRR_CLKDIV_2
#define CONFIG_SYS_LBC_LBCR		0x00040000

/*
 * FLASH on the Local Bus
 */
#define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
#define CONFIG_FLASH_CFI_DRIVER		/* use the CFI driver */
#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT

#define CONFIG_SYS_FLASH_BASE		0xFC000000 /* FLASH base address */
#define CONFIG_SYS_FLASH_SIZE		64 /* FLASH size is 64M */
#define CONFIG_SYS_FLASH_PROTECTION	1 /* Use h/w Flash protection. */

/* Window base at flash base */
#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_64MB)

#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE \
				| BR_PS_16	/* 16 bit port */ \
				| BR_MS_GPCM	/* MSEL = GPCM */ \
				| BR_V)		/* valid */
#define CONFIG_SYS_OR0_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
				| OR_UPM_XAM \
				| OR_GPCM_CSNT \
				| OR_GPCM_ACS_DIV2 \
				| OR_GPCM_XACS \
				| OR_GPCM_SCY_4 \
				| OR_GPCM_TRLX_SET \
				| OR_GPCM_EHTR_SET)

#define CONFIG_SYS_MAX_FLASH_BANKS	1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	512

/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_ERASE_TOUT	(1000 * 1024)
/* Flash Write Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	(500 * 1024)

/*
 * SJA1000 CAN controller on Local Bus
 */
#define CONFIG_SYS_SJA1000_BASE	0xFBFF0000
#define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_SJA1000_BASE \
				| BR_PS_8	/* 8 bit port size */ \
				| BR_MS_GPCM	/* MSEL = GPCM */ \
				| BR_V)		/* valid */
#define CONFIG_SYS_OR1_PRELIM	(OR_AM_32KB \
				| OR_GPCM_SCY_5 \
				| OR_GPCM_EHTR_SET)
				/* 0xFFFF8052 */

#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_SJA1000_BASE
#define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_32KB)

/*
 * CPLD on Local Bus
 */
#define CONFIG_SYS_CPLD_BASE	0xFBFF8000
#define CONFIG_SYS_BR2_PRELIM	(CONFIG_SYS_CPLD_BASE \
				| BR_PS_8	/* 8 bit port */ \
				| BR_MS_GPCM	/* MSEL = GPCM */ \
				| BR_V)		/* valid */
#define CONFIG_SYS_OR2_PRELIM	(OR_AM_32KB \
				| OR_GPCM_SCY_4 \
				| OR_GPCM_EHTR_SET)
				/* 0xFFFF8042 */

#define CONFIG_SYS_LBLAWBAR2_PRELIM	CONFIG_SYS_CPLD_BASE
#define CONFIG_SYS_LBLAWAR2_PRELIM	(LBLAWAR_EN | LBLAWAR_32KB)

/*
 * Serial Port
 */
#define CONFIG_CONS_INDEX	1
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#define CONFIG_SYS_BAUDRATE_TABLE  \
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR + 0x4500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR + 0x4600)

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	400000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C2_SPEED	400000
#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100

/*
 * General PCI
 * Addresses are mapped 1-1.
 */
#define CONFIG_SYS_PCIE1_BASE		0xA0000000
#define CONFIG_SYS_PCIE1_MEM_BASE	0xA0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS	0xA0000000
#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000
#define CONFIG_SYS_PCIE1_CFG_BASE	0xB0000000
#define CONFIG_SYS_PCIE1_CFG_SIZE	0x01000000
#define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS	0xB1000000
#define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000

/* enable PCIE clock */
#define CONFIG_SYS_SCCR_PCIEXP1CM	1

#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCIE

#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1

/*
 * TSEC
 */
#define CONFIG_TSEC_ENET	/* TSEC ethernet support */
#define CONFIG_SYS_TSEC1_OFFSET	0x24000
#define CONFIG_SYS_TSEC1	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
#define CONFIG_SYS_TSEC2_OFFSET	0x25000
#define CONFIG_SYS_TSEC2	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)

/*
 * TSEC ethernet configuration
 */
#define CONFIG_MII		1 /* MII PHY management */
#define CONFIG_TSEC1_NAME	"eTSEC0"
#define CONFIG_TSEC2_NAME	"eTSEC1"
#define TSEC1_PHY_ADDR		1
#define TSEC2_PHY_ADDR		2
#define TSEC1_PHYIDX		0
#define TSEC2_PHYIDX		0
#define TSEC1_FLAGS		0
#define TSEC2_FLAGS		0

/* Options are: eTSEC[0-1] */
#define CONFIG_ETHPRIME		"eTSEC0"

/*
 * Environment
 */
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + \
				 CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K(one sector) for env */
#define CONFIG_ENV_SIZE		0x2000
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE

/*
 * Command line configuration.
 */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LOAD_ADDR		0x2000000 /* default load address */

#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size */

/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(256 << 20) /* Initial Memory map for Linux */

/*
 * Core HID Setup
 */
#define CONFIG_SYS_HID0_INIT	0x000000000
#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
				 HID0_ENABLE_INSTRUCTION_CACHE | \
				 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
#define CONFIG_SYS_HID2		HID2_HBE

/*
 * MMU Setup
 */

/* DDR: cache cacheable */
#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
					BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
					BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U

/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_IMMR | BATL_PP_RW | \
			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
					BATU_VP)
#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U

/* FLASH: icache cacheable, but dcache-inhibit and guarded */
#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
					BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
					BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT2L	(CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
					BATL_CACHEINHIBIT | \
					BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U

/* Stack in dcache: cacheable, no memory coherence */
#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
					BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U

/*
 * Environment Configuration
 */

#define CONFIG_ENV_OVERWRITE

#if defined(CONFIG_TSEC_ENET)
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#endif

#define CONFIG_LOADADDR	800000	/* default location for tftp and bootm */


#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"consoledev=ttyS0\0"						\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"addtty=setenv bootargs ${bootargs}"				\
		" console=${consoledev},${baudrate}\0"			\
	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
	"addmisc=setenv bootargs ${bootargs}\0"				\
	"kernel_addr=FC0A0000\0"					\
	"fdt_addr=FC2A0000\0"						\
	"ramdisk_addr=FC2C0000\0"					\
	"u-boot=mpc8308_p1m/u-boot.bin\0"				\
	"kernel_addr_r=1000000\0"					\
	"fdt_addr_r=C00000\0"						\
	"hostname=mpc8308_p1m\0"					\
	"bootfile=mpc8308_p1m/uImage\0"					\
	"fdtfile=mpc8308_p1m/mpc8308_p1m.dtb\0"				\
	"rootpath=/opt/eldk-4.2/ppc_6xx\0"				\
	"flash_self=run ramargs addip addtty addmtd addmisc;"		\
		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
	"flash_nfs=run nfsargs addip addtty addmtd addmisc;"		\
		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
		"tftp ${fdt_addr_r} ${fdtfile};"			\
		"run nfsargs addip addtty addmtd addmisc;"		\
		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
	"bootcmd=run flash_self\0"					\
	"load=tftp ${loadaddr} ${u-boot}\0"				\
	"update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)	\
		" +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
		" +${filesize};cp.b ${fileaddr} "			\
		__stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"	\
	"upd=run load update\0"						\

#endif	/* __CONFIG_H */
Commit	Line	Data
bc8f8c26 IY	1	/*
	2	* Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
	3	* Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
	4	*
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
bc8f8c26 IY	7	*/
	8
	9	#ifndef __CONFIG_H
	10	#define __CONFIG_H
	11
	12	/*
	13	* High Level Configuration Options
	14	*/
	15	#define CONFIG_E300 1 /* E300 family */
8afad91f	16	#define CONFIG_MPC830x 1 /* MPC830x family */
bc8f8c26	17	#define CONFIG_MPC8308 1 /* MPC8308 CPU specific */
bc8f8c26 IY	18
	19	/*
	20	* On-board devices
	21	*
	22	* TSECs
	23	*/
	24	#define CONFIG_TSEC1
	25	#define CONFIG_TSEC2
	26
	27	/*
	28	* System Clock Setup
	29	*/
	30	#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
	31	#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
	32
	33	/*
	34	* Hardware Reset Configuration Word
	35	* if CLKIN is 66.66MHz, then
	36	* CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
	37	* We choose the A type silicon as default, so the core is 400Mhz.
	38	*/
	39	#define CONFIG_SYS_HRCW_LOW (\
	40	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 \|\
	41	HRCWL_DDR_TO_SCB_CLK_2X1 \|\
	42	HRCWL_SVCOD_DIV_2 \|\
	43	HRCWL_CSB_TO_CLKIN_4X1 \|\
	44	HRCWL_CORE_TO_CSB_3X1)
	45	/*
	46	* There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
	47	* in 8308's HRCWH according to the manual, but original Freescale's
	48	* code has them and I've expirienced some problems using the board
	49	* with BDI3000 attached when I've tried to set these bits to zero
	50	* (UART doesn't work after the 'reset run' command).
	51	*/
	52	#define CONFIG_SYS_HRCW_HIGH (\
	53	HRCWH_PCI_HOST \|\
	54	HRCWH_PCI1_ARBITER_ENABLE \|\
	55	HRCWH_CORE_ENABLE \|\
	56	HRCWH_FROM_0X00000100 \|\
	57	HRCWH_BOOTSEQ_DISABLE \|\
	58	HRCWH_SW_WATCHDOG_DISABLE \|\
	59	HRCWH_ROM_LOC_LOCAL_16BIT \|\
	60	HRCWH_RL_EXT_LEGACY \|\
	61	HRCWH_TSEC1M_IN_MII \|\
	62	HRCWH_TSEC2M_IN_MII \|\
	63	HRCWH_BIG_ENDIAN)
	64
	65	/*
	66	* System IO Config
	67	*/
	68	#define CONFIG_SYS_SICRH (\
	69	SICRH_ESDHC_A_GPIO \|\
	70	SICRH_ESDHC_B_GPIO \|\
	71	SICRH_ESDHC_C_GTM \|\
	72	SICRH_GPIO_A_TSEC2 \|\
	73	SICRH_GPIO_B_TSEC2_TX_CLK \|\
	74	SICRH_IEEE1588_A_GPIO \|\
	75	SICRH_USB \|\
	76	SICRH_GTM_GPIO \|\
	77	SICRH_IEEE1588_B_GPIO \|\
	78	SICRH_ETSEC2_CRS \|\
	79	SICRH_GPIOSEL_1 \|\
	80	SICRH_TMROBI_V3P3 \|\
	81	SICRH_TSOBI1_V3P3 \|\
82	SICRH_TSOBI2_V3P3) /* 0xf577d100 */
83	#define CONFIG_SYS_SICRL (\
84	SICRL_SPI_PF0 \|\
85	SICRL_UART_PF0 \|\
86	SICRL_IRQ_PF0 \|\
87	SICRL_I2C2_PF0 \|\
88	SICRL_ETSEC1_TX_CLK) /* 0x00000000 */
89
90	#define CONFIG_SYS_GPIO1_PRELIM
91	/* GPIO Default input/output settings */
92	#define CONFIG_SYS_GPIO1_DIR 0x7AAF8C00
93	/*
94	* Default GPIO values:
95	* LED#1 enabled; WLAN enabled; Both COM LED on (orange)
96	*/
97	#define CONFIG_SYS_GPIO1_DAT 0x08008C00
98
99	/*
100	* IMMR new address
101	*/
102	#define CONFIG_SYS_IMMR 0xE0000000
103
104	/*
105	* SERDES
106	*/
107	#define CONFIG_FSL_SERDES
108	#define CONFIG_FSL_SERDES1 0xe3000
109
110	/*
111	* Arbiter Setup
112	*/
113	#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
114	#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
115	#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
116
117	/*
118	* DDR Setup
119	*/
120	#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
121	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
122	#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
123	#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
124	#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
125	\| DDRCDR_PZ_LOZ \
126	\| DDRCDR_NZ_LOZ \
127	\| DDRCDR_ODT \
128	\| DDRCDR_Q_DRN)
129	/* 0x7b880001 */
130	/*
131	* Manually set up DDR parameters
132	* consist of two chips HY5PS12621BFP-C4 from HYNIX
133	*/
134
135	#define CONFIG_SYS_DDR_SIZE 128 /* MB */
136
137	#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
138	#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
2fef4020 JH	139	\| CSCONFIG_ODT_RD_NEVER \
	140	\| CSCONFIG_ODT_WR_ONLY_CURRENT \
	141	\| CSCONFIG_ROW_BIT_13 \
	142	\| CSCONFIG_COL_BIT_10)
	143	/* 0x80010102 */
bc8f8c26 IY	144	#define CONFIG_SYS_DDR_TIMING_3 0x00000000
	145	#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
	146	\| (0 << TIMING_CFG0_WRT_SHIFT) \
	147	\| (0 << TIMING_CFG0_RRT_SHIFT) \
	148	\| (0 << TIMING_CFG0_WWT_SHIFT) \
	149	\| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
	150	\| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
	151	\| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
	152	\| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
	153	/* 0x00220802 */
	154	#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
	155	\| (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
	156	\| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
	157	\| (5 << TIMING_CFG1_CASLAT_SHIFT) \
	158	\| (6 << TIMING_CFG1_REFREC_SHIFT) \
	159	\| (2 << TIMING_CFG1_WRREC_SHIFT) \
	160	\| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
	161	\| (2 << TIMING_CFG1_WRTORD_SHIFT))
	162	/* 0x27256222 */
	163	#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
	164	\| (4 << TIMING_CFG2_CPO_SHIFT) \
	165	\| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
	166	\| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
	167	\| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
	168	\| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
	169	\| (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
	170	/* 0x121048c5 */
	171	#define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
	172	\| (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
	173	/* 0x03600100 */
	174	#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
	175	\| SDRAM_CFG_SDRAM_TYPE_DDR2 \
2fef4020	176	\| SDRAM_CFG_DBW_32)
bc8f8c26 IY	177	/* 0x43080000 */
	178
	179	#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
	180	#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
	181	\| (0x0232 << SDRAM_MODE_SD_SHIFT))
	182	/* ODT 150ohm CL=3, AL=1 on SDRAM */
	183	#define CONFIG_SYS_DDR_MODE2 0x00000000
	184
	185	/*
	186	* Memory test
	187	*/
	188	#define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */
	189	#define CONFIG_SYS_MEMTEST_END 0x07f00000
	190
	191	/*
	192	* The reserved memory
	193	*/
14d0a02a	194	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
bc8f8c26 IY	195
	196	#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
	197	#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
	198
	199	/*
	200	* Initial RAM Base Address Setup
	201	*/
	202	#define CONFIG_SYS_INIT_RAM_LOCK 1
	203	#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
80ae4df9	204	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
bc8f8c26	205	#define CONFIG_SYS_GBL_DATA_OFFSET \
25ddd1fb	206	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
bc8f8c26 IY	207
	208	/*
	209	* Local Bus Configuration & Clock Setup
	210	*/
	211	#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
	212	#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
	213	#define CONFIG_SYS_LBC_LBCR 0x00040000
	214
	215	/*
	216	* FLASH on the Local Bus
	217	*/
	218	#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
	219	#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
	220	#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
	221
	222	#define CONFIG_SYS_FLASH_BASE 0xFC000000 /* FLASH base address */
	223	#define CONFIG_SYS_FLASH_SIZE 64 /* FLASH size is 64M */
	224	#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
	225
	226	/* Window base at flash base */
	227	#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
	228	#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN \| LBLAWAR_64MB)
	229
7d6a0982 JH	230	#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
	231	\| BR_PS_16 /* 16 bit port */ \
	232	\| BR_MS_GPCM /* MSEL = GPCM */ \
	233	\| BR_V) /* valid */
	234	#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
bc8f8c26 IY	235	\| OR_UPM_XAM \
	236	\| OR_GPCM_CSNT \
	237	\| OR_GPCM_ACS_DIV2 \
	238	\| OR_GPCM_XACS \
	239	\| OR_GPCM_SCY_4 \
7d6a0982 JH	240	\| OR_GPCM_TRLX_SET \
7d6a0982 JH	241	\| OR_GPCM_EHTR_SET)
bc8f8c26 IY	242
	243	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
	244	#define CONFIG_SYS_MAX_FLASH_SECT 512
	245
	246	/* Flash Erase Timeout (ms) */
	247	#define CONFIG_SYS_FLASH_ERASE_TOUT (1000 * 1024)
	248	/* Flash Write Timeout (ms) */
	249	#define CONFIG_SYS_FLASH_WRITE_TOUT (500 * 1024)
	250
	251	/*
	252	* SJA1000 CAN controller on Local Bus
	253	*/
80ae4df9 JH	254	#define CONFIG_SYS_SJA1000_BASE 0xFBFF0000
80ae4df9 JH	255	#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_SJA1000_BASE \
7d6a0982 JH	256	\| BR_PS_8 /* 8 bit port size */ \
	257	\| BR_MS_GPCM /* MSEL = GPCM */ \
	258	\| BR_V) /* valid */
	259	#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
bc8f8c26	260	\| OR_GPCM_SCY_5 \
7d6a0982	261	\| OR_GPCM_EHTR_SET)
bc8f8c26 IY	262	/* 0xFFFF8052 */
	263
	264	#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_SJA1000_BASE
	265	#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN \| LBLAWAR_32KB)
	266
	267	/*
	268	* CPLD on Local Bus
	269	*/
80ae4df9 JH	270	#define CONFIG_SYS_CPLD_BASE 0xFBFF8000
80ae4df9 JH	271	#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_CPLD_BASE \
7d6a0982 JH	272	\| BR_PS_8 /* 8 bit port */ \
	273	\| BR_MS_GPCM /* MSEL = GPCM */ \
	274	\| BR_V) /* valid */
	275	#define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB \
bc8f8c26	276	\| OR_GPCM_SCY_4 \
7d6a0982	277	\| OR_GPCM_EHTR_SET)
bc8f8c26 IY	278	/* 0xFFFF8042 */
	279
	280	#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_CPLD_BASE
	281	#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN \| LBLAWAR_32KB)
	282
	283	/*
	284	* Serial Port
	285	*/
	286	#define CONFIG_CONS_INDEX 1
	287	#undef CONFIG_SERIAL_SOFTWARE_FIFO
bc8f8c26 IY	288	#define CONFIG_SYS_NS16550_SERIAL
	289	#define CONFIG_SYS_NS16550_REG_SIZE 1
	290	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
	291
	292	#define CONFIG_SYS_BAUDRATE_TABLE \
	293	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
	294
	295	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
	296	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
	297
bc8f8c26	298	/* I2C */
00f792e0 HS	299	#define CONFIG_SYS_I2C
	300	#define CONFIG_SYS_I2C_FSL
	301	#define CONFIG_SYS_FSL_I2C_SPEED 400000
	302	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	303	#define CONFIG_SYS_FSL_I2C2_SPEED 400000
	304	#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
	305	#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
	306	#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
bc8f8c26 IY	307
	308	/*
	309	* General PCI
	310	* Addresses are mapped 1-1.
	311	*/
	312	#define CONFIG_SYS_PCIE1_BASE 0xA0000000
	313	#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
	314	#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
	315	#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
	316	#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
	317	#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
	318	#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
	319	#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
	320	#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
	321
	322	/* enable PCIE clock */
	323	#define CONFIG_SYS_SCCR_PCIEXP1CM 1
	324
842033e6	325	#define CONFIG_PCI_INDIRECT_BRIDGE
bc8f8c26 IY	326	#define CONFIG_PCIE
bc8f8c26 IY	327
bc8f8c26 IY	328	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
	329	#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
	330
	331	/*
	332	* TSEC
	333	*/
bc8f8c26 IY	334	#define CONFIG_TSEC_ENET /* TSEC ethernet support */
	335	#define CONFIG_SYS_TSEC1_OFFSET 0x24000
	336	#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
	337	#define CONFIG_SYS_TSEC2_OFFSET 0x25000
	338	#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
	339
	340	/*
	341	* TSEC ethernet configuration
	342	*/
	343	#define CONFIG_MII 1 /* MII PHY management */
	344	#define CONFIG_TSEC1_NAME "eTSEC0"
	345	#define CONFIG_TSEC2_NAME "eTSEC1"
	346	#define TSEC1_PHY_ADDR 1
	347	#define TSEC2_PHY_ADDR 2
	348	#define TSEC1_PHYIDX 0
	349	#define TSEC2_PHYIDX 0
	350	#define TSEC1_FLAGS 0
	351	#define TSEC2_FLAGS 0
	352
	353	/* Options are: eTSEC[0-1] */
	354	#define CONFIG_ETHPRIME "eTSEC0"
	355
	356	/*
	357	* Environment
	358	*/
bc8f8c26 IY	359	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
	360	CONFIG_SYS_MONITOR_LEN)
	361	#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
	362	#define CONFIG_ENV_SIZE 0x2000
	363	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
	364	#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
	365
	366	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	367	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
	368
	369	/*
	370	* BOOTP options
	371	*/
	372	#define CONFIG_BOOTP_BOOTFILESIZE
bc8f8c26 IY	373
	374	/*
	375	* Command line configuration.
	376	*/
bc8f8c26	377
bc8f8c26 IY	378	/*
	379	* Miscellaneous configurable options
	380	*/
bc8f8c26	381	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
bc8f8c26 IY	382
	383	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
	384
bc8f8c26 IY	385	/* Boot Argument Buffer Size */
bc8f8c26 IY	386	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
bc8f8c26 IY	387
	388	/*
	389	* For booting Linux, the board info and command line data
	390	* have to be in the first 8 MB of memory, since this is
	391	* the maximum mapped by the Linux kernel during initialization.
	392	*/
9eda770b	393	#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
bc8f8c26 IY	394
	395	/*
	396	* Core HID Setup
	397	*/
	398	#define CONFIG_SYS_HID0_INIT 0x000000000
	399	#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \| \
	400	HID0_ENABLE_INSTRUCTION_CACHE \| \
	401	HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
	402	#define CONFIG_SYS_HID2 HID2_HBE
	403
	404	/*
	405	* MMU Setup
	406	*/
	407
	408	/* DDR: cache cacheable */
72cd4087	409	#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \| BATL_PP_RW \| \
bc8f8c26 IY	410	BATL_MEMCOHERENCE)
	411	#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \| BATU_BL_128M \| \
	412	BATU_VS \| BATU_VP)
	413	#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
	414	#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
	415
	416	/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
72cd4087	417	#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \| BATL_PP_RW \| \
bc8f8c26 IY	418	BATL_CACHEINHIBIT \| BATL_GUARDEDSTORAGE)
	419	#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \| BATU_BL_8M \| BATU_VS \| \
	420	BATU_VP)
	421	#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
	422	#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
	423
	424	/* FLASH: icache cacheable, but dcache-inhibit and guarded */
72cd4087	425	#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE \| BATL_PP_RW \| \
bc8f8c26 IY	426	BATL_MEMCOHERENCE)
	427	#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE \| BATU_BL_8M \| \
	428	BATU_VS \| BATU_VP)
72cd4087	429	#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE \| BATL_PP_RW \| \
bc8f8c26 IY	430	BATL_CACHEINHIBIT \| \
	431	BATL_GUARDEDSTORAGE)
	432	#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
	433
	434	/* Stack in dcache: cacheable, no memory coherence */
72cd4087	435	#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR \| BATL_PP_RW)
bc8f8c26 IY	436	#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR \| BATU_BL_128K \| \
	437	BATU_VS \| BATU_VP)
	438	#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
	439	#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
	440
bc8f8c26 IY	441	/*
	442	* Environment Configuration
	443	*/
	444
	445	#define CONFIG_ENV_OVERWRITE
	446
	447	#if defined(CONFIG_TSEC_ENET)
	448	#define CONFIG_HAS_ETH0
	449	#define CONFIG_HAS_ETH1
	450	#endif
	451
bc8f8c26 IY	452	#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
bc8f8c26 IY	453
bc8f8c26	454
bc8f8c26 IY	455	#define CONFIG_EXTRA_ENV_SETTINGS \
	456	"netdev=eth0\0" \
	457	"consoledev=ttyS0\0" \
	458	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	459	"nfsroot=${serverip}:${rootpath}\0" \
	460	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	461	"addip=setenv bootargs ${bootargs} " \
	462	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	463	":${hostname}:${netdev}:off panic=1\0" \
	464	"addtty=setenv bootargs ${bootargs}" \
	465	" console=${consoledev},${baudrate}\0" \
	466	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
	467	"addmisc=setenv bootargs ${bootargs}\0" \
	468	"kernel_addr=FC0A0000\0" \
	469	"fdt_addr=FC2A0000\0" \
	470	"ramdisk_addr=FC2C0000\0" \
	471	"u-boot=mpc8308_p1m/u-boot.bin\0" \
	472	"kernel_addr_r=1000000\0" \
	473	"fdt_addr_r=C00000\0" \
	474	"hostname=mpc8308_p1m\0" \
	475	"bootfile=mpc8308_p1m/uImage\0" \
	476	"fdtfile=mpc8308_p1m/mpc8308_p1m.dtb\0" \
	477	"rootpath=/opt/eldk-4.2/ppc_6xx\0" \
	478	"flash_self=run ramargs addip addtty addmtd addmisc;" \
	479	"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
	480	"flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
	481	"bootm ${kernel_addr} - ${fdt_addr}\0" \
	482	"net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
	483	"tftp ${fdt_addr_r} ${fdtfile};" \
	484	"run nfsargs addip addtty addmtd addmisc;" \
	485	"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
	486	"bootcmd=run flash_self\0" \
	487	"load=tftp ${loadaddr} ${u-boot}\0" \
93ea89f0 MV	488	"update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
93ea89f0 MV	489	" +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
bc8f8c26	490	" +${filesize};cp.b ${fileaddr} " \
93ea89f0	491	__stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
bc8f8c26 IY	492	"upd=run load update\0" \
	493
	494	#endif /* __CONFIG_H */