[people/ms/u-boot.git] / include / configs / mpr2.h

/*
 * Configuation settings for MPR2
 *
 * Copyright (C) 2008
 * Mark Jonas <mark.jonas@de.bosch.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __MPR2_H
#define __MPR2_H

/* Supported commands */

/* Default environment variables */
#define CONFIG_BAUDRATE		115200
#define CONFIG_BOOTARGS		"console=ttySC0,115200"
#define CONFIG_BOOTFILE		"/boot/zImage"
#define CONFIG_LOADADDR		0x8E000000

/* CPU and platform */
#define CONFIG_CPU_SH7720	1
#define CONFIG_MPR2		1

/* U-Boot internals */
#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
#define CONFIG_SYS_CBSIZE		256	/* Buffer size for input from the Console */
#define CONFIG_SYS_PBSIZE		256	/* Buffer size for Console output */
#define CONFIG_SYS_MAXARGS		16	/* max args accepted for monitor commands */
#define CONFIG_SYS_BARGSIZE		512	/* Buffer size for Boot Arguments passed to kernel */
#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }	/* List of legal baudrate settings for this board */
#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN		(128 * 1024)
#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)

#define CONFIG_SYS_TEXT_BASE	0x8FFC0000

/* Memory */
#define CONFIG_SYS_SDRAM_BASE		0x8C000000
#define CONFIG_SYS_SDRAM_SIZE		(64 * 1024 * 1024)
#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))

/* Flash */
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_BASE		0xA0000000
#define CONFIG_SYS_MAX_FLASH_SECT	256
#define CONFIG_SYS_MAX_FLASH_BANKS	1
#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE	(128 * 1024)
#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_SYS_FLASH_ERASE_TOUT	120000
#define CONFIG_SYS_FLASH_WRITE_TOUT	500

/* Clocks */
#define CONFIG_SYS_CLK_FREQ	24000000
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_TMU_CLK_DIV		4	/* 4 (default), 16, 64, 256 or 1024 */

/* UART */
#define CONFIG_SCIF_CONSOLE	1
#define CONFIG_CONS_SCIF0	1

#endif	/* __MPR2_H */
Commit	Line	Data
3313e0e2 MJ	1	/*
	2	* Configuation settings for MPR2
	3	*
	4	* Copyright (C) 2008
	5	* Mark Jonas <mark.jonas@de.bosch.com>
	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
3313e0e2 MJ	8	*/
	9
	10	#ifndef __MPR2_H
	11	#define __MPR2_H
	12
	13	/* Supported commands */
3313e0e2 MJ	14
	15	/* Default environment variables */
	16	#define CONFIG_BAUDRATE 115200
	17	#define CONFIG_BOOTARGS "console=ttySC0,115200"
b3f44c21	18	#define CONFIG_BOOTFILE "/boot/zImage"
3313e0e2	19	#define CONFIG_LOADADDR 0x8E000000
3313e0e2 MJ	20
3313e0e2 MJ	21	/* CPU and platform */
3313e0e2 MJ	22	#define CONFIG_CPU_SH7720 1
	23	#define CONFIG_MPR2 1
	24
	25	/* U-Boot internals */
6d0f6bcf	26	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	27	#define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */
	28	#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
	29	#define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */
	30	#define CONFIG_SYS_BARGSIZE 512 /* Buffer size for Boot Arguments passed to kernel */
	31	#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */
	32	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
	33	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	34	#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
	35	#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
3313e0e2	36
b8256962 NI	37	#define CONFIG_SYS_TEXT_BASE 0x8FFC0000
b8256962 NI	38
3313e0e2	39	/* Memory */
6d0f6bcf JCPV	40	#define CONFIG_SYS_SDRAM_BASE 0x8C000000
	41	#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
	42	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
	43	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
3313e0e2 MJ	44
3313e0e2 MJ	45	/* Flash */
6d0f6bcf	46	#define CONFIG_SYS_FLASH_CFI
00b1883a	47	#define CONFIG_FLASH_CFI_DRIVER
6d0f6bcf JCPV	48	#define CONFIG_SYS_FLASH_EMPTY_INFO
	49	#define CONFIG_SYS_FLASH_BASE 0xA0000000
	50	#define CONFIG_SYS_MAX_FLASH_SECT 256
	51	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	52	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
5a1aceb0	53	#define CONFIG_ENV_IS_IN_FLASH
0e8d1586 JCPV	54	#define CONFIG_ENV_SECT_SIZE (128 * 1024)
0e8d1586 JCPV	55	#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
6d0f6bcf JCPV	56	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
	57	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
	58	#define CONFIG_SYS_FLASH_WRITE_TOUT 500
3313e0e2 MJ	59
	60	/* Clocks */
	61	#define CONFIG_SYS_CLK_FREQ 24000000
684a501e NI	62	#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
684a501e NI	63	#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
be45c632	64	#define CONFIG_SYS_TMU_CLK_DIV 4 /* 4 (default), 16, 64, 256 or 1024 */
3313e0e2 MJ	65
3313e0e2 MJ	66	/* UART */
6c58a030	67	#define CONFIG_SCIF_CONSOLE 1
3313e0e2 MJ	68	#define CONFIG_CONS_SCIF0 1
	69
	70	#endif /* __MPR2_H */