[people/ms/u-boot.git] / include / configs / ms7720se.h

/*
 * Configuation settings for the Hitachi Solution Engine 7720
 *
 * Copyright (C) 2007 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __MS7720SE_H
#define __MS7720SE_H

#define CONFIG_CPU_SH7720	1

#define CONFIG_BOOTFILE		"/boot/zImage"
#define CONFIG_LOADADDR		0x8E000000

#define CONFIG_DISPLAY_BOARDINFO
#undef  CONFIG_SHOW_BOOT_PROGRESS

/* MEMORY */
#define MS7720SE_SDRAM_BASE		0x8C000000
#define MS7720SE_FLASH_BASE_1		0xA0000000
#define MS7720SE_FLASH_BANK_SIZE	(8 * 1024 * 1024)

#define CONFIG_SYS_PBSIZE	256	/* Buffer size for Console output */
/* List of legal baudrate settings for this board */
#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }

/* SCIF */
#define CONFIG_CONS_SCIF0	1

#define CONFIG_SYS_MEMTEST_START	MS7720SE_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))

#define CONFIG_SYS_SDRAM_BASE		MS7720SE_SDRAM_BASE
#define CONFIG_SYS_SDRAM_SIZE		(64 * 1024 * 1024)

#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
#define CONFIG_SYS_MONITOR_BASE	MS7720SE_FLASH_BASE_1
#define CONFIG_SYS_MONITOR_LEN		(128 * 1024)
#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)
#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)

/* FLASH */
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
#undef  CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_SYS_FLASH_EMPTY_INFO	/* print 'E' for empty sector on flinfo */

#define CONFIG_SYS_FLASH_BASE		MS7720SE_FLASH_BASE_1

#define CONFIG_SYS_MAX_FLASH_SECT	150
#define CONFIG_SYS_MAX_FLASH_BANKS	1
#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }

#define CONFIG_ENV_SECT_SIZE	(64 * 1024)
#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_SYS_FLASH_ERASE_TOUT	120000
#define CONFIG_SYS_FLASH_WRITE_TOUT	500

/* Board Clock */
#define CONFIG_SYS_CLK_FREQ	33333333
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_TMU_CLK_DIV		4	/* 4 (default), 16, 64, 256 or 1024 */

/* PCMCIA */
#define CONFIG_IDE_PCMCIA	1
#define CONFIG_MARUBUN_PCCARD	1
#define CONFIG_PCMCIA_SLOT_A	1
#define CONFIG_SYS_IDE_MAXDEVICE	1
#define CONFIG_SYS_MARUBUN_MRSHPC	0xb83fffe0
#define CONFIG_SYS_MARUBUN_MW1		0xb8400000
#define CONFIG_SYS_MARUBUN_MW2		0xb8500000
#define CONFIG_SYS_MARUBUN_IO		0xb8600000

#define CONFIG_SYS_PIO_MODE		1
#define CONFIG_SYS_IDE_MAXBUS		1
#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_MARUBUN_IO	/* base address */
#define CONFIG_SYS_ATA_IDE0_OFFSET	0x01F0		/* ide0 offste */
#define CONFIG_SYS_ATA_DATA_OFFSET	0		/* data reg offset */
#define CONFIG_SYS_ATA_REG_OFFSET	0		/* reg offset */
#define CONFIG_SYS_ATA_ALT_OFFSET	0x200		/* alternate register offset */
#define CONFIG_IDE_SWAP_IO

#endif	/* __MS7720SE_H */
Commit	Line	Data
b2b5e2bb YS	1	/*
	2	* Configuation settings for the Hitachi Solution Engine 7720
	3	*
	4	* Copyright (C) 2007 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
b2b5e2bb YS	7	*/
	8
	9	#ifndef __MS7720SE_H
	10	#define __MS7720SE_H
	11
b2b5e2bb	12	#define CONFIG_CPU_SH7720 1
b2b5e2bb	13
b3f44c21	14	#define CONFIG_BOOTFILE "/boot/zImage"
b2b5e2bb YS	15	#define CONFIG_LOADADDR 0x8E000000
b2b5e2bb YS	16
18a40e84	17	#define CONFIG_DISPLAY_BOARDINFO
b2b5e2bb YS	18	#undef CONFIG_SHOW_BOOT_PROGRESS
	19
	20	/* MEMORY */
	21	#define MS7720SE_SDRAM_BASE 0x8C000000
	22	#define MS7720SE_FLASH_BASE_1 0xA0000000
	23	#define MS7720SE_FLASH_BANK_SIZE (8 * 1024 * 1024)
	24
6d0f6bcf	25	#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
b2b5e2bb	26	/* List of legal baudrate settings for this board */
6d0f6bcf	27	#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
b2b5e2bb YS	28
b2b5e2bb YS	29	/* SCIF */
b2b5e2bb YS	30	#define CONFIG_CONS_SCIF0 1
b2b5e2bb YS	31
6d0f6bcf JCPV	32	#define CONFIG_SYS_MEMTEST_START MS7720SE_SDRAM_BASE
6d0f6bcf JCPV	33	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
b2b5e2bb	34
6d0f6bcf JCPV	35	#define CONFIG_SYS_SDRAM_BASE MS7720SE_SDRAM_BASE
6d0f6bcf JCPV	36	#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
b2b5e2bb	37
6d0f6bcf JCPV	38	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
	39	#define CONFIG_SYS_MONITOR_BASE MS7720SE_FLASH_BASE_1
	40	#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
	41	#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
6d0f6bcf	42	#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
b2b5e2bb	43
b2b5e2bb	44	/* FLASH */
6d0f6bcf	45	#define CONFIG_SYS_FLASH_CFI
00b1883a	46	#define CONFIG_FLASH_CFI_DRIVER
6d0f6bcf JCPV	47	#undef CONFIG_SYS_FLASH_QUIET_TEST
6d0f6bcf JCPV	48	#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
b2b5e2bb	49
6d0f6bcf	50	#define CONFIG_SYS_FLASH_BASE MS7720SE_FLASH_BASE_1
b2b5e2bb	51
6d0f6bcf JCPV	52	#define CONFIG_SYS_MAX_FLASH_SECT 150
	53	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	54	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
b2b5e2bb	55
0e8d1586 JCPV	56	#define CONFIG_ENV_SECT_SIZE (64 * 1024)
0e8d1586 JCPV	57	#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
6d0f6bcf JCPV	58	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
	59	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
	60	#define CONFIG_SYS_FLASH_WRITE_TOUT 500
b2b5e2bb YS	61
	62	/* Board Clock */
	63	#define CONFIG_SYS_CLK_FREQ 33333333
684a501e NI	64	#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
684a501e NI	65	#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
be45c632	66	#define CONFIG_SYS_TMU_CLK_DIV 4 /* 4 (default), 16, 64, 256 or 1024 */
b2b5e2bb YS	67
	68	/* PCMCIA */
	69	#define CONFIG_IDE_PCMCIA 1
	70	#define CONFIG_MARUBUN_PCCARD 1
	71	#define CONFIG_PCMCIA_SLOT_A 1
6d0f6bcf JCPV	72	#define CONFIG_SYS_IDE_MAXDEVICE 1
	73	#define CONFIG_SYS_MARUBUN_MRSHPC 0xb83fffe0
	74	#define CONFIG_SYS_MARUBUN_MW1 0xb8400000
	75	#define CONFIG_SYS_MARUBUN_MW2 0xb8500000
	76	#define CONFIG_SYS_MARUBUN_IO 0xb8600000
	77
	78	#define CONFIG_SYS_PIO_MODE 1
	79	#define CONFIG_SYS_IDE_MAXBUS 1
6d0f6bcf JCPV	80	#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_MARUBUN_IO /* base address */
	81	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */
	82	#define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */
	83	#define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */
	84	#define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */
f2a37fcd	85	#define CONFIG_IDE_SWAP_IO
b2b5e2bb YS	86
b2b5e2bb YS	87	#endif /* __MS7720SE_H */