[people/ms/u-boot.git] / include / configs / ms7720se.h

/*
 * Configuation settings for the Hitachi Solution Engine 7720
 *
 * Copyright (C) 2007 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __MS7720SE_H
#define __MS7720SE_H

#define CONFIG_CPU_SH7720	1
#define CONFIG_MS7720SE		1

#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_PCMCIA
#define CONFIG_CMD_IDE

#define CONFIG_BAUDRATE		115200
#define CONFIG_BOOTARGS		"console=ttySC0,115200"
#define CONFIG_BOOTFILE		"/boot/zImage"
#define CONFIG_LOADADDR		0x8E000000

#undef  CONFIG_SHOW_BOOT_PROGRESS

/* MEMORY */
#define MS7720SE_SDRAM_BASE		0x8C000000
#define MS7720SE_FLASH_BASE_1		0xA0000000
#define MS7720SE_FLASH_BANK_SIZE	(8 * 1024 * 1024)

#define CONFIG_SYS_TEXT_BASE	0x8FFC0000
#define CONFIG_SYS_LONGHELP		/* undef to save memory	*/
#define CONFIG_SYS_CBSIZE	256	/* Buffer size for input from the Console */
#define CONFIG_SYS_PBSIZE	256	/* Buffer size for Console output */
#define CONFIG_SYS_MAXARGS	16	/* max args accepted for monitor commands */
/* Buffer size for Boot Arguments passed to kernel */
#define CONFIG_SYS_BARGSIZE	512
/* List of legal baudrate settings for this board */
#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }

/* SCIF */
#define CONFIG_SCIF_CONSOLE	1
#define CONFIG_CONS_SCIF0	1

#define CONFIG_SYS_MEMTEST_START	MS7720SE_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))

#define CONFIG_SYS_SDRAM_BASE		MS7720SE_SDRAM_BASE
#define CONFIG_SYS_SDRAM_SIZE		(64 * 1024 * 1024)

#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
#define CONFIG_SYS_MONITOR_BASE	MS7720SE_FLASH_BASE_1
#define CONFIG_SYS_MONITOR_LEN		(128 * 1024)
#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)
#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)

/* FLASH */
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
#undef  CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_SYS_FLASH_EMPTY_INFO	/* print 'E' for empty sector on flinfo */

#define CONFIG_SYS_FLASH_BASE		MS7720SE_FLASH_BASE_1

#define CONFIG_SYS_MAX_FLASH_SECT	150
#define CONFIG_SYS_MAX_FLASH_BANKS	1
#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }

#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE	(64 * 1024)
#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_SYS_FLASH_ERASE_TOUT	120000
#define CONFIG_SYS_FLASH_WRITE_TOUT	500

/* Board Clock */
#define CONFIG_SYS_CLK_FREQ	33333333
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_TMU_CLK_DIV		4	/* 4 (default), 16, 64, 256 or 1024 */

/* PCMCIA */
#define CONFIG_IDE_PCMCIA	1
#define CONFIG_MARUBUN_PCCARD	1
#define CONFIG_PCMCIA_SLOT_A	1
#define CONFIG_SYS_IDE_MAXDEVICE	1
#define CONFIG_SYS_MARUBUN_MRSHPC	0xb83fffe0
#define CONFIG_SYS_MARUBUN_MW1		0xb8400000
#define CONFIG_SYS_MARUBUN_MW2		0xb8500000
#define CONFIG_SYS_MARUBUN_IO		0xb8600000

#define CONFIG_SYS_PIO_MODE		1
#define CONFIG_SYS_IDE_MAXBUS		1
#define CONFIG_DOS_PARTITION	1
#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_MARUBUN_IO	/* base address */
#define CONFIG_SYS_ATA_IDE0_OFFSET	0x01F0		/* ide0 offste */
#define CONFIG_SYS_ATA_DATA_OFFSET	0		/* data reg offset */
#define CONFIG_SYS_ATA_REG_OFFSET	0		/* reg offset */
#define CONFIG_SYS_ATA_ALT_OFFSET	0x200		/* alternate register offset */
#define CONFIG_IDE_SWAP_IO

#endif	/* __MS7720SE_H */
Commit	Line	Data
b2b5e2bb YS	1	/*
	2	* Configuation settings for the Hitachi Solution Engine 7720
	3	*
	4	* Copyright (C) 2007 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
b2b5e2bb YS	7	*/
	8
	9	#ifndef __MS7720SE_H
	10	#define __MS7720SE_H
	11
b2b5e2bb YS	12	#define CONFIG_CPU_SH7720 1
	13	#define CONFIG_MS7720SE 1
	14
b2b5e2bb	15	#define CONFIG_CMD_SDRAM
b2b5e2bb YS	16	#define CONFIG_CMD_PCMCIA
b2b5e2bb YS	17	#define CONFIG_CMD_IDE
b2b5e2bb	18
b2b5e2bb YS	19	#define CONFIG_BAUDRATE 115200
b2b5e2bb YS	20	#define CONFIG_BOOTARGS "console=ttySC0,115200"
b3f44c21	21	#define CONFIG_BOOTFILE "/boot/zImage"
b2b5e2bb YS	22	#define CONFIG_LOADADDR 0x8E000000
b2b5e2bb YS	23
b2b5e2bb YS	24	#undef CONFIG_SHOW_BOOT_PROGRESS
	25
	26	/* MEMORY */
	27	#define MS7720SE_SDRAM_BASE 0x8C000000
	28	#define MS7720SE_FLASH_BASE_1 0xA0000000
	29	#define MS7720SE_FLASH_BANK_SIZE (8 * 1024 * 1024)
	30
46198754	31	#define CONFIG_SYS_TEXT_BASE 0x8FFC0000
6d0f6bcf	32	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	33	#define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */
	34	#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
	35	#define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */
b2b5e2bb	36	/* Buffer size for Boot Arguments passed to kernel */
6d0f6bcf	37	#define CONFIG_SYS_BARGSIZE 512
b2b5e2bb	38	/* List of legal baudrate settings for this board */
6d0f6bcf	39	#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
b2b5e2bb YS	40
b2b5e2bb YS	41	/* SCIF */
6c58a030	42	#define CONFIG_SCIF_CONSOLE 1
b2b5e2bb YS	43	#define CONFIG_CONS_SCIF0 1
b2b5e2bb YS	44
6d0f6bcf JCPV	45	#define CONFIG_SYS_MEMTEST_START MS7720SE_SDRAM_BASE
6d0f6bcf JCPV	46	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
b2b5e2bb	47
6d0f6bcf JCPV	48	#define CONFIG_SYS_SDRAM_BASE MS7720SE_SDRAM_BASE
6d0f6bcf JCPV	49	#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
b2b5e2bb	50
6d0f6bcf JCPV	51	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
	52	#define CONFIG_SYS_MONITOR_BASE MS7720SE_FLASH_BASE_1
	53	#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
	54	#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
6d0f6bcf	55	#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
b2b5e2bb	56
b2b5e2bb	57	/* FLASH */
6d0f6bcf	58	#define CONFIG_SYS_FLASH_CFI
00b1883a	59	#define CONFIG_FLASH_CFI_DRIVER
6d0f6bcf JCPV	60	#undef CONFIG_SYS_FLASH_QUIET_TEST
6d0f6bcf JCPV	61	#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
b2b5e2bb	62
6d0f6bcf	63	#define CONFIG_SYS_FLASH_BASE MS7720SE_FLASH_BASE_1
b2b5e2bb	64
6d0f6bcf JCPV	65	#define CONFIG_SYS_MAX_FLASH_SECT 150
	66	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	67	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
b2b5e2bb	68
5a1aceb0	69	#define CONFIG_ENV_IS_IN_FLASH
0e8d1586 JCPV	70	#define CONFIG_ENV_SECT_SIZE (64 * 1024)
0e8d1586 JCPV	71	#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
6d0f6bcf JCPV	72	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
	73	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
	74	#define CONFIG_SYS_FLASH_WRITE_TOUT 500
b2b5e2bb YS	75
	76	/* Board Clock */
	77	#define CONFIG_SYS_CLK_FREQ 33333333
684a501e NI	78	#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
684a501e NI	79	#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
be45c632	80	#define CONFIG_SYS_TMU_CLK_DIV 4 /* 4 (default), 16, 64, 256 or 1024 */
b2b5e2bb YS	81
	82	/* PCMCIA */
	83	#define CONFIG_IDE_PCMCIA 1
	84	#define CONFIG_MARUBUN_PCCARD 1
	85	#define CONFIG_PCMCIA_SLOT_A 1
6d0f6bcf JCPV	86	#define CONFIG_SYS_IDE_MAXDEVICE 1
	87	#define CONFIG_SYS_MARUBUN_MRSHPC 0xb83fffe0
	88	#define CONFIG_SYS_MARUBUN_MW1 0xb8400000
	89	#define CONFIG_SYS_MARUBUN_MW2 0xb8500000
	90	#define CONFIG_SYS_MARUBUN_IO 0xb8600000
	91
	92	#define CONFIG_SYS_PIO_MODE 1
	93	#define CONFIG_SYS_IDE_MAXBUS 1
b2b5e2bb	94	#define CONFIG_DOS_PARTITION 1
6d0f6bcf JCPV	95	#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_MARUBUN_IO /* base address */
	96	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */
	97	#define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */
	98	#define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */
	99	#define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */
f2a37fcd	100	#define CONFIG_IDE_SWAP_IO
b2b5e2bb YS	101
b2b5e2bb YS	102	#endif /* __MS7720SE_H */