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6c0bbdcc NI |
1 | /* |
2 | * Configuation settings for the Hitachi Solution Engine 7722 | |
3 | * | |
4 | * Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> | |
5 | * | |
1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
6c0bbdcc NI |
7 | */ |
8 | ||
9 | #ifndef __MS7722SE_H | |
10 | #define __MS7722SE_H | |
11 | ||
6c0bbdcc NI |
12 | #define CONFIG_CPU_SH7722 1 |
13 | #define CONFIG_MS7722SE 1 | |
14 | ||
5783758f | 15 | #define CONFIG_CMD_JFFS2 |
6c0bbdcc | 16 | #define CONFIG_CMD_SDRAM |
6c0bbdcc NI |
17 | |
18 | #define CONFIG_BAUDRATE 115200 | |
53677ef1 | 19 | #define CONFIG_BOOTARGS "console=ttySC0,115200 root=1f01" |
6c0bbdcc | 20 | |
6c0bbdcc NI |
21 | #undef CONFIG_SHOW_BOOT_PROGRESS |
22 | ||
23 | /* SMC9111 */ | |
7194ab80 | 24 | #define CONFIG_SMC91111 |
6c0bbdcc NI |
25 | #define CONFIG_SMC91111_BASE (0xB8000000) |
26 | ||
27 | /* MEMORY */ | |
28 | #define MS7722SE_SDRAM_BASE (0x8C000000) | |
29 | #define MS7722SE_FLASH_BASE_1 (0xA0000000) | |
6c0bbdcc NI |
30 | #define MS7722SE_FLASH_BANK_SIZE (8*1024 * 1024) |
31 | ||
5c1877d6 | 32 | #define CONFIG_SYS_TEXT_BASE 0x8FFC0000 |
6d0f6bcf | 33 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
6d0f6bcf JCPV |
34 | #define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */ |
35 | #define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */ | |
36 | #define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */ | |
37 | #define CONFIG_SYS_BARGSIZE 512 /* Buffer size for Boot Arguments passed to kernel */ | |
38 | #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */ | |
6c0bbdcc NI |
39 | |
40 | /* SCIF */ | |
6c58a030 | 41 | #define CONFIG_SCIF_CONSOLE 1 |
6c0bbdcc | 42 | #define CONFIG_CONS_SCIF0 1 |
6d0f6bcf JCPV |
43 | #undef CONFIG_SYS_CONSOLE_INFO_QUIET /* Suppress display of console information at boot */ |
44 | #undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE | |
45 | #undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE | |
6c0bbdcc | 46 | |
6d0f6bcf JCPV |
47 | #define CONFIG_SYS_MEMTEST_START (MS7722SE_SDRAM_BASE) |
48 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024)) | |
6c0bbdcc | 49 | |
6d0f6bcf JCPV |
50 | #undef CONFIG_SYS_ALT_MEMTEST /* Enable alternate, more extensive, memory test */ |
51 | #undef CONFIG_SYS_MEMTEST_SCRATCH /* Scratch address used by the alternate memory test */ | |
6c0bbdcc | 52 | |
6d0f6bcf | 53 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* Enable temporary baudrate change while serial download */ |
6c0bbdcc | 54 | |
6d0f6bcf JCPV |
55 | #define CONFIG_SYS_SDRAM_BASE (MS7722SE_SDRAM_BASE) |
56 | #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) /* maybe more, but if so u-boot doesn't know about it... */ | |
6c0bbdcc | 57 | |
6d0f6bcf | 58 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024) /* default load address for scripts ?!? */ |
6c0bbdcc | 59 | |
6d0f6bcf | 60 | #define CONFIG_SYS_MONITOR_BASE (MS7722SE_FLASH_BASE_1) /* Address of u-boot image |
53677ef1 | 61 | in Flash (NOT run time address in SDRAM) ?!? */ |
6d0f6bcf JCPV |
62 | #define CONFIG_SYS_MONITOR_LEN (128 * 1024) /* */ |
63 | #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Size of DRAM reserved for malloc() use */ | |
6d0f6bcf | 64 | #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) |
6c0bbdcc NI |
65 | |
66 | /* FLASH */ | |
6d0f6bcf | 67 | #define CONFIG_SYS_FLASH_CFI |
00b1883a | 68 | #define CONFIG_FLASH_CFI_DRIVER |
6d0f6bcf JCPV |
69 | #undef CONFIG_SYS_FLASH_QUIET_TEST |
70 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ | |
6c0bbdcc | 71 | |
6d0f6bcf | 72 | #define CONFIG_SYS_FLASH_BASE (MS7722SE_FLASH_BASE_1) /* Physical start address of Flash memory */ |
6c0bbdcc | 73 | |
6d0f6bcf | 74 | #define CONFIG_SYS_MAX_FLASH_SECT 150 /* Max number of sectors on each |
53677ef1 | 75 | Flash chip */ |
6c0bbdcc NI |
76 | |
77 | /* if you use all NOR Flash , you change dip-switch. Please see MS7722SE01 Manual. */ | |
6d0f6bcf JCPV |
78 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 |
79 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + (0 * MS7722SE_FLASH_BANK_SIZE), \ | |
80 | CONFIG_SYS_FLASH_BASE + (1 * MS7722SE_FLASH_BANK_SIZE), \ | |
6c0bbdcc NI |
81 | } |
82 | ||
6d0f6bcf JCPV |
83 | #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) /* Timeout for Flash erase operations (in ms) */ |
84 | #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) /* Timeout for Flash write operations (in ms) */ | |
85 | #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) /* Timeout for Flash set sector lock bit operations (in ms) */ | |
86 | #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) /* Timeout for Flash clear lock bit operations (in ms) */ | |
6c0bbdcc | 87 | |
6d0f6bcf | 88 | #undef CONFIG_SYS_FLASH_PROTECTION /* Use hardware flash sectors protection instead of U-Boot software protection */ |
6c0bbdcc | 89 | |
6d0f6bcf | 90 | #undef CONFIG_SYS_DIRECT_FLASH_TFTP |
6c0bbdcc | 91 | |
5a1aceb0 | 92 | #define CONFIG_ENV_IS_IN_FLASH |
6c0bbdcc | 93 | #define CONFIG_ENV_OVERWRITE 1 |
0e8d1586 JCPV |
94 | #define CONFIG_ENV_SECT_SIZE (8 * 1024) |
95 | #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) | |
6d0f6bcf JCPV |
96 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + (1 * CONFIG_ENV_SECT_SIZE)) |
97 | #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */ | |
0e8d1586 | 98 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) |
6d0f6bcf | 99 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE)) |
6c0bbdcc NI |
100 | |
101 | /* Board Clock */ | |
102 | #define CONFIG_SYS_CLK_FREQ 33333333 | |
684a501e NI |
103 | #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ |
104 | #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ | |
be45c632 | 105 | #define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */ |
6c0bbdcc NI |
106 | |
107 | #endif /* __MS7722SE_H */ |