[people/ms/u-boot.git] / include / configs / ms7750se.h

/*
 * Configuation settings for the Hitachi Solution Engine 7750
 *
 * Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __MS7750SE_H
#define __MS7750SE_H

#define CONFIG_SH		1
#define CONFIG_SH4		1
#define CONFIG_CPU_SH7750	1
/* #define CONFIG_CPU_SH7751	1 */
/* #define CONFIG_CPU_TYPE_R	1 */
#define CONFIG_MS7750SE		1
#define __LITTLE_ENDIAN__	1

/*
 * Command line configuration.
 */
/*#include <config_cmd_default.h>*/

#define CONFIG_CMD_FLASH
#define CONFIG_CMD_SAVEENV

#define CONFIG_SCIF_CONSOLE	1
#define CONFIG_BAUDRATE		38400
#define CONFIG_CONS_SCIF1	1
#define CONFIG_BOARD_LATE_INIT

#define CONFIG_BOOTDELAY	-1
#define CONFIG_BOOTARGS		"console=ttySC0,38400"
#define CONFIG_ENV_OVERWRITE	1

/* SDRAM */
#define CONFIG_SYS_SDRAM_BASE		(0x8C000000)
#define CONFIG_SYS_SDRAM_SIZE		(64 * 1024 * 1024)

#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_PROMPT		"=> "
#define CONFIG_SYS_CBSIZE		256
#define CONFIG_SYS_PBSIZE		256
#define CONFIG_SYS_MAXARGS		16
#define CONFIG_SYS_BARGSIZE		512

#define CONFIG_SYS_TEXT_BASE		0x8FFC0000
#define CONFIG_SYS_MEMTEST_START	(CONFIG_SYS_SDRAM_BASE)
#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_TEXT_BASE - 0x100000)

/* NOR Flash */
/* #define CONFIG_SYS_FLASH_BASE		(0xA1000000)*/
#define CONFIG_SYS_FLASH_BASE		(0xA0000000)
#define CONFIG_SYS_MAX_FLASH_BANKS	(1)	/* Max number of
					 * Flash memory banks
					 */
#define CONFIG_SYS_MAX_FLASH_SECT	142
#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }

#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE)	/* Address of u-boot image in Flash */
#define CONFIG_SYS_MONITOR_LEN		(128 * 1024)
#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)		/* Size of DRAM reserved for malloc() use */

#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
#define CONFIG_SYS_RX_ETH_BUFFER	(8)

#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
#undef CONFIG_SYS_FLASH_CFI_BROKEN_TABLE
#undef  CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_SYS_FLASH_EMPTY_INFO				/* print 'E' for empty sector on flinfo */


#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE	0x20000
#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_SYS_FLASH_ERASE_TOUT	120000
#define CONFIG_SYS_FLASH_WRITE_TOUT	500

/* Board Clock */
#define CONFIG_SYS_CLK_FREQ	33333333
#define CONFIG_SYS_TMU_CLK_DIV		4
#define CONFIG_SYS_HZ		1000

#endif /* __MS7750SE_H */
Commit	Line	Data
047375bf NI	1	/*
	2	* Configuation settings for the Hitachi Solution Engine 7750
	3	*
	4	* Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
047375bf NI	7	*/
	8
	9	#ifndef __MS7750SE_H
	10	#define __MS7750SE_H
69df3c4d	11
69df3c4d NI	12	#define CONFIG_SH 1
	13	#define CONFIG_SH4 1
	14	#define CONFIG_CPU_SH7750 1
047375bf NI	15	/* #define CONFIG_CPU_SH7751 1 */
047375bf NI	16	/* #define CONFIG_CPU_TYPE_R 1 */
69df3c4d NI	17	#define CONFIG_MS7750SE 1
	18	#define __LITTLE_ENDIAN__ 1
	19
047375bf NI	20	/*
	21	* Command line configuration.
	22	*/
61fb15c5	23	/#include <config_cmd_default.h>/
047375bf	24
047375bf	25	#define CONFIG_CMD_FLASH
bdab39d3	26	#define CONFIG_CMD_SAVEENV
69df3c4d	27
6c58a030	28	#define CONFIG_SCIF_CONSOLE 1
69df3c4d NI	29	#define CONFIG_BAUDRATE 38400
69df3c4d NI	30	#define CONFIG_CONS_SCIF1 1
9660e442	31	#define CONFIG_BOARD_LATE_INIT
69df3c4d	32
69df3c4d	33	#define CONFIG_BOOTDELAY -1
53677ef1	34	#define CONFIG_BOOTARGS "console=ttySC0,38400"
69df3c4d NI	35	#define CONFIG_ENV_OVERWRITE 1
69df3c4d NI	36
047375bf	37	/* SDRAM */
6d0f6bcf JCPV	38	#define CONFIG_SYS_SDRAM_BASE (0x8C000000)
	39	#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
	40
	41	#define CONFIG_SYS_LONGHELP
	42	#define CONFIG_SYS_PROMPT "=> "
	43	#define CONFIG_SYS_CBSIZE 256
	44	#define CONFIG_SYS_PBSIZE 256
	45	#define CONFIG_SYS_MAXARGS 16
	46	#define CONFIG_SYS_BARGSIZE 512
69df3c4d	47
da8241ba	48	#define CONFIG_SYS_TEXT_BASE 0x8FFC0000
6d0f6bcf	49	#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
14d0a02a	50	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000)
69df3c4d	51
047375bf	52	/* NOR Flash */
6d0f6bcf JCPV	53	/* #define CONFIG_SYS_FLASH_BASE (0xA1000000)*/
	54	#define CONFIG_SYS_FLASH_BASE (0xA0000000)
	55	#define CONFIG_SYS_MAX_FLASH_BANKS (1) /* Max number of
53677ef1 WD	56	* Flash memory banks
53677ef1 WD	57	*/
6d0f6bcf JCPV	58	#define CONFIG_SYS_MAX_FLASH_SECT 142
6d0f6bcf JCPV	59	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
69df3c4d	60
6d0f6bcf JCPV	61	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
	62	#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) /* Address of u-boot image in Flash */
	63	#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
	64	#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Size of DRAM reserved for malloc() use */
69df3c4d	65
6d0f6bcf JCPV	66	#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
6d0f6bcf JCPV	67	#define CONFIG_SYS_RX_ETH_BUFFER (8)
69df3c4d	68
6d0f6bcf	69	#define CONFIG_SYS_FLASH_CFI
00b1883a	70	#define CONFIG_FLASH_CFI_DRIVER
6d0f6bcf JCPV	71	#undef CONFIG_SYS_FLASH_CFI_BROKEN_TABLE
	72	#undef CONFIG_SYS_FLASH_QUIET_TEST
	73	#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
69df3c4d	74
69df3c4d	75
5a1aceb0	76	#define CONFIG_ENV_IS_IN_FLASH
0e8d1586 JCPV	77	#define CONFIG_ENV_SECT_SIZE 0x20000
0e8d1586 JCPV	78	#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
6d0f6bcf JCPV	79	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
	80	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
	81	#define CONFIG_SYS_FLASH_WRITE_TOUT 500
69df3c4d	82
047375bf	83	/* Board Clock */
69df3c4d	84	#define CONFIG_SYS_CLK_FREQ 33333333
be45c632	85	#define CONFIG_SYS_TMU_CLK_DIV 4
8dd29c87	86	#define CONFIG_SYS_HZ 1000
69df3c4d	87
047375bf	88	#endif /* __MS7750SE_H */