[people/ms/u-boot.git] / include / configs / muas3001.h

/*
 * (C) Copyright 2008
 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+ 
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_8260		1
#define CONFIG_MPC8260		1
#define CONFIG_MUAS3001		1

#define	CONFIG_SYS_TEXT_BASE	0xFF000000

#define CONFIG_CPM2		1	/* Has a CPM2 */

/* Do boardspecific init */
#define CONFIG_BOARD_EARLY_INIT_R       1

/* enable Watchdog */
#define CONFIG_WATCHDOG		1

/*
 * Select serial console configuration
 *
 * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
 * for SCC).
 */
#define	CONFIG_CONS_ON_SMC		/* Console is on SMC         */
#undef  CONFIG_CONS_ON_SCC		/* It's not on SCC           */
#undef	CONFIG_CONS_NONE		/* It's not on external UART */
#if defined(CONFIG_MUAS_DEV_BOARD)
#define CONFIG_CONS_INDEX	2	/* SMC2 is used for console  */
#else
#define CONFIG_CONS_INDEX	1	/* SMC1 is used for console  */
#endif

/*
 * Select ethernet configuration
 *
 * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
 * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
 * SCC, 1-3 for FCC)
 *
 * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
 * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
 * must be unset.
 */
#undef	CONFIG_ETHER_ON_SCC		/* Ethernet is not on SCC */
#define	CONFIG_ETHER_ON_FCC		/* Ethernet is on FCC     */
#undef	CONFIG_ETHER_NONE		/* No external Ethernet   */

#define CONFIG_ETHER_INDEX	1
#define CONFIG_ETHER_ON_FCC1
#define CONFIG_HAS_ETH0
#define FCC_ENET

/*
 * - Rx-CLK is CLK11
 * - Tx-CLK is CLK12
 */
# define CONFIG_SYS_CMXFCR_VALUE1	(CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK12)
# define CONFIG_SYS_CMXFCR_MASK1	(CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
/*
 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
 */
# define CONFIG_SYS_CPMFCR_RAMTYPE	(0)
/* know on local Bus */
/* define CONFIG_SYS_CPMFCR_RAMTYPE	(CPMFCR_DTB | CPMFCR_BDB) */
/*
 * - Enable Full Duplex in FSMR
 */
# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)

#define CONFIG_MII			/* MII PHY management		*/
#define CONFIG_BITBANGMII		/* bit-bang MII PHY management	*/
# define CONFIG_SYS_PHY_ADDR		1
/*
 * GPIO pins used for bit-banged MII communications
 */
#define MDIO_PORT	0		/* Port A */
#define MDIO_DECLARE	volatile ioport_t *iop = ioport_addr ( \
				(immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
#define MDC_DECLARE	MDIO_DECLARE


#define CONFIG_SYS_MDIO_PIN	0x00200000	/* PA10 */
#define CONFIG_SYS_MDC_PIN	0x00400000	/* PA9  */

#define MDIO_ACTIVE	(iop->pdir |=  CONFIG_SYS_MDIO_PIN)
#define MDIO_TRISTATE	(iop->pdir &= ~CONFIG_SYS_MDIO_PIN)
#define MDIO_READ	((iop->pdat &  CONFIG_SYS_MDIO_PIN) != 0)

#define MDIO(bit)	if(bit) iop->pdat |=  CONFIG_SYS_MDIO_PIN; \
			else	iop->pdat &= ~CONFIG_SYS_MDIO_PIN

#define MDC(bit)	if(bit) iop->pdat |=  CONFIG_SYS_MDC_PIN; \
			else	iop->pdat &= ~CONFIG_SYS_MDC_PIN

#define MIIDELAY	udelay(1)

#ifndef CONFIG_8260_CLKIN
#define CONFIG_8260_CLKIN	66000000	/* in Hz */
#endif

#define CONFIG_BAUDRATE		115200

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_DTT
#define CONFIG_CMD_ECHO
#define CONFIG_CMD_IMMAP
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C

/*
 * Default environment settings
 */
#define CONFIG_EXTRA_ENV_SETTINGS						\
	"netdev=eth0\0"								\
	"u-boot_addr_r=100000\0"						\
	"kernel_addr_r=200000\0"						\
	"fdt_addr_r=400000\0"							\
	"rootpath=/opt/eldk/ppc_6xx\0"						\
	"u-boot=muas3001/u-boot.bin\0"						\
	"bootfile=muas3001/uImage\0"						\
	"fdt_file=muas3001/muas3001.dtb\0"					\
	"ramdisk_file=uRamdisk\0"						\
	"load=tftp ${u-boot_addr_r} ${u-boot}\0"				\
	"update=prot off ff000000 ff03ffff; era ff000000 ff03ffff; "		\
		"cp.b ${u-boot_addr_r} ff000000 ${filesize};"			\
		"prot on ff000000 ff03ffff\0"					\
	"ramargs=setenv bootargs root=/dev/ram rw\0"				\
	"nfsargs=setenv bootargs root=/dev/nfs rw "				\
		"nfsroot=${serverip}:${rootpath}\0"				\
	"addcons=setenv bootargs ${bootargs} console=ttyCPM0,${baudrate}\0"	\
	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"			\
	"addip=setenv bootargs ${bootargs} "					\
		"ip=${ipaddr}:${serverip}:${gatewayip}:"			\
		"${netmask}:${hostname}:${netdev}:off panic=1\0"		\
	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; "				\
		"tftp ${fdt_addr_r} ${fdt_file}; run nfsargs addip addcons;"	\
		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"			\
	"net_self=tftp ${kernel_addr_r} ${bootfile}; "				\
		"tftp ${fdt_addr_r} ${fdt_file}; "				\
		"tftp ${ramdisk_addr} ${ramdisk_file}; "			\
		"run ramargs addip; "						\
		"bootm ${kernel_addr_r} ${ramdisk_addr} ${fdt_addr_r}\0"	\
	"ramdisk_addr=ff210000\0"						\
	"kernel_addr=ff050000\0"						\
	"fdt_addr=ff200000\0"							\
	"flash_self=run ramargs addip addcons;bootm ${kernel_addr}"		\
	" ${ramdisk_addr} ${fdt_addr}\0"					\
	"updateramdisk=era ${ramdisk_addr} +1f0000;tftpb ${kernel_addr_r}"	\
	" ${ramdisk_file};"							\
	"cp.b ${kernel_addr_r} ${ramdisk_addr} ${filesize}\0"			\
	"updatekernel=era ${kernel_addr} +1b0000;tftpb ${kernel_addr_r}"	\
	" ${bootfile};"								\
	"cp.b ${kernel_addr_r} ${kernel_addr} ${filesize}\0"			\
	"updatefdt=era ${fdt_addr} +10000;tftpb ${fdt_addr_r} ${fdt_file};"	\
	"cp.b ${fdt_addr_r} ${fdt_addr} ${filesize}\0"				\
	""

#define CONFIG_BOOTCOMMAND	"run net_nfs"
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
#else
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size  */
#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size  */

#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/

#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */

#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */

#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }

#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_FLASH_BASE		0xFF000000
#define CONFIG_SYS_FLASH_SIZE		32
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of flash banks	*/
#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max num of sects on one chip */

#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }

#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#endif

#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256KB for Monitor */

#define CONFIG_ENV_IS_IN_FLASH

#ifdef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE	0x10000
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#endif /* CONFIG_ENV_IS_IN_FLASH */

/*
 * I2C Bus
 */
#define CONFIG_HARD_I2C		1	/* To enable I2C support	*/
#define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed and slave address	*/
#define CONFIG_SYS_I2C_SLAVE		0x7F

#define	CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
/* I2C SYSMON (LM75, AD7414 is almost compatible)                       */
#define	CONFIG_DTT_LM75		1	/* ON Semi's LM75               */
#define	CONFIG_DTT_SENSORS	{0}	/* Sensor addresses             */
#define	CONFIG_SYS_DTT_MAX_TEMP	70
#define	CONFIG_SYS_DTT_LOW_TEMP	-30
#define	CONFIG_SYS_DTT_HYSTERESIS	3

#define CONFIG_SYS_IMMR		0xF0000000
#define CONFIG_SYS_DEFAULT_IMMR	0x0F010000

#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
#define CONFIG_SYS_INIT_RAM_SIZE	0x2000	/* Size of used area in DPRAM	*/
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/* Hard reset configuration word */
#define CONFIG_SYS_HRCW_MASTER		0x0E028200	/* BPS=11 CIP=1 ISB=010 BMS=1 */

/* No slaves */
#define CONFIG_SYS_HRCW_SLAVE1 	0
#define CONFIG_SYS_HRCW_SLAVE2 	0
#define CONFIG_SYS_HRCW_SLAVE3 	0
#define CONFIG_SYS_HRCW_SLAVE4 	0
#define CONFIG_SYS_HRCW_SLAVE5 	0
#define CONFIG_SYS_HRCW_SLAVE6 	0
#define CONFIG_SYS_HRCW_SLAVE7 	0

#define CONFIG_SYS_MALLOC_LEN		(4096 << 10)	/* Reserve 4 MB for malloc()	*/
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8260 CPUs */
#if defined(CONFIG_CMD_KGDB)
#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif

#define CONFIG_SYS_HID0_INIT		0
#define CONFIG_SYS_HID0_FINAL		(HID0_ICE | HID0_IFEM | HID0_ABE)

#define CONFIG_SYS_HID2		0

#define CONFIG_SYS_SIUMCR		0x00200000
#define CONFIG_SYS_BCR			0x004c0000
#define CONFIG_SYS_SCCR		0x0

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control                             4-35
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 */
#if defined(CONFIG_WATCHDOG)
#define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
#else
#define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
			 SYPCR_SWRI|SYPCR_SWP)
#endif /* CONFIG_WATCHDOG */

/*-----------------------------------------------------------------------
 * RMR - Reset Mode Register                                     5-5
 *-----------------------------------------------------------------------
 * turn on Checkstop Reset Enable
 */
#define CONFIG_SYS_RMR         0

/*-----------------------------------------------------------------------
 * TMCNTSC - Time Counter Status and Control                     4-40
 *-----------------------------------------------------------------------
 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 * and enable Time Counter
 */
#define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control                 4-42
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 * Periodic timer
 */
#define CONFIG_SYS_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)

/*-----------------------------------------------------------------------
 * RCCR - RISC Controller Configuration                         13-7
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_RCCR        0

/*
 * Init Memory Controller:
 *
 * Bank Bus     Machine PortSz  Device
 * ---- ---     ------- ------  ------
 *  0   60x     GPCM    32 bit  FLASH
 *  1   60x     SDRAM   64 bit  SDRAM
 *  4   60x     GPCM    16 bit  I/O Ctrl
 *
 */
/* Bank 0 - FLASH
 */
#define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)	|\
			 BRx_PS_32			|\
			 BRx_MS_GPCM_P			|\
			 BRx_V)

#define CONFIG_SYS_OR0_PRELIM (0xff000020)

/* Bank 1 - 60x bus SDRAM
 */
#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT	(256 << 20)	/* less than 256 MB */

#define CONFIG_SYS_MPTPR       0x2800

/*-----------------------------------------------------------------------------
 * Address for Mode Register Set (MRS) command
 *-----------------------------------------------------------------------------
 */
#define CONFIG_SYS_MRS_OFFS	0x00000110
#define CONFIG_SYS_PSRT        0x13

#define CONFIG_SYS_BR1_PRELIM  ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK)  |\
			 BRx_PS_64                      |\
			 BRx_MS_SDRAM_P                 |\
			 BRx_V)

#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR1_LITTLE

/* SDRAM initialization values
*/
#define CONFIG_SYS_OR1_LITTLE	((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
			 ORxS_BPD_4                     |\
			 ORxS_ROWST_PBI1_A7		|\
			 ORxS_NUMR_12)

#define CONFIG_SYS_PSDMR_LITTLE	0x004b36a3

#define CONFIG_SYS_OR1_BIG	((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
			 ORxS_BPD_4                     |\
			 ORxS_ROWST_PBI1_A4		|\
			 ORxS_NUMR_12)

#define CONFIG_SYS_PSDMR_BIG		0x014f36a3

/* IO on CS4 initialization values
*/
#define CONFIG_SYS_IO_BASE	0xc0000000
#define CONFIG_SYS_IO_SIZE	1

#define CONFIG_SYS_BR4_PRELIM	((CONFIG_SYS_IO_BASE & BRx_BA_MSK) |\
			 BRx_PS_16 | BRx_MS_GPCM_L | BRx_V)

#define CONFIG_SYS_OR4_PRELIM	(0xfff80020)

#define	CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC	/* "bad" address		*/

/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT	1
#define CONFIG_OF_BOARD_SETUP	1

#define OF_TBCLK		(bd->bi_busfreq / 4)
#if defined(CONFIG_MUAS_DEV_BOARD)
#define OF_STDOUT_PATH		"/soc/cpm/serial@11a90"
#else
#define OF_STDOUT_PATH		"/soc/cpm/serial@11a80"
#endif

#endif /* __CONFIG_H */
Commit	Line	Data
adf22b66 HS	1	/*
	2	* (C) Copyright 2008
	3	* Heiko Schocher, DENX Software Engineering, hs@denx.de.
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
adf22b66 HS	6	*/
	7
	8	#ifndef __CONFIG_H
	9	#define __CONFIG_H
	10
	11	/*
	12	* High Level Configuration Options
	13	* (easy to change)
	14	*/
	15
	16	#define CONFIG_8260 1
	17	#define CONFIG_MPC8260 1
	18	#define CONFIG_MUAS3001 1
	19
2ae18241 WD	20	#define CONFIG_SYS_TEXT_BASE 0xFF000000
2ae18241 WD	21
adf22b66 HS	22	#define CONFIG_CPM2 1 /* Has a CPM2 */
	23
	24	/* Do boardspecific init */
	25	#define CONFIG_BOARD_EARLY_INIT_R 1
	26
4a02a2dc HS	27	/* enable Watchdog */
	28	#define CONFIG_WATCHDOG 1
	29
adf22b66 HS	30	/*
	31	* Select serial console configuration
	32	*
	33	* If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
	34	* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
	35	* for SCC).
	36	*/
	37	#define CONFIG_CONS_ON_SMC /* Console is on SMC */
	38	#undef CONFIG_CONS_ON_SCC /* It's not on SCC */
	39	#undef CONFIG_CONS_NONE /* It's not on external UART */
	40	#if defined(CONFIG_MUAS_DEV_BOARD)
	41	#define CONFIG_CONS_INDEX 2 /* SMC2 is used for console */
	42	#else
	43	#define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */
	44	#endif
	45
	46	/*
	47	* Select ethernet configuration
	48	*
	49	* If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
	50	* then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
	51	* SCC, 1-3 for FCC)
	52	*
	53	* If CONFIG_ETHER_NONE is defined, then either the ethernet routines
	54	* must be defined elsewhere (as for the console), or CONFIG_CMD_NET
	55	* must be unset.
	56	*/
	57	#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */
	58	#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */
	59	#undef CONFIG_ETHER_NONE /* No external Ethernet */
	60
	61	#define CONFIG_ETHER_INDEX 1
	62	#define CONFIG_ETHER_ON_FCC1
3ca55bce	63	#define CONFIG_HAS_ETH0
adf22b66 HS	64	#define FCC_ENET
	65
	66	/*
	67	* - Rx-CLK is CLK11
	68	* - Tx-CLK is CLK12
	69	*/
d4590da4 MF	70	# define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11 \| CMXFCR_TF1CS_CLK12)
d4590da4 MF	71	# define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1 \| CMXFCR_RF1CS_MSK \| CMXFCR_TF1CS_MSK)
adf22b66 HS	72	/*
	73	* - RAM for BD/Buffers is on the 60x Bus (see 28-13)
	74	*/
6d0f6bcf	75	# define CONFIG_SYS_CPMFCR_RAMTYPE (0)
adf22b66	76	/* know on local Bus */
6d0f6bcf	77	/* define CONFIG_SYS_CPMFCR_RAMTYPE (CPMFCR_DTB \| CPMFCR_BDB) */
adf22b66 HS	78	/*
	79	* - Enable Full Duplex in FSMR
	80	*/
6d0f6bcf	81	# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE\|FCC_PSMR_LPB)
adf22b66 HS	82
	83	#define CONFIG_MII /* MII PHY management */
	84	#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
6d0f6bcf	85	# define CONFIG_SYS_PHY_ADDR 1
adf22b66 HS	86	/*
	87	* GPIO pins used for bit-banged MII communications
	88	*/
	89	#define MDIO_PORT 0 /* Port A */
be225442 LCM	90	#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
	91	(immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
	92	#define MDC_DECLARE MDIO_DECLARE
	93
adf22b66	94
6d0f6bcf JCPV	95	#define CONFIG_SYS_MDIO_PIN 0x00200000 /* PA10 */
6d0f6bcf JCPV	96	#define CONFIG_SYS_MDC_PIN 0x00400000 /* PA9 */
adf22b66	97
6d0f6bcf JCPV	98	#define MDIO_ACTIVE (iop->pdir \|= CONFIG_SYS_MDIO_PIN)
	99	#define MDIO_TRISTATE (iop->pdir &= ~CONFIG_SYS_MDIO_PIN)
	100	#define MDIO_READ ((iop->pdat & CONFIG_SYS_MDIO_PIN) != 0)
adf22b66	101
6d0f6bcf JCPV	102	#define MDIO(bit) if(bit) iop->pdat \|= CONFIG_SYS_MDIO_PIN; \
6d0f6bcf JCPV	103	else iop->pdat &= ~CONFIG_SYS_MDIO_PIN
adf22b66	104
6d0f6bcf JCPV	105	#define MDC(bit) if(bit) iop->pdat \|= CONFIG_SYS_MDC_PIN; \
6d0f6bcf JCPV	106	else iop->pdat &= ~CONFIG_SYS_MDC_PIN
adf22b66 HS	107
	108	#define MIIDELAY udelay(1)
	109
	110	#ifndef CONFIG_8260_CLKIN
	111	#define CONFIG_8260_CLKIN 66000000 /* in Hz */
	112	#endif
	113
	114	#define CONFIG_BAUDRATE 115200
	115
	116	/*
	117	* Command line configuration.
	118	*/
	119	#include <config_cmd_default.h>
	120
245f6ef3	121	#define CONFIG_CMD_DTT
adf22b66 HS	122	#define CONFIG_CMD_ECHO
	123	#define CONFIG_CMD_IMMAP
	124	#define CONFIG_CMD_MII
	125	#define CONFIG_CMD_PING
	126	#define CONFIG_CMD_I2C
	127
	128	/*
	129	* Default environment settings
	130	*/
	131	#define CONFIG_EXTRA_ENV_SETTINGS \
	132	"netdev=eth0\0" \
	133	"u-boot_addr_r=100000\0" \
	134	"kernel_addr_r=200000\0" \
	135	"fdt_addr_r=400000\0" \
	136	"rootpath=/opt/eldk/ppc_6xx\0" \
	137	"u-boot=muas3001/u-boot.bin\0" \
	138	"bootfile=muas3001/uImage\0" \
	139	"fdt_file=muas3001/muas3001.dtb\0" \
	140	"ramdisk_file=uRamdisk\0" \
	141	"load=tftp ${u-boot_addr_r} ${u-boot}\0" \
	142	"update=prot off ff000000 ff03ffff; era ff000000 ff03ffff; " \
	143	"cp.b ${u-boot_addr_r} ff000000 ${filesize};" \
	144	"prot on ff000000 ff03ffff\0" \
	145	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	146	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	147	"nfsroot=${serverip}:${rootpath}\0" \
	148	"addcons=setenv bootargs ${bootargs} console=ttyCPM0,${baudrate}\0" \
	149	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
	150	"addip=setenv bootargs ${bootargs} " \
	151	"ip=${ipaddr}:${serverip}:${gatewayip}:" \
	152	"${netmask}:${hostname}:${netdev}:off panic=1\0" \
	153	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
	154	"tftp ${fdt_addr_r} ${fdt_file}; run nfsargs addip addcons;" \
	155	"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
	156	"net_self=tftp ${kernel_addr_r} ${bootfile}; " \
	157	"tftp ${fdt_addr_r} ${fdt_file}; " \
	158	"tftp ${ramdisk_addr} ${ramdisk_file}; " \
	159	"run ramargs addip; " \
	160	"bootm ${kernel_addr_r} ${ramdisk_addr} ${fdt_addr_r}\0" \
	161	"ramdisk_addr=ff210000\0" \
	162	"kernel_addr=ff050000\0" \
	163	"fdt_addr=ff200000\0" \
	164	"flash_self=run ramargs addip addcons;bootm ${kernel_addr}" \
	165	" ${ramdisk_addr} ${fdt_addr}\0" \
	166	"updateramdisk=era ${ramdisk_addr} +1f0000;tftpb ${kernel_addr_r}" \
	167	" ${ramdisk_file};" \
	168	"cp.b ${kernel_addr_r} ${ramdisk_addr} ${filesize}\0" \
	169	"updatekernel=era ${kernel_addr} +1b0000;tftpb ${kernel_addr_r}" \
	170	" ${bootfile};" \
	171	"cp.b ${kernel_addr_r} ${kernel_addr} ${filesize}\0" \
	172	"updatefdt=era ${fdt_addr} +10000;tftpb ${fdt_addr_r} ${fdt_file};" \
	173	"cp.b ${fdt_addr_r} ${fdt_addr} ${filesize}\0" \
	174	""
	175
	176	#define CONFIG_BOOTCOMMAND "run net_nfs"
	177	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	178
adf22b66 HS	179	/*
	180	* Miscellaneous configurable options
	181	*/
6d0f6bcf	182	#define CONFIG_SYS_HUSH_PARSER
6d0f6bcf JCPV	183	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	184	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
adf22b66	185	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	186	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
adf22b66	187	#else
6d0f6bcf	188	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
adf22b66	189	#endif
6d0f6bcf JCPV	190	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	191	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	192	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
adf22b66	193
6d0f6bcf JCPV	194	#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
6d0f6bcf JCPV	195	#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
adf22b66	196
6d0f6bcf	197	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
adf22b66	198
6d0f6bcf	199	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
adf22b66	200
6d0f6bcf	201	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
adf22b66	202
6d0f6bcf JCPV	203	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	204	#define CONFIG_SYS_FLASH_BASE 0xFF000000
	205	#define CONFIG_SYS_FLASH_SIZE 32
	206	#define CONFIG_SYS_FLASH_CFI
adf22b66	207	#define CONFIG_FLASH_CFI_DRIVER
6d0f6bcf JCPV	208	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
6d0f6bcf JCPV	209	#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
adf22b66	210
6d0f6bcf	211	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
adf22b66	212
14d0a02a	213	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
6d0f6bcf JCPV	214	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
6d0f6bcf JCPV	215	#define CONFIG_SYS_RAMBOOT
adf22b66 HS	216	#endif
adf22b66 HS	217
6d0f6bcf	218	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256KB for Monitor */
adf22b66	219
5a1aceb0	220	#define CONFIG_ENV_IS_IN_FLASH
adf22b66	221
5a1aceb0	222	#ifdef CONFIG_ENV_IS_IN_FLASH
0e8d1586	223	#define CONFIG_ENV_SECT_SIZE 0x10000
6d0f6bcf	224	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
5a1aceb0	225	#endif /* CONFIG_ENV_IS_IN_FLASH */
adf22b66 HS	226
	227	/*
	228	* I2C Bus
	229	*/
	230	#define CONFIG_HARD_I2C 1 /* To enable I2C support */
6d0f6bcf JCPV	231	#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
6d0f6bcf JCPV	232	#define CONFIG_SYS_I2C_SLAVE 0x7F
adf22b66	233
6d0f6bcf	234	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
245f6ef3 HS	235	/* I2C SYSMON (LM75, AD7414 is almost compatible) */
	236	#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
	237	#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
6d0f6bcf JCPV	238	#define CONFIG_SYS_DTT_MAX_TEMP 70
	239	#define CONFIG_SYS_DTT_LOW_TEMP -30
	240	#define CONFIG_SYS_DTT_HYSTERESIS 3
245f6ef3	241
6d0f6bcf JCPV	242	#define CONFIG_SYS_IMMR 0xF0000000
6d0f6bcf JCPV	243	#define CONFIG_SYS_DEFAULT_IMMR 0x0F010000
adf22b66	244
6d0f6bcf	245	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
553f0982	246	#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */
25ddd1fb	247	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	248	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
adf22b66 HS	249
adf22b66 HS	250	/* Hard reset configuration word */
6d0f6bcf	251	#define CONFIG_SYS_HRCW_MASTER 0x0E028200 /* BPS=11 CIP=1 ISB=010 BMS=1 */
adf22b66 HS	252
adf22b66 HS	253	/* No slaves */
6d0f6bcf JCPV	254	#define CONFIG_SYS_HRCW_SLAVE1 0
	255	#define CONFIG_SYS_HRCW_SLAVE2 0
	256	#define CONFIG_SYS_HRCW_SLAVE3 0
	257	#define CONFIG_SYS_HRCW_SLAVE4 0
	258	#define CONFIG_SYS_HRCW_SLAVE5 0
	259	#define CONFIG_SYS_HRCW_SLAVE6 0
	260	#define CONFIG_SYS_HRCW_SLAVE7 0
adf22b66	261
6d0f6bcf JCPV	262	#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
6d0f6bcf JCPV	263	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
adf22b66	264
6d0f6bcf	265	#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
adf22b66	266	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	267	# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
adf22b66 HS	268	#endif
adf22b66 HS	269
6d0f6bcf JCPV	270	#define CONFIG_SYS_HID0_INIT 0
6d0f6bcf JCPV	271	#define CONFIG_SYS_HID0_FINAL (HID0_ICE \| HID0_IFEM \| HID0_ABE)
adf22b66	272
6d0f6bcf	273	#define CONFIG_SYS_HID2 0
adf22b66	274
6d0f6bcf JCPV	275	#define CONFIG_SYS_SIUMCR 0x00200000
	276	#define CONFIG_SYS_BCR 0x004c0000
	277	#define CONFIG_SYS_SCCR 0x0
adf22b66	278
4a02a2dc HS	279	/*-----------------------------------------------------------------------
	280	* SYPCR - System Protection Control 4-35
	281	* SYPCR can only be written once after reset!
	282	*-----------------------------------------------------------------------
	283	* Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
	284	*/
	285	#if defined(CONFIG_WATCHDOG)
6d0f6bcf	286	#define CONFIG_SYS_SYPCR (SYPCR_SWTC\|SYPCR_BMT\|SYPCR_PBME\|SYPCR_LBME\|\
4a02a2dc HS	287	SYPCR_SWRI\|SYPCR_SWP\|SYPCR_SWE)
4a02a2dc HS	288	#else
6d0f6bcf	289	#define CONFIG_SYS_SYPCR (SYPCR_SWTC\|SYPCR_BMT\|SYPCR_PBME\|SYPCR_LBME\|\
4a02a2dc HS	290	SYPCR_SWRI\|SYPCR_SWP)
	291	#endif /* CONFIG_WATCHDOG */
	292
adf22b66 HS	293	/*-----------------------------------------------------------------------
	294	* RMR - Reset Mode Register 5-5
	295	*-----------------------------------------------------------------------
	296	* turn on Checkstop Reset Enable
	297	*/
6d0f6bcf	298	#define CONFIG_SYS_RMR 0
adf22b66 HS	299
	300	/*-----------------------------------------------------------------------
	301	* TMCNTSC - Time Counter Status and Control 4-40
	302	*-----------------------------------------------------------------------
	303	* Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
	304	* and enable Time Counter
	305	*/
6d0f6bcf	306	#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC\|TMCNTSC_ALR\|TMCNTSC_TCF\|TMCNTSC_TCE)
adf22b66 HS	307
	308	/*-----------------------------------------------------------------------
	309	* PISCR - Periodic Interrupt Status and Control 4-42
	310	*-----------------------------------------------------------------------
	311	* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
	312	* Periodic timer
	313	*/
6d0f6bcf	314	#define CONFIG_SYS_PISCR (PISCR_PS\|PISCR_PTF\|PISCR_PTE)
adf22b66 HS	315
	316	/*-----------------------------------------------------------------------
	317	* RCCR - RISC Controller Configuration 13-7
	318	*-----------------------------------------------------------------------
	319	*/
6d0f6bcf	320	#define CONFIG_SYS_RCCR 0
adf22b66 HS	321
	322	/*
	323	* Init Memory Controller:
	324	*
	325	* Bank Bus Machine PortSz Device
	326	* ---- --- ------- ------ ------
	327	* 0 60x GPCM 32 bit FLASH
	328	* 1 60x SDRAM 64 bit SDRAM
	329	* 4 60x GPCM 16 bit I/O Ctrl
	330	*
	331	*/
	332	/* Bank 0 - FLASH
	333	*/
6d0f6bcf	334	#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) \|\
adf22b66 HS	335	BRx_PS_32 \|\
	336	BRx_MS_GPCM_P \|\
	337	BRx_V)
	338
6d0f6bcf	339	#define CONFIG_SYS_OR0_PRELIM (0xff000020)
adf22b66 HS	340
	341	/* Bank 1 - 60x bus SDRAM
	342	*/
6d0f6bcf	343	#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (256 << 20) /* less than 256 MB */
adf22b66	344
6d0f6bcf	345	#define CONFIG_SYS_MPTPR 0x2800
adf22b66 HS	346
	347	/*-----------------------------------------------------------------------------
	348	* Address for Mode Register Set (MRS) command
	349	*-----------------------------------------------------------------------------
	350	*/
6d0f6bcf JCPV	351	#define CONFIG_SYS_MRS_OFFS 0x00000110
6d0f6bcf JCPV	352	#define CONFIG_SYS_PSRT 0x13
adf22b66	353
6d0f6bcf	354	#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) \|\
adf22b66 HS	355	BRx_PS_64 \|\
	356	BRx_MS_SDRAM_P \|\
	357	BRx_V)
	358
6d0f6bcf	359	#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1_LITTLE
adf22b66 HS	360
	361	/* SDRAM initialization values
	362	*/
6d0f6bcf	363	#define CONFIG_SYS_OR1_LITTLE ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) \|\
adf22b66 HS	364	ORxS_BPD_4 \|\
	365	ORxS_ROWST_PBI1_A7 \|\
	366	ORxS_NUMR_12)
	367
6d0f6bcf	368	#define CONFIG_SYS_PSDMR_LITTLE 0x004b36a3
a55d074d	369
6d0f6bcf	370	#define CONFIG_SYS_OR1_BIG ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) \|\
a55d074d HS	371	ORxS_BPD_4 \|\
	372	ORxS_ROWST_PBI1_A4 \|\
	373	ORxS_NUMR_12)
	374
6d0f6bcf	375	#define CONFIG_SYS_PSDMR_BIG 0x014f36a3
adf22b66 HS	376
	377	/* IO on CS4 initialization values
	378	*/
6d0f6bcf JCPV	379	#define CONFIG_SYS_IO_BASE 0xc0000000
6d0f6bcf JCPV	380	#define CONFIG_SYS_IO_SIZE 1
adf22b66	381
6d0f6bcf	382	#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_IO_BASE & BRx_BA_MSK) \|\
0b7c5639	383	BRx_PS_16 \| BRx_MS_GPCM_L \| BRx_V)
adf22b66	384
6d0f6bcf	385	#define CONFIG_SYS_OR4_PRELIM (0xfff80020)
adf22b66	386
6d0f6bcf	387	#define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */
adf22b66 HS	388
	389	/* pass open firmware flat tree */
	390	#define CONFIG_OF_LIBFDT 1
	391	#define CONFIG_OF_BOARD_SETUP 1
	392
adf22b66 HS	393	#define OF_TBCLK (bd->bi_busfreq / 4)
	394	#if defined(CONFIG_MUAS_DEV_BOARD)
	395	#define OF_STDOUT_PATH "/soc/cpm/serial@11a90"
	396	#else
	397	#define OF_STDOUT_PATH "/soc/cpm/serial@11a80"
	398	#endif
	399
	400	#endif /* __CONFIG_H */