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Commit | Line | Data |
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adf22b66 HS |
1 | /* |
2 | * (C) Copyright 2008 | |
3 | * Heiko Schocher, DENX Software Engineering, hs@denx.de. | |
4 | * | |
3765b3e7 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
adf22b66 HS |
6 | */ |
7 | ||
8 | #ifndef __CONFIG_H | |
9 | #define __CONFIG_H | |
10 | ||
11 | /* | |
12 | * High Level Configuration Options | |
13 | * (easy to change) | |
14 | */ | |
15 | ||
adf22b66 HS |
16 | #define CONFIG_MUAS3001 1 |
17 | ||
2ae18241 WD |
18 | #define CONFIG_SYS_TEXT_BASE 0xFF000000 |
19 | ||
adf22b66 HS |
20 | #define CONFIG_CPM2 1 /* Has a CPM2 */ |
21 | ||
22 | /* Do boardspecific init */ | |
23 | #define CONFIG_BOARD_EARLY_INIT_R 1 | |
24 | ||
4a02a2dc HS |
25 | /* enable Watchdog */ |
26 | #define CONFIG_WATCHDOG 1 | |
27 | ||
adf22b66 HS |
28 | /* |
29 | * Select serial console configuration | |
30 | * | |
31 | * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then | |
32 | * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 | |
33 | * for SCC). | |
34 | */ | |
35 | #define CONFIG_CONS_ON_SMC /* Console is on SMC */ | |
36 | #undef CONFIG_CONS_ON_SCC /* It's not on SCC */ | |
37 | #undef CONFIG_CONS_NONE /* It's not on external UART */ | |
38 | #if defined(CONFIG_MUAS_DEV_BOARD) | |
39 | #define CONFIG_CONS_INDEX 2 /* SMC2 is used for console */ | |
40 | #else | |
41 | #define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */ | |
42 | #endif | |
43 | ||
44 | /* | |
45 | * Select ethernet configuration | |
46 | * | |
47 | * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, | |
48 | * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for | |
49 | * SCC, 1-3 for FCC) | |
50 | * | |
51 | * If CONFIG_ETHER_NONE is defined, then either the ethernet routines | |
52 | * must be defined elsewhere (as for the console), or CONFIG_CMD_NET | |
53 | * must be unset. | |
54 | */ | |
55 | #undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */ | |
56 | #define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */ | |
57 | #undef CONFIG_ETHER_NONE /* No external Ethernet */ | |
58 | ||
59 | #define CONFIG_ETHER_INDEX 1 | |
60 | #define CONFIG_ETHER_ON_FCC1 | |
3ca55bce | 61 | #define CONFIG_HAS_ETH0 |
adf22b66 HS |
62 | #define FCC_ENET |
63 | ||
64 | /* | |
65 | * - Rx-CLK is CLK11 | |
66 | * - Tx-CLK is CLK12 | |
67 | */ | |
d4590da4 MF |
68 | # define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK12) |
69 | # define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK) | |
adf22b66 HS |
70 | /* |
71 | * - RAM for BD/Buffers is on the 60x Bus (see 28-13) | |
72 | */ | |
6d0f6bcf | 73 | # define CONFIG_SYS_CPMFCR_RAMTYPE (0) |
adf22b66 | 74 | /* know on local Bus */ |
6d0f6bcf | 75 | /* define CONFIG_SYS_CPMFCR_RAMTYPE (CPMFCR_DTB | CPMFCR_BDB) */ |
adf22b66 HS |
76 | /* |
77 | * - Enable Full Duplex in FSMR | |
78 | */ | |
6d0f6bcf | 79 | # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) |
adf22b66 HS |
80 | |
81 | #define CONFIG_MII /* MII PHY management */ | |
82 | #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ | |
6d0f6bcf | 83 | # define CONFIG_SYS_PHY_ADDR 1 |
adf22b66 HS |
84 | /* |
85 | * GPIO pins used for bit-banged MII communications | |
86 | */ | |
87 | #define MDIO_PORT 0 /* Port A */ | |
be225442 LCM |
88 | #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ |
89 | (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) | |
90 | #define MDC_DECLARE MDIO_DECLARE | |
91 | ||
adf22b66 | 92 | |
6d0f6bcf JCPV |
93 | #define CONFIG_SYS_MDIO_PIN 0x00200000 /* PA10 */ |
94 | #define CONFIG_SYS_MDC_PIN 0x00400000 /* PA9 */ | |
adf22b66 | 95 | |
6d0f6bcf JCPV |
96 | #define MDIO_ACTIVE (iop->pdir |= CONFIG_SYS_MDIO_PIN) |
97 | #define MDIO_TRISTATE (iop->pdir &= ~CONFIG_SYS_MDIO_PIN) | |
98 | #define MDIO_READ ((iop->pdat & CONFIG_SYS_MDIO_PIN) != 0) | |
adf22b66 | 99 | |
6d0f6bcf JCPV |
100 | #define MDIO(bit) if(bit) iop->pdat |= CONFIG_SYS_MDIO_PIN; \ |
101 | else iop->pdat &= ~CONFIG_SYS_MDIO_PIN | |
adf22b66 | 102 | |
6d0f6bcf JCPV |
103 | #define MDC(bit) if(bit) iop->pdat |= CONFIG_SYS_MDC_PIN; \ |
104 | else iop->pdat &= ~CONFIG_SYS_MDC_PIN | |
adf22b66 HS |
105 | |
106 | #define MIIDELAY udelay(1) | |
107 | ||
108 | #ifndef CONFIG_8260_CLKIN | |
109 | #define CONFIG_8260_CLKIN 66000000 /* in Hz */ | |
110 | #endif | |
111 | ||
112 | #define CONFIG_BAUDRATE 115200 | |
113 | ||
114 | /* | |
115 | * Command line configuration. | |
116 | */ | |
117 | #include <config_cmd_default.h> | |
118 | ||
245f6ef3 | 119 | #define CONFIG_CMD_DTT |
adf22b66 HS |
120 | #define CONFIG_CMD_ECHO |
121 | #define CONFIG_CMD_IMMAP | |
122 | #define CONFIG_CMD_MII | |
123 | #define CONFIG_CMD_PING | |
124 | #define CONFIG_CMD_I2C | |
125 | ||
126 | /* | |
127 | * Default environment settings | |
128 | */ | |
129 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
130 | "netdev=eth0\0" \ | |
131 | "u-boot_addr_r=100000\0" \ | |
132 | "kernel_addr_r=200000\0" \ | |
133 | "fdt_addr_r=400000\0" \ | |
134 | "rootpath=/opt/eldk/ppc_6xx\0" \ | |
135 | "u-boot=muas3001/u-boot.bin\0" \ | |
136 | "bootfile=muas3001/uImage\0" \ | |
137 | "fdt_file=muas3001/muas3001.dtb\0" \ | |
138 | "ramdisk_file=uRamdisk\0" \ | |
139 | "load=tftp ${u-boot_addr_r} ${u-boot}\0" \ | |
140 | "update=prot off ff000000 ff03ffff; era ff000000 ff03ffff; " \ | |
141 | "cp.b ${u-boot_addr_r} ff000000 ${filesize};" \ | |
142 | "prot on ff000000 ff03ffff\0" \ | |
143 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
144 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
145 | "nfsroot=${serverip}:${rootpath}\0" \ | |
146 | "addcons=setenv bootargs ${bootargs} console=ttyCPM0,${baudrate}\0" \ | |
147 | "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ | |
148 | "addip=setenv bootargs ${bootargs} " \ | |
149 | "ip=${ipaddr}:${serverip}:${gatewayip}:" \ | |
150 | "${netmask}:${hostname}:${netdev}:off panic=1\0" \ | |
151 | "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ | |
152 | "tftp ${fdt_addr_r} ${fdt_file}; run nfsargs addip addcons;" \ | |
153 | "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ | |
154 | "net_self=tftp ${kernel_addr_r} ${bootfile}; " \ | |
155 | "tftp ${fdt_addr_r} ${fdt_file}; " \ | |
156 | "tftp ${ramdisk_addr} ${ramdisk_file}; " \ | |
157 | "run ramargs addip; " \ | |
158 | "bootm ${kernel_addr_r} ${ramdisk_addr} ${fdt_addr_r}\0" \ | |
159 | "ramdisk_addr=ff210000\0" \ | |
160 | "kernel_addr=ff050000\0" \ | |
161 | "fdt_addr=ff200000\0" \ | |
162 | "flash_self=run ramargs addip addcons;bootm ${kernel_addr}" \ | |
163 | " ${ramdisk_addr} ${fdt_addr}\0" \ | |
164 | "updateramdisk=era ${ramdisk_addr} +1f0000;tftpb ${kernel_addr_r}" \ | |
165 | " ${ramdisk_file};" \ | |
166 | "cp.b ${kernel_addr_r} ${ramdisk_addr} ${filesize}\0" \ | |
167 | "updatekernel=era ${kernel_addr} +1b0000;tftpb ${kernel_addr_r}" \ | |
168 | " ${bootfile};" \ | |
169 | "cp.b ${kernel_addr_r} ${kernel_addr} ${filesize}\0" \ | |
170 | "updatefdt=era ${fdt_addr} +10000;tftpb ${fdt_addr_r} ${fdt_file};" \ | |
171 | "cp.b ${fdt_addr_r} ${fdt_addr} ${filesize}\0" \ | |
172 | "" | |
173 | ||
174 | #define CONFIG_BOOTCOMMAND "run net_nfs" | |
175 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
176 | ||
adf22b66 HS |
177 | /* |
178 | * Miscellaneous configurable options | |
179 | */ | |
6d0f6bcf | 180 | #define CONFIG_SYS_HUSH_PARSER |
6d0f6bcf | 181 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
adf22b66 | 182 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 183 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
adf22b66 | 184 | #else |
6d0f6bcf | 185 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
adf22b66 | 186 | #endif |
6d0f6bcf JCPV |
187 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
188 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
189 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
adf22b66 | 190 | |
6d0f6bcf JCPV |
191 | #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ |
192 | #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ | |
adf22b66 | 193 | |
6d0f6bcf | 194 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
adf22b66 | 195 | |
6d0f6bcf | 196 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
adf22b66 | 197 | |
6d0f6bcf JCPV |
198 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
199 | #define CONFIG_SYS_FLASH_BASE 0xFF000000 | |
200 | #define CONFIG_SYS_FLASH_SIZE 32 | |
201 | #define CONFIG_SYS_FLASH_CFI | |
adf22b66 | 202 | #define CONFIG_FLASH_CFI_DRIVER |
6d0f6bcf JCPV |
203 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ |
204 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ | |
adf22b66 | 205 | |
6d0f6bcf | 206 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } |
adf22b66 | 207 | |
14d0a02a | 208 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
6d0f6bcf | 209 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256KB for Monitor */ |
adf22b66 | 210 | |
5a1aceb0 | 211 | #define CONFIG_ENV_IS_IN_FLASH |
adf22b66 | 212 | |
5a1aceb0 | 213 | #ifdef CONFIG_ENV_IS_IN_FLASH |
0e8d1586 | 214 | #define CONFIG_ENV_SECT_SIZE 0x10000 |
6d0f6bcf | 215 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) |
5a1aceb0 | 216 | #endif /* CONFIG_ENV_IS_IN_FLASH */ |
adf22b66 HS |
217 | |
218 | /* | |
219 | * I2C Bus | |
220 | */ | |
221 | #define CONFIG_HARD_I2C 1 /* To enable I2C support */ | |
6d0f6bcf JCPV |
222 | #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ |
223 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
adf22b66 | 224 | |
6d0f6bcf | 225 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 |
245f6ef3 HS |
226 | /* I2C SYSMON (LM75, AD7414 is almost compatible) */ |
227 | #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ | |
228 | #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ | |
6d0f6bcf JCPV |
229 | #define CONFIG_SYS_DTT_MAX_TEMP 70 |
230 | #define CONFIG_SYS_DTT_LOW_TEMP -30 | |
231 | #define CONFIG_SYS_DTT_HYSTERESIS 3 | |
245f6ef3 | 232 | |
6d0f6bcf JCPV |
233 | #define CONFIG_SYS_IMMR 0xF0000000 |
234 | #define CONFIG_SYS_DEFAULT_IMMR 0x0F010000 | |
adf22b66 | 235 | |
6d0f6bcf | 236 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
553f0982 | 237 | #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */ |
25ddd1fb | 238 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 239 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
adf22b66 HS |
240 | |
241 | /* Hard reset configuration word */ | |
6d0f6bcf | 242 | #define CONFIG_SYS_HRCW_MASTER 0x0E028200 /* BPS=11 CIP=1 ISB=010 BMS=1 */ |
adf22b66 HS |
243 | |
244 | /* No slaves */ | |
6d0f6bcf JCPV |
245 | #define CONFIG_SYS_HRCW_SLAVE1 0 |
246 | #define CONFIG_SYS_HRCW_SLAVE2 0 | |
247 | #define CONFIG_SYS_HRCW_SLAVE3 0 | |
248 | #define CONFIG_SYS_HRCW_SLAVE4 0 | |
249 | #define CONFIG_SYS_HRCW_SLAVE5 0 | |
250 | #define CONFIG_SYS_HRCW_SLAVE6 0 | |
251 | #define CONFIG_SYS_HRCW_SLAVE7 0 | |
adf22b66 | 252 | |
6d0f6bcf JCPV |
253 | #define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */ |
254 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
adf22b66 | 255 | |
6d0f6bcf | 256 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */ |
adf22b66 | 257 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 258 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
adf22b66 HS |
259 | #endif |
260 | ||
6d0f6bcf JCPV |
261 | #define CONFIG_SYS_HID0_INIT 0 |
262 | #define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE) | |
adf22b66 | 263 | |
6d0f6bcf | 264 | #define CONFIG_SYS_HID2 0 |
adf22b66 | 265 | |
6d0f6bcf JCPV |
266 | #define CONFIG_SYS_SIUMCR 0x00200000 |
267 | #define CONFIG_SYS_BCR 0x004c0000 | |
268 | #define CONFIG_SYS_SCCR 0x0 | |
adf22b66 | 269 | |
4a02a2dc HS |
270 | /*----------------------------------------------------------------------- |
271 | * SYPCR - System Protection Control 4-35 | |
272 | * SYPCR can only be written once after reset! | |
273 | *----------------------------------------------------------------------- | |
274 | * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable | |
275 | */ | |
276 | #if defined(CONFIG_WATCHDOG) | |
6d0f6bcf | 277 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ |
4a02a2dc HS |
278 | SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) |
279 | #else | |
6d0f6bcf | 280 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ |
4a02a2dc HS |
281 | SYPCR_SWRI|SYPCR_SWP) |
282 | #endif /* CONFIG_WATCHDOG */ | |
283 | ||
adf22b66 HS |
284 | /*----------------------------------------------------------------------- |
285 | * RMR - Reset Mode Register 5-5 | |
286 | *----------------------------------------------------------------------- | |
287 | * turn on Checkstop Reset Enable | |
288 | */ | |
6d0f6bcf | 289 | #define CONFIG_SYS_RMR 0 |
adf22b66 HS |
290 | |
291 | /*----------------------------------------------------------------------- | |
292 | * TMCNTSC - Time Counter Status and Control 4-40 | |
293 | *----------------------------------------------------------------------- | |
294 | * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, | |
295 | * and enable Time Counter | |
296 | */ | |
6d0f6bcf | 297 | #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) |
adf22b66 HS |
298 | |
299 | /*----------------------------------------------------------------------- | |
300 | * PISCR - Periodic Interrupt Status and Control 4-42 | |
301 | *----------------------------------------------------------------------- | |
302 | * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable | |
303 | * Periodic timer | |
304 | */ | |
6d0f6bcf | 305 | #define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) |
adf22b66 HS |
306 | |
307 | /*----------------------------------------------------------------------- | |
308 | * RCCR - RISC Controller Configuration 13-7 | |
309 | *----------------------------------------------------------------------- | |
310 | */ | |
6d0f6bcf | 311 | #define CONFIG_SYS_RCCR 0 |
adf22b66 HS |
312 | |
313 | /* | |
314 | * Init Memory Controller: | |
315 | * | |
316 | * Bank Bus Machine PortSz Device | |
317 | * ---- --- ------- ------ ------ | |
318 | * 0 60x GPCM 32 bit FLASH | |
319 | * 1 60x SDRAM 64 bit SDRAM | |
320 | * 4 60x GPCM 16 bit I/O Ctrl | |
321 | * | |
322 | */ | |
323 | /* Bank 0 - FLASH | |
324 | */ | |
6d0f6bcf | 325 | #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ |
adf22b66 HS |
326 | BRx_PS_32 |\ |
327 | BRx_MS_GPCM_P |\ | |
328 | BRx_V) | |
329 | ||
6d0f6bcf | 330 | #define CONFIG_SYS_OR0_PRELIM (0xff000020) |
adf22b66 HS |
331 | |
332 | /* Bank 1 - 60x bus SDRAM | |
333 | */ | |
6d0f6bcf | 334 | #define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (256 << 20) /* less than 256 MB */ |
adf22b66 | 335 | |
6d0f6bcf | 336 | #define CONFIG_SYS_MPTPR 0x2800 |
adf22b66 HS |
337 | |
338 | /*----------------------------------------------------------------------------- | |
339 | * Address for Mode Register Set (MRS) command | |
340 | *----------------------------------------------------------------------------- | |
341 | */ | |
6d0f6bcf JCPV |
342 | #define CONFIG_SYS_MRS_OFFS 0x00000110 |
343 | #define CONFIG_SYS_PSRT 0x13 | |
adf22b66 | 344 | |
6d0f6bcf | 345 | #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\ |
adf22b66 HS |
346 | BRx_PS_64 |\ |
347 | BRx_MS_SDRAM_P |\ | |
348 | BRx_V) | |
349 | ||
6d0f6bcf | 350 | #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1_LITTLE |
adf22b66 HS |
351 | |
352 | /* SDRAM initialization values | |
353 | */ | |
6d0f6bcf | 354 | #define CONFIG_SYS_OR1_LITTLE ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ |
adf22b66 HS |
355 | ORxS_BPD_4 |\ |
356 | ORxS_ROWST_PBI1_A7 |\ | |
357 | ORxS_NUMR_12) | |
358 | ||
6d0f6bcf | 359 | #define CONFIG_SYS_PSDMR_LITTLE 0x004b36a3 |
a55d074d | 360 | |
6d0f6bcf | 361 | #define CONFIG_SYS_OR1_BIG ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ |
a55d074d HS |
362 | ORxS_BPD_4 |\ |
363 | ORxS_ROWST_PBI1_A4 |\ | |
364 | ORxS_NUMR_12) | |
365 | ||
6d0f6bcf | 366 | #define CONFIG_SYS_PSDMR_BIG 0x014f36a3 |
adf22b66 HS |
367 | |
368 | /* IO on CS4 initialization values | |
369 | */ | |
6d0f6bcf JCPV |
370 | #define CONFIG_SYS_IO_BASE 0xc0000000 |
371 | #define CONFIG_SYS_IO_SIZE 1 | |
adf22b66 | 372 | |
6d0f6bcf | 373 | #define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_IO_BASE & BRx_BA_MSK) |\ |
0b7c5639 | 374 | BRx_PS_16 | BRx_MS_GPCM_L | BRx_V) |
adf22b66 | 375 | |
6d0f6bcf | 376 | #define CONFIG_SYS_OR4_PRELIM (0xfff80020) |
adf22b66 | 377 | |
6d0f6bcf | 378 | #define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */ |
adf22b66 HS |
379 | |
380 | /* pass open firmware flat tree */ | |
381 | #define CONFIG_OF_LIBFDT 1 | |
382 | #define CONFIG_OF_BOARD_SETUP 1 | |
383 | ||
adf22b66 HS |
384 | #define OF_TBCLK (bd->bi_busfreq / 4) |
385 | #if defined(CONFIG_MUAS_DEV_BOARD) | |
386 | #define OF_STDOUT_PATH "/soc/cpm/serial@11a90" | |
387 | #else | |
388 | #define OF_STDOUT_PATH "/soc/cpm/serial@11a80" | |
389 | #endif | |
390 | ||
391 | #endif /* __CONFIG_H */ |