[people/ms/u-boot.git] / include / configs / mucmc52.h

/*
 * (C) Copyright 2008-2009
 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
 *
 * (C) Copyright 2003-2005
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define	CONFIG_MUCMC52		1	/* MUCMC52 board	*/
#define	CONFIG_HOSTNAME		mucmc52

#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE	0xFFF00000
#endif

#include "manroland/common.h"
#include "manroland/mpc5200-common.h"

#define	CONFIG_LAST_STAGE_INIT
/*
 * Serial console configuration
 */
#define	CONFIG_BAUDRATE		38400	/* ... at 38400 bps	*/

#define	CONFIG_CMD_PCI

/*
 * Flash configuration
 */
#define	CONFIG_SYS_MAX_FLASH_SECT	67

/*
 * Environment settings
 */
#define	CONFIG_ENV_SECT_SIZE	0x20000

/*
 * Memory map
 */
#define	CONFIG_SYS_STATUS1_BASE	0x80600200
#define	CONFIG_SYS_STATUS2_BASE	0x80600300
#define	CONFIG_SYS_PMI_UNI_BASE	0x80800000
#define	CONFIG_SYS_PMI_BROAD_BASE	0x80810000

/*
 * GPIO configuration
 */
#define	CONFIG_SYS_GPS_PORT_CONFIG	0x8D550644

#define	CONFIG_SYS_MEMTEST_START	0x00100000
#define	CONFIG_SYS_MEMTEST_END		0x00f00000

#define	CONFIG_SYS_LOAD_ADDR		0x100000

#define	CONFIG_SYS_BOOTCS_CFG		0x0004FB00

/* 8Mbit SRAM @0x80100000 */
#define	CONFIG_SYS_CS1_SIZE		0x00100000
#define	CONFIG_SYS_CS1_CFG		0x00019B00

#define CONFIG_SYS_SRAM_SIZE		CONFIG_SYS_CS1_SIZE

/* FRAM 32Kbyte @0x80700000 */
#define	CONFIG_SYS_CS2_START		0x80700000
#define	CONFIG_SYS_CS2_SIZE		0x00008000
#define	CONFIG_SYS_CS2_CFG		0x00019800

/* Display H1, Status Inputs, EPLD @0x80600000 */
#define	CONFIG_SYS_CS3_START		0x80600000
#define	CONFIG_SYS_CS3_SIZE		0x00100000
#define	CONFIG_SYS_CS3_CFG		0x00019800

/* PMI Unicast 32Kbyte @0x80800000 */
#define	CONFIG_SYS_CS6_START		CONFIG_SYS_PMI_UNI_BASE
#define	CONFIG_SYS_CS6_SIZE		0x00008000
#define	CONFIG_SYS_CS6_CFG		0xFFFFF930

/* PMI Broadcast 32Kbyte @0x80810000 */
#define	CONFIG_SYS_CS7_START		CONFIG_SYS_PMI_BROAD_BASE
#define	CONFIG_SYS_CS7_SIZE		0x00008000
#define	CONFIG_SYS_CS7_CFG		0xFF00F930

/*-----------------------------------------------------------------------
 * IDE/ATA stuff Supports IDE harddisk
 *-----------------------------------------------------------------------
 */
#define	CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 2 drives per IDE bus	*/

/*
 * PCI Mapping:
 * 0x40000000 - 0x4fffffff - PCI Memory
 * 0x50000000 - 0x50ffffff - PCI IO Space
 */
#define	CONFIG_PCI		1
#define	CONFIG_PCI_PNP		1
#define	CONFIG_PCI_SCAN_SHOW	1
#define	CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1

#define	CONFIG_PCI_MEM_BUS	0x40000000
#define	CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
#define	CONFIG_PCI_MEM_SIZE	0x10000000

#define	CONFIG_PCI_IO_BUS	0x50000000
#define	CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
#define	CONFIG_PCI_IO_SIZE	0x01000000

#define	CONFIG_SYS_ISA_IO		CONFIG_PCI_IO_BUS

/*---------------------------------------------------------------------*/
/* Display addresses						       */
/*---------------------------------------------------------------------*/

#define	CONFIG_SYS_DISP_CHR_RAM	(CONFIG_SYS_DISPLAY_BASE + 0x38)
#define	CONFIG_SYS_DISP_CWORD		(CONFIG_SYS_DISPLAY_BASE + 0x30)

#endif /* __CONFIG_H */
Commit	Line	Data
258c37b1	1	/*
7f625fc6	2	* (C) Copyright 2008-2009
258c37b1 HS	3	* Heiko Schocher, DENX Software Engineering, hs@denx.de.
	4	*
	5	* (C) Copyright 2003-2005
	6	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	7	*
3765b3e7	8	* SPDX-License-Identifier: GPL-2.0+
258c37b1 HS	9	*/
	10
	11	#ifndef __CONFIG_H
	12	#define __CONFIG_H
	13
	14	/*
	15	* High Level Configuration Options
	16	* (easy to change)
	17	*/
	18
7f625fc6 HS	19	#define CONFIG_MUCMC52 1 /* MUCMC52 board */
7f625fc6 HS	20	#define CONFIG_HOSTNAME mucmc52
258c37b1	21
2ae18241 WD	22	#ifndef CONFIG_SYS_TEXT_BASE
	23	#define CONFIG_SYS_TEXT_BASE 0xFFF00000
	24	#endif
	25
7f625fc6 HS	26	#include "manroland/common.h"
7f625fc6 HS	27	#include "manroland/mpc5200-common.h"
258c37b1 HS	28
258c37b1 HS	29	#define CONFIG_LAST_STAGE_INIT
258c37b1 HS	30	/*
	31	* Serial console configuration
	32	*/
258c37b1	33	#define CONFIG_BAUDRATE 38400 /* ... at 38400 bps */
258c37b1	34
258c37b1	35	#define CONFIG_CMD_PCI
258c37b1 HS	36
	37	/*
	38	* Flash configuration
	39	*/
7f625fc6	40	#define CONFIG_SYS_MAX_FLASH_SECT 67
258c37b1 HS	41
	42	/*
	43	* Environment settings
	44	*/
0e8d1586	45	#define CONFIG_ENV_SECT_SIZE 0x20000
258c37b1 HS	46
	47	/*
	48	* Memory map
	49	*/
6d0f6bcf JCPV	50	#define CONFIG_SYS_STATUS1_BASE 0x80600200
	51	#define CONFIG_SYS_STATUS2_BASE 0x80600300
	52	#define CONFIG_SYS_PMI_UNI_BASE 0x80800000
	53	#define CONFIG_SYS_PMI_BROAD_BASE 0x80810000
258c37b1	54
258c37b1 HS	55	/*
	56	* GPIO configuration
	57	*/
6d0f6bcf	58	#define CONFIG_SYS_GPS_PORT_CONFIG 0x8D550644
258c37b1	59
7f625fc6 HS	60	#define CONFIG_SYS_MEMTEST_START 0x00100000
7f625fc6 HS	61	#define CONFIG_SYS_MEMTEST_END 0x00f00000
258c37b1	62
7f625fc6	63	#define CONFIG_SYS_LOAD_ADDR 0x100000
258c37b1	64
6d0f6bcf	65	#define CONFIG_SYS_BOOTCS_CFG 0x0004FB00
258c37b1 HS	66
258c37b1 HS	67	/* 8Mbit SRAM @0x80100000 */
6d0f6bcf JCPV	68	#define CONFIG_SYS_CS1_SIZE 0x00100000
6d0f6bcf JCPV	69	#define CONFIG_SYS_CS1_CFG 0x00019B00
258c37b1	70
d1831c5e HS	71	#define CONFIG_SYS_SRAM_SIZE CONFIG_SYS_CS1_SIZE
d1831c5e HS	72
258c37b1	73	/* FRAM 32Kbyte @0x80700000 */
6d0f6bcf JCPV	74	#define CONFIG_SYS_CS2_START 0x80700000
	75	#define CONFIG_SYS_CS2_SIZE 0x00008000
	76	#define CONFIG_SYS_CS2_CFG 0x00019800
258c37b1 HS	77
258c37b1 HS	78	/* Display H1, Status Inputs, EPLD @0x80600000 */
6d0f6bcf JCPV	79	#define CONFIG_SYS_CS3_START 0x80600000
	80	#define CONFIG_SYS_CS3_SIZE 0x00100000
	81	#define CONFIG_SYS_CS3_CFG 0x00019800
258c37b1 HS	82
258c37b1 HS	83	/* PMI Unicast 32Kbyte @0x80800000 */
6d0f6bcf JCPV	84	#define CONFIG_SYS_CS6_START CONFIG_SYS_PMI_UNI_BASE
	85	#define CONFIG_SYS_CS6_SIZE 0x00008000
	86	#define CONFIG_SYS_CS6_CFG 0xFFFFF930
258c37b1 HS	87
258c37b1 HS	88	/* PMI Broadcast 32Kbyte @0x80810000 */
6d0f6bcf JCPV	89	#define CONFIG_SYS_CS7_START CONFIG_SYS_PMI_BROAD_BASE
	90	#define CONFIG_SYS_CS7_SIZE 0x00008000
	91	#define CONFIG_SYS_CS7_CFG 0xFF00F930
258c37b1	92
258c37b1 HS	93	/*-----------------------------------------------------------------------
	94	* IDE/ATA stuff Supports IDE harddisk
	95	*-----------------------------------------------------------------------
	96	*/
6d0f6bcf	97	#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 2 drives per IDE bus */
258c37b1	98
258c37b1 HS	99	/*
	100	* PCI Mapping:
	101	* 0x40000000 - 0x4fffffff - PCI Memory
	102	* 0x50000000 - 0x50ffffff - PCI IO Space
	103	*/
	104	#define CONFIG_PCI 1
	105	#define CONFIG_PCI_PNP 1
	106	#define CONFIG_PCI_SCAN_SHOW 1
	107	#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
	108
	109	#define CONFIG_PCI_MEM_BUS 0x40000000
	110	#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
	111	#define CONFIG_PCI_MEM_SIZE 0x10000000
	112
	113	#define CONFIG_PCI_IO_BUS 0x50000000
	114	#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
	115	#define CONFIG_PCI_IO_SIZE 0x01000000
	116
6d0f6bcf	117	#define CONFIG_SYS_ISA_IO CONFIG_PCI_IO_BUS
258c37b1 HS	118
	119	/---------------------------------------------------------------------/
	120	/* Display addresses */
	121	/---------------------------------------------------------------------/
	122
6d0f6bcf JCPV	123	#define CONFIG_SYS_DISP_CHR_RAM (CONFIG_SYS_DISPLAY_BASE + 0x38)
6d0f6bcf JCPV	124	#define CONFIG_SYS_DISP_CWORD (CONFIG_SYS_DISPLAY_BASE + 0x30)
258c37b1 HS	125
258c37b1 HS	126	#endif /* __CONFIG_H */