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5fb2b234 HS |
1 | /* |
2 | * (C) Copyright 2007 | |
3 | * Heiko Schocher, DENX Software Engineering, hs@denx.de. | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
5fb2b234 HS |
6 | */ |
7 | ||
8 | #ifndef __CONFIG_H | |
9 | #define __CONFIG_H | |
10 | /* | |
11 | * High Level Configuration Options | |
12 | * (easy to change) | |
13 | */ | |
14 | #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ | |
15 | #define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ | |
16 | #define CONFIG_MPC5200_DDR 1 /* (with DDR-SDRAM) */ | |
17 | #define CONFIG_MUNICES 1 /* ... on MUNICes board */ | |
2ae18241 WD |
18 | |
19 | #ifndef CONFIG_SYS_TEXT_BASE | |
20 | #define CONFIG_SYS_TEXT_BASE 0xFFF00000 | |
21 | #endif | |
22 | ||
6d0f6bcf | 23 | #define CONFIG_SYS_MPC5XXX_CLKIN 33333333 /* ... running at 33.333333MHz */ |
6d0f6bcf | 24 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ |
31d82672 | 25 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
5fb2b234 HS |
26 | |
27 | /* | |
28 | * Command line configuration. | |
29 | */ | |
30 | #include <config_cmd_default.h> | |
31 | ||
32 | #define CONFIG_CMD_ASKENV | |
33 | #define CONFIG_CMD_ELF | |
34 | #define CONFIG_CMD_IMMAP | |
35 | #define CONFIG_CMD_NET | |
36 | #define CONFIG_CMD_PING | |
37 | #define CONFIG_CMD_REGINFO | |
38 | ||
1b769881 | 39 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 40 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
5fb2b234 HS |
41 | #endif |
42 | ||
43 | /* | |
44 | * Serial console configuration | |
45 | */ | |
46 | #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ | |
47 | #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ | |
6d0f6bcf | 48 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
5fb2b234 HS |
49 | |
50 | #define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */ | |
51 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
52 | #undef CONFIG_BOOTARGS | |
53 | ||
54 | #define CONFIG_PREBOOT "echo;" \ | |
55 | "echo Type \"run net_nfs\" to load Kernel over TFTP and to mount root filesystem over NFS;" \ | |
56 | "echo" | |
57 | ||
58 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
59 | "netdev=eth0\0" \ | |
60 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
61 | "nfsroot=$(serverip):$(rootpath)\0" \ | |
62 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
63 | "addip=setenv bootargs $(bootargs) " \ | |
64 | "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ | |
65 | ":$(hostname):$(netdev):off panic=5\0" \ | |
66 | "flash_nfs=run nfsargs addip;" \ | |
67 | "bootm $(kernel_addr)\0" \ | |
68 | "flash_self=run ramargs addip;" \ | |
69 | "bootm $(kernel_addr) $(ramdisk_addr)\0" \ | |
70 | "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \ | |
71 | "rootpath=/opt/eldk/ppc_6xx\0" \ | |
72 | "bootfile=/tftpboot/munices/u-boot.bin\0" \ | |
73 | "update=tftpboot 200000 ${bootfile};protect off fff00000 fff3ffff;" \ | |
74 | "erase fff00000 fff3ffff; cp.b 200000 FFF00000 ${filesize}\0" \ | |
75 | "" | |
76 | #define CONFIG_BOOTCOMMAND "run net_nfs" | |
77 | ||
78 | /* | |
79 | * IPB Bus clocking configuration. | |
80 | */ | |
6d0f6bcf JCPV |
81 | #define CONFIG_SYS_IPBSPEED_133 /* define for 133MHz speed */ |
82 | #if defined(CONFIG_SYS_IPBSPEED_133) | |
5fb2b234 HS |
83 | /* |
84 | * PCI Bus clocking configuration | |
85 | * | |
86 | * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if | |
6d0f6bcf | 87 | * CONFIG_SYS_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't |
5fb2b234 HS |
88 | * been tested with a IPB Bus Clock of 66 MHz. |
89 | */ | |
6d0f6bcf | 90 | #define CONFIG_SYS_PCISPEED_66 /* define for 66MHz speed */ |
5fb2b234 | 91 | #else |
6d0f6bcf | 92 | #undef CONFIG_SYS_PCISPEED_66 /* for 33MHz speed */ |
5fb2b234 HS |
93 | #endif |
94 | ||
95 | /* | |
96 | * Memory map | |
97 | */ | |
6d0f6bcf | 98 | #define CONFIG_SYS_MBAR 0xF0000000 /* MBAR hast to be switched by other bootloader or debugger config */ |
fa05664c | 99 | |
6d0f6bcf JCPV |
100 | #define CONFIG_SYS_DEFAULT_MBAR 0x80000000 |
101 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 | |
5fb2b234 | 102 | /* Use SRAM until RAM will be available */ |
6d0f6bcf | 103 | #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM |
553f0982 | 104 | #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */ |
25ddd1fb | 105 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf JCPV |
106 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
107 | ||
14d0a02a | 108 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
6d0f6bcf JCPV |
109 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
110 | # define CONFIG_SYS_RAMBOOT 1 | |
5fb2b234 HS |
111 | #endif |
112 | ||
6d0f6bcf JCPV |
113 | #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ |
114 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
115 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
5fb2b234 HS |
116 | |
117 | /* | |
118 | * Flash configuration | |
119 | */ | |
6d0f6bcf JCPV |
120 | #define CONFIG_SYS_FLASH_BASE 0xFF000000 |
121 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ | |
00b1883a | 122 | #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ |
6d0f6bcf JCPV |
123 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } |
124 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
125 | #define CONFIG_SYS_FLASH_SIZE 0x01000000 /* 16 MByte */ | |
126 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ | |
127 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks (= chip selects) */ | |
128 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */ | |
5fb2b234 HS |
129 | |
130 | /* | |
131 | * Chip selects configuration | |
132 | */ | |
133 | /* Boot Chipselect */ | |
6d0f6bcf JCPV |
134 | #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE |
135 | #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE | |
136 | #define CONFIG_SYS_BOOTCS_CFG 0x00047800 | |
5fb2b234 HS |
137 | |
138 | /* | |
139 | * Environment settings | |
140 | */ | |
5a1aceb0 | 141 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 | 142 | #define CONFIG_ENV_OFFSET 0x40000 |
14d0a02a | 143 | #define CONFIG_ENV_ADDR (CONFIG_SYS_TEXT_BASE + CONFIG_ENV_OFFSET) |
0e8d1586 JCPV |
144 | #define CONFIG_ENV_SECT_SIZE 0x20000 |
145 | #define CONFIG_ENV_SIZE 0x4000 | |
146 | #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE) | |
14d0a02a | 147 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_TEXT_BASE + CONFIG_ENV_OFFSET_REDUND) |
0e8d1586 | 148 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) |
5fb2b234 HS |
149 | #define CONFIG_ENV_OVERWRITE 1 |
150 | ||
151 | /* | |
152 | * Ethernet configuration | |
153 | */ | |
154 | #define CONFIG_MPC5xxx_FEC 1 | |
86321fc1 | 155 | #define CONFIG_MPC5xxx_FEC_MII100 |
5fb2b234 HS |
156 | #define CONFIG_PHY_ADDR 0x01 |
157 | #define CONFIG_MII 1 | |
158 | ||
159 | /* | |
160 | * GPIO configuration | |
161 | */ | |
6d0f6bcf | 162 | #define CONFIG_SYS_GPS_PORT_CONFIG 0x00058044 /* PSC1=UART, PSC2=UART ; Ether=100MBit with MD |
5fb2b234 HS |
163 | no PCI */ |
164 | ||
165 | /* | |
166 | * Miscellaneous configurable options | |
167 | */ | |
6d0f6bcf JCPV |
168 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
169 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
170 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
171 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
172 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
173 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
5fb2b234 | 174 | |
6d0f6bcf JCPV |
175 | #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ |
176 | #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ | |
5fb2b234 | 177 | |
6d0f6bcf JCPV |
178 | #define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */ |
179 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
5fb2b234 HS |
180 | |
181 | #define CONFIG_DISPLAY_BOARDINFO 1 | |
182 | #define CONFIG_CMDLINE_EDITING 1 | |
183 | ||
184 | /* | |
185 | * Various low-level settings | |
186 | */ | |
6d0f6bcf JCPV |
187 | #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI |
188 | #define CONFIG_SYS_HID0_FINAL HID0_ICE | |
5fb2b234 | 189 | |
6d0f6bcf JCPV |
190 | #define CONFIG_SYS_CS_BURST 0x00000000 |
191 | #define CONFIG_SYS_CS_DEADCYCLE 0x33333333 | |
192 | #define CONFIG_SYS_RESET_ADDRESS 0xff000000 | |
5fb2b234 HS |
193 | |
194 | /* pass open firmware flat tree */ | |
195 | #define CONFIG_OF_LIBFDT 1 | |
196 | #define CONFIG_OF_BOARD_SETUP 1 | |
197 | ||
198 | #define OF_CPU "PowerPC,5200@0" | |
199 | #define OF_TBCLK (bd->bi_busfreq / 4) | |
200 | #define OF_SOC "soc5200@f0000000" | |
201 | #define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" | |
202 | ||
203 | #endif /* __CONFIG_H */ |