[people/ms/u-boot.git] / include / configs / munices.h

/*
 * (C) Copyright 2007
 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H
/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_MPC5200		1	/* This is an MPC5200 CPU */
#define CONFIG_MPC5200_DDR	1	/* (with DDR-SDRAM) */
#define CONFIG_MUNICES		1	/* ... on MUNICes board */

#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE	0xFFF00000
#endif

#define CONFIG_SYS_MPC5XXX_CLKIN	33333333 /* ... running at 33.333333MHz */
#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
#define CONFIG_HIGH_BATS	1	/* High BATs supported */

/*
 * Command line configuration.
 */
#define CONFIG_CMD_IMMAP
#define CONFIG_CMD_REGINFO

#if defined(CONFIG_CMD_KGDB)
#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif

/*
 * Serial console configuration
 */
#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }

#define	CONFIG_TIMESTAMP	1	/* Print image info with timestamp */
#undef	CONFIG_BOOTARGS

#define CONFIG_PREBOOT	"echo;"	\
	"echo Type \"run net_nfs\" to load Kernel over TFTP and to mount root filesystem over NFS;" \
	"echo"

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=$(serverip):$(rootpath)\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs $(bootargs) "				\
		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"	\
		":$(hostname):$(netdev):off panic=5\0"			\
	"flash_nfs=run nfsargs addip;"					\
		"bootm $(kernel_addr)\0"				\
	"flash_self=run ramargs addip;"					\
		"bootm $(kernel_addr) $(ramdisk_addr)\0"		\
	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0"	\
	"rootpath=/opt/eldk/ppc_6xx\0"					\
	"bootfile=/tftpboot/munices/u-boot.bin\0"			\
	"update=tftpboot 200000 ${bootfile};protect off fff00000 fff3ffff;" \
	"erase fff00000 fff3ffff; cp.b 200000 FFF00000 ${filesize}\0"	\
	""
#define CONFIG_BOOTCOMMAND	"run net_nfs"

/*
 * IPB Bus clocking configuration.
 */
#define  CONFIG_SYS_IPBSPEED_133		/* define for 133MHz speed */
#if defined(CONFIG_SYS_IPBSPEED_133)
/*
 * PCI Bus clocking configuration
 *
 * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
 * CONFIG_SYS_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
 * been tested with a IPB Bus Clock of 66 MHz.
 */
#define CONFIG_SYS_PCISPEED_66		/* define for 66MHz speed */
#else
#undef CONFIG_SYS_PCISPEED_66			/* for 33MHz speed */
#endif

/*
 * Memory map
 */
#define CONFIG_SYS_MBAR		0xF0000000 /* MBAR hast to be switched by other bootloader or debugger config  */

#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
#define CONFIG_SYS_SDRAM_BASE		0x00000000
/* Use SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE	/* Size of used area in DPRAM */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#   define CONFIG_SYS_RAMBOOT		1
#endif

#define CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*
 * Flash configuration
 */
#define CONFIG_SYS_FLASH_BASE		0xFF000000
#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
#define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_SIZE		0x01000000 /* 16 MByte */
#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */
#define CONFIG_SYS_MAX_FLASH_BANKS	1	 /* max num of flash banks (= chip selects) */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	/* not supported yet for AMD */

/*
 * Chip selects configuration
 */
/* Boot Chipselect */
#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_BOOTCS_CFG		0x00047800

/*
 * Environment settings
 */
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_OFFSET		0x40000
#define CONFIG_ENV_ADDR		(CONFIG_SYS_TEXT_BASE + CONFIG_ENV_OFFSET)
#define CONFIG_ENV_SECT_SIZE	0x20000
#define CONFIG_ENV_SIZE		0x4000
#define CONFIG_ENV_OFFSET_REDUND   (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_SYS_TEXT_BASE + CONFIG_ENV_OFFSET_REDUND)
#define CONFIG_ENV_SIZE_REDUND     (CONFIG_ENV_SIZE)
#define CONFIG_ENV_OVERWRITE	1

/*
 * Ethernet configuration
 */
#define CONFIG_MPC5xxx_FEC	1
#define CONFIG_MPC5xxx_FEC_MII100
#define CONFIG_PHY_ADDR		0x01
#define CONFIG_MII		1

/*
 * GPIO configuration
 */
#define CONFIG_SYS_GPS_PORT_CONFIG	0x00058044 /* PSC1=UART, PSC2=UART ; Ether=100MBit with MD
						no PCI */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/

#define CONFIG_SYS_LOAD_ADDR		0x200000	/* default load address */

#define CONFIG_CMDLINE_EDITING  1

/*
 * Various low-level settings
 */
#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL		HID0_ICE

#define CONFIG_SYS_CS_BURST		0x00000000
#define CONFIG_SYS_CS_DEADCYCLE	0x33333333
#define CONFIG_SYS_RESET_ADDRESS	0xff000000

#define OF_CPU			"PowerPC,5200@0"
#define OF_TBCLK		(bd->bi_busfreq / 4)
#define OF_SOC                  "soc5200@f0000000"
#define OF_STDOUT_PATH		"/soc5200@f0000000/serial@2000"

#endif /* __CONFIG_H */
Commit	Line	Data
5fb2b234 HS	1	/*
	2	* (C) Copyright 2007
	3	* Heiko Schocher, DENX Software Engineering, hs@denx.de.
	4	*
3765b3e7	5	* SPDX-License-Identifier: GPL-2.0+
5fb2b234 HS	6	*/
	7
	8	#ifndef __CONFIG_H
	9	#define __CONFIG_H
	10	/*
	11	* High Level Configuration Options
	12	* (easy to change)
	13	*/
b2a6dfe4	14	#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
5fb2b234 HS	15	#define CONFIG_MPC5200_DDR 1 /* (with DDR-SDRAM) */
5fb2b234 HS	16	#define CONFIG_MUNICES 1 /* ... on MUNICes board */
2ae18241 WD	17
	18	#ifndef CONFIG_SYS_TEXT_BASE
	19	#define CONFIG_SYS_TEXT_BASE 0xFFF00000
	20	#endif
	21
6d0f6bcf	22	#define CONFIG_SYS_MPC5XXX_CLKIN 33333333 /* ... running at 33.333333MHz */
6d0f6bcf	23	#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
31d82672	24	#define CONFIG_HIGH_BATS 1 /* High BATs supported */
5fb2b234 HS	25
	26	/*
	27	* Command line configuration.
	28	*/
5fb2b234	29	#define CONFIG_CMD_IMMAP
5fb2b234 HS	30	#define CONFIG_CMD_REGINFO
5fb2b234 HS	31
1b769881	32	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	33	# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
5fb2b234 HS	34	#endif
	35
	36	/*
	37	* Serial console configuration
	38	*/
	39	#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
	40	#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
6d0f6bcf	41	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
5fb2b234 HS	42
5fb2b234 HS	43	#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
5fb2b234 HS	44	#undef CONFIG_BOOTARGS
	45
	46	#define CONFIG_PREBOOT "echo;" \
	47	"echo Type \"run net_nfs\" to load Kernel over TFTP and to mount root filesystem over NFS;" \
	48	"echo"
	49
	50	#define CONFIG_EXTRA_ENV_SETTINGS \
	51	"netdev=eth0\0" \
	52	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	53	"nfsroot=$(serverip):$(rootpath)\0" \
	54	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	55	"addip=setenv bootargs $(bootargs) " \
	56	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
	57	":$(hostname):$(netdev):off panic=5\0" \
	58	"flash_nfs=run nfsargs addip;" \
	59	"bootm $(kernel_addr)\0" \
	60	"flash_self=run ramargs addip;" \
	61	"bootm $(kernel_addr) $(ramdisk_addr)\0" \
	62	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
	63	"rootpath=/opt/eldk/ppc_6xx\0" \
	64	"bootfile=/tftpboot/munices/u-boot.bin\0" \
	65	"update=tftpboot 200000 ${bootfile};protect off fff00000 fff3ffff;" \
	66	"erase fff00000 fff3ffff; cp.b 200000 FFF00000 ${filesize}\0" \
	67	""
	68	#define CONFIG_BOOTCOMMAND "run net_nfs"
	69
	70	/*
	71	* IPB Bus clocking configuration.
	72	*/
6d0f6bcf JCPV	73	#define CONFIG_SYS_IPBSPEED_133 /* define for 133MHz speed */
6d0f6bcf JCPV	74	#if defined(CONFIG_SYS_IPBSPEED_133)
5fb2b234 HS	75	/*
	76	* PCI Bus clocking configuration
	77	*
	78	* Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
6d0f6bcf	79	* CONFIG_SYS_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
5fb2b234 HS	80	* been tested with a IPB Bus Clock of 66 MHz.
5fb2b234 HS	81	*/
6d0f6bcf	82	#define CONFIG_SYS_PCISPEED_66 /* define for 66MHz speed */
5fb2b234	83	#else
6d0f6bcf	84	#undef CONFIG_SYS_PCISPEED_66 /* for 33MHz speed */
5fb2b234 HS	85	#endif
	86
	87	/*
	88	* Memory map
	89	*/
6d0f6bcf	90	#define CONFIG_SYS_MBAR 0xF0000000 /* MBAR hast to be switched by other bootloader or debugger config */
fa05664c	91
6d0f6bcf JCPV	92	#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
6d0f6bcf JCPV	93	#define CONFIG_SYS_SDRAM_BASE 0x00000000
5fb2b234	94	/* Use SRAM until RAM will be available */
6d0f6bcf	95	#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
553f0982	96	#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
25ddd1fb	97	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf JCPV	98	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
6d0f6bcf JCPV	99
14d0a02a	100	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
6d0f6bcf JCPV	101	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
6d0f6bcf JCPV	102	# define CONFIG_SYS_RAMBOOT 1
5fb2b234 HS	103	#endif
5fb2b234 HS	104
6d0f6bcf JCPV	105	#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
	106	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
	107	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
5fb2b234 HS	108
	109	/*
	110	* Flash configuration
	111	*/
6d0f6bcf JCPV	112	#define CONFIG_SYS_FLASH_BASE 0xFF000000
6d0f6bcf JCPV	113	#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
00b1883a	114	#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
6d0f6bcf JCPV	115	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
	116	#define CONFIG_SYS_FLASH_EMPTY_INFO
	117	#define CONFIG_SYS_FLASH_SIZE 0x01000000 /* 16 MByte */
	118	#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
	119	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks (= chip selects) */
	120	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */
5fb2b234 HS	121
	122	/*
	123	* Chip selects configuration
	124	*/
	125	/* Boot Chipselect */
6d0f6bcf JCPV	126	#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
	127	#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
	128	#define CONFIG_SYS_BOOTCS_CFG 0x00047800
5fb2b234 HS	129
	130	/*
	131	* Environment settings
	132	*/
5a1aceb0	133	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586	134	#define CONFIG_ENV_OFFSET 0x40000
14d0a02a	135	#define CONFIG_ENV_ADDR (CONFIG_SYS_TEXT_BASE + CONFIG_ENV_OFFSET)
0e8d1586 JCPV	136	#define CONFIG_ENV_SECT_SIZE 0x20000
	137	#define CONFIG_ENV_SIZE 0x4000
	138	#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
14d0a02a	139	#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_TEXT_BASE + CONFIG_ENV_OFFSET_REDUND)
0e8d1586	140	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
5fb2b234 HS	141	#define CONFIG_ENV_OVERWRITE 1
	142
	143	/*
	144	* Ethernet configuration
	145	*/
	146	#define CONFIG_MPC5xxx_FEC 1
86321fc1	147	#define CONFIG_MPC5xxx_FEC_MII100
5fb2b234 HS	148	#define CONFIG_PHY_ADDR 0x01
	149	#define CONFIG_MII 1
	150
	151	/*
	152	* GPIO configuration
	153	*/
6d0f6bcf	154	#define CONFIG_SYS_GPS_PORT_CONFIG 0x00058044 /* PSC1=UART, PSC2=UART ; Ether=100MBit with MD
5fb2b234 HS	155	no PCI */
	156
	157	/*
	158	* Miscellaneous configurable options
	159	*/
6d0f6bcf	160	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	161	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
	162	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	163	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	164	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
5fb2b234	165
6d0f6bcf JCPV	166	#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
6d0f6bcf JCPV	167	#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
5fb2b234	168
6d0f6bcf	169	#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */
5fb2b234	170
5fb2b234 HS	171	#define CONFIG_CMDLINE_EDITING 1
	172
	173	/*
	174	* Various low-level settings
	175	*/
6d0f6bcf JCPV	176	#define CONFIG_SYS_HID0_INIT HID0_ICE \| HID0_ICFI
6d0f6bcf JCPV	177	#define CONFIG_SYS_HID0_FINAL HID0_ICE
5fb2b234	178
6d0f6bcf JCPV	179	#define CONFIG_SYS_CS_BURST 0x00000000
	180	#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
	181	#define CONFIG_SYS_RESET_ADDRESS 0xff000000
5fb2b234	182
5fb2b234 HS	183	#define OF_CPU "PowerPC,5200@0"
	184	#define OF_TBCLK (bd->bi_busfreq / 4)
	185	#define OF_SOC "soc5200@f0000000"
	186	#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
	187
	188	#endif /* __CONFIG_H */