[people/ms/u-boot.git] / include / configs / mx31ads.h

/*
 * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
 *
 * Configuration settings for the MX31ADS Freescale board.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#include <asm/arch/imx-regs.h>

 /* High Level Configuration Options */
#define CONFIG_ARM1136		1		/* This is an arm1136 CPU core */
#define CONFIG_MX31		1		/* in a mx31 */
#define CONFIG_MX31_HCLK_FREQ	26000000	/* RedBoot says 26MHz */
#define CONFIG_MX31_CLK32	32768

#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO

#define CONFIG_SYS_TEXT_BASE		0xA0000000

/*
 * Disabled for now due to build problems under Debian and a significant increase
 * in the final file size: 144260 vs. 109536 Bytes.
 */
#if 0
#define CONFIG_OF_LIBFDT		1
#define CONFIG_FIT			1
#define CONFIG_FIT_VERBOSE		1
#endif

#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS	1
#define CONFIG_INITRD_TAG		1

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128 * 1024)

/*
 * Hardware drivers
 */

#define CONFIG_MXC_UART	1
#define CONFIG_SYS_MX31_UART1		1

#define CONFIG_HARD_SPI		1
#define CONFIG_MXC_SPI		1
#define CONFIG_DEFAULT_SPI_BUS	1
#define CONFIG_DEFAULT_SPI_MODE	(SPI_MODE_0 | SPI_CS_HIGH)

#define CONFIG_FSL_PMIC
#define CONFIG_FSL_PMIC_BUS	1
#define CONFIG_FSL_PMIC_CS	0
#define CONFIG_FSL_PMIC_CLK	1000000
#define CONFIG_FSL_PMIC_MODE	(SPI_MODE_0 | SPI_CS_HIGH)
#define CONFIG_RTC_MC13783	1

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CONS_INDEX	1
#define CONFIG_BAUDRATE		115200
#define CONFIG_SYS_BAUDRATE_TABLE	{9600, 19200, 38400, 57600, 115200}

/***********************************************************
 * Command definition
 ***********************************************************/

#include <config_cmd_default.h>

#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_SPI
#define CONFIG_CMD_DATE

#define CONFIG_BOOTDELAY	3

#define CONFIG_LOADADDR		0x80800000	/* loadaddr env var */

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"uboot_addr=0xa0000000\0"					\
	"uboot=mx31ads/u-boot.bin\0"					\
	"kernel=mx31ads/uImage\0"					\
	"nfsroot=/opt/eldk/arm\0"					\
	"bootargs_base=setenv bootargs console=ttymxc0,115200\0"	\
	"bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "	\
		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"	\
	"bootcmd=run bootcmd_net\0"					\
	"bootcmd_net=run bootargs_base bootargs_nfs; "			\
		"tftpboot ${loadaddr} ${kernel}; bootm\0"		\
	"prg_uboot=tftpboot ${loadaddr} ${uboot}; "			\
		"protect off ${uboot_addr} 0xa003ffff; "		\
		"erase ${uboot_addr} 0xa003ffff; "			\
		"cp.b ${loadaddr} ${uboot_addr} ${filesize}; "		\
		"setenv filesize; saveenv\0"

#define CONFIG_NET_MULTI
#define CONFIG_CS8900
#define CONFIG_CS8900_BASE	0xb4020300
#define CONFIG_CS8900_BUS16		1	/* follow the Linux driver */

/*
 * The MX31ADS board seems to have a hardware "peculiarity" confirmed under
 * U-Boot, RedBoot and Linux: the ethernet Rx signal is reaching the CS8900A
 * controller inverted. The controller is capable of detecting and correcting
 * this, but it needs 4 network packets for that. Which means, at startup, you
 * will not receive answers to the first 4 packest, unless there have been some
 * broadcasts on the network, or your board is on a hub. Reducing the ARP
 * timeout from default 5 seconds to 200ms we speed up the initial TFTP
 * transfer, should the user wish one, significantly.
 */
#define CONFIG_ARP_TIMEOUT	200UL

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_SYS_PROMPT		"=> "
#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */

#define CONFIG_SYS_MEMTEST_START	0		/* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0x10000

#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR

#define CONFIG_SYS_HZ			1000

#define CONFIG_CMDLINE_EDITING	1

/*-----------------------------------------------------------------------
 * Stack sizes
 *
 * The stack sizes are set up in start.S using the settings below
 */
#define CONFIG_STACKSIZE	(128 * 1024)	/* regular stack */

/*-----------------------------------------------------------------------
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	1
#define PHYS_SDRAM_1		CSD0_BASE
#define PHYS_SDRAM_1_SIZE	(128 * 1024 * 1024)
#define CONFIG_BOARD_EARLY_INIT_F

#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
						GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_INIT_RAM_ADDR + \
						CONFIG_SYS_GBL_DATA_OFFSET)

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */
#define CONFIG_SYS_FLASH_BASE		CS0_BASE
#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT	262		/* max number of sectors on one chip */
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE	/* Monitor at beginning of flash */
#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256KiB */

#define	CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_SECT_SIZE	(128 * 1024)
#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)

/* Address and size of Redundant Environment Sector	*/
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE


/*-----------------------------------------------------------------------
 * CFI FLASH driver setup
 */
#define CONFIG_SYS_FLASH_CFI			1 /* Flash memory is CFI compliant */
#define CONFIG_FLASH_CFI_DRIVER		1 /* Use drivers/cfi_flash.c */
#define CONFIG_FLASH_SPANSION_S29WS_N	1 /* A non-standard buffered write algorithm */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1 /* Use buffered writes (~10x faster) */
#define CONFIG_SYS_FLASH_PROTECTION		1 /* Use hardware sector protection */

/*
 * JFFS2 partitions
 */
#undef CONFIG_CMD_MTDPARTS
#define CONFIG_JFFS2_DEV	"nor0"

#endif /* __CONFIG_H */
Commit	Line	Data
b5dc9b30 GL	1	/*
	2	* Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
	3	*
	4	* Configuration settings for the MX31ADS Freescale board.
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License as
	8	* published by the Free Software Foundation; either version 2 of
	9	* the License, or (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	19	* MA 02111-1307 USA
	20	*/
	21
	22	#ifndef __CONFIG_H
	23	#define __CONFIG_H
	24
86271115	25	#include <asm/arch/imx-regs.h>
b5dc9b30 GL	26
	27	/* High Level Configuration Options */
	28	#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
	29	#define CONFIG_MX31 1 /* in a mx31 */
	30	#define CONFIG_MX31_HCLK_FREQ 26000000 /* RedBoot says 26MHz */
2ab02fd4	31	#define CONFIG_MX31_CLK32 32768
b5dc9b30 GL	32
	33	#define CONFIG_DISPLAY_CPUINFO
	34	#define CONFIG_DISPLAY_BOARDINFO
	35
4ac2e2d6 FE	36	#define CONFIG_SYS_TEXT_BASE 0xA0000000
4ac2e2d6 FE	37
b5dc9b30 GL	38	/*
	39	* Disabled for now due to build problems under Debian and a significant increase
	40	* in the final file size: 144260 vs. 109536 Bytes.
	41	*/
	42	#if 0
	43	#define CONFIG_OF_LIBFDT 1
	44	#define CONFIG_FIT 1
	45	#define CONFIG_FIT_VERBOSE 1
	46	#endif
	47
	48	#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
	49	#define CONFIG_SETUP_MEMORY_TAGS 1
	50	#define CONFIG_INITRD_TAG 1
	51
	52	/*
	53	* Size of malloc() pool
	54	*/
6d0f6bcf	55	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
b5dc9b30 GL	56
	57	/*
	58	* Hardware drivers
	59	*/
	60
47d19da4	61	#define CONFIG_MXC_UART 1
6d0f6bcf	62	#define CONFIG_SYS_MX31_UART1 1
b5dc9b30	63
0a0b606f GL	64	#define CONFIG_HARD_SPI 1
0a0b606f GL	65	#define CONFIG_MXC_SPI 1
d255bb0e	66	#define CONFIG_DEFAULT_SPI_BUS 1
9f481e95	67	#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 \| SPI_CS_HIGH)
0a0b606f	68
dfe5e14f SB	69	#define CONFIG_FSL_PMIC
	70	#define CONFIG_FSL_PMIC_BUS 1
	71	#define CONFIG_FSL_PMIC_CS 0
	72	#define CONFIG_FSL_PMIC_CLK 1000000
9f481e95	73	#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 \| SPI_CS_HIGH)
0a0b606f GL	74	#define CONFIG_RTC_MC13783 1
0a0b606f GL	75
b5dc9b30 GL	76	/* allow to overwrite serial and ethaddr */
	77	#define CONFIG_ENV_OVERWRITE
	78	#define CONFIG_CONS_INDEX 1
	79	#define CONFIG_BAUDRATE 115200
6d0f6bcf	80	#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
b5dc9b30 GL	81
	82	/***********************************************************
	83	* Command definition
	84	***********************************************************/
	85
	86	#include <config_cmd_default.h>
	87
b5dc9b30	88	#define CONFIG_CMD_PING
7602ed50	89	#define CONFIG_CMD_DHCP
0a0b606f GL	90	#define CONFIG_CMD_SPI
0a0b606f GL	91	#define CONFIG_CMD_DATE
b5dc9b30 GL	92
	93	#define CONFIG_BOOTDELAY 3
	94
7602ed50	95	#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
0a0b606f GL	96
	97	#define CONFIG_EXTRA_ENV_SETTINGS \
	98	"netdev=eth0\0" \
	99	"uboot_addr=0xa0000000\0" \
	100	"uboot=mx31ads/u-boot.bin\0" \
	101	"kernel=mx31ads/uImage\0" \
	102	"nfsroot=/opt/eldk/arm\0" \
	103	"bootargs_base=setenv bootargs console=ttymxc0,115200\0" \
	104	"bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs " \
	105	"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
	106	"bootcmd=run bootcmd_net\0" \
	107	"bootcmd_net=run bootargs_base bootargs_nfs; " \
	108	"tftpboot ${loadaddr} ${kernel}; bootm\0" \
	109	"prg_uboot=tftpboot ${loadaddr} ${uboot}; " \
	110	"protect off ${uboot_addr} 0xa003ffff; " \
	111	"erase ${uboot_addr} 0xa003ffff; " \
	112	"cp.b ${loadaddr} ${uboot_addr} ${filesize}; " \
	113	"setenv filesize; saveenv\0"
b5dc9b30	114
b1c0eaac BW	115	#define CONFIG_NET_MULTI
	116	#define CONFIG_CS8900
	117	#define CONFIG_CS8900_BASE 0xb4020300
	118	#define CONFIG_CS8900_BUS16 1 /* follow the Linux driver */
d23ff682 GL	119
	120	/*
	121	* The MX31ADS board seems to have a hardware "peculiarity" confirmed under
	122	* U-Boot, RedBoot and Linux: the ethernet Rx signal is reaching the CS8900A
	123	* controller inverted. The controller is capable of detecting and correcting
	124	* this, but it needs 4 network packets for that. Which means, at startup, you
	125	* will not receive answers to the first 4 packest, unless there have been some
	126	* broadcasts on the network, or your board is on a hub. Reducing the ARP
	127	* timeout from default 5 seconds to 200ms we speed up the initial TFTP
	128	* transfer, should the user wish one, significantly.
	129	*/
	130	#define CONFIG_ARP_TIMEOUT 200UL
b5dc9b30 GL	131
	132	/*
	133	* Miscellaneous configurable options
	134	*/
6d0f6bcf JCPV	135	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	136	#define CONFIG_SYS_PROMPT "=> "
	137	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
b5dc9b30	138	/* Print Buffer Size */
6d0f6bcf JCPV	139	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
	140	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	141	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
b5dc9b30	142
6d0f6bcf JCPV	143	#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
6d0f6bcf JCPV	144	#define CONFIG_SYS_MEMTEST_END 0x10000
b5dc9b30	145
6d0f6bcf	146	#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
b5dc9b30	147
6d0f6bcf	148	#define CONFIG_SYS_HZ 1000
b5dc9b30 GL	149
	150	#define CONFIG_CMDLINE_EDITING 1
	151
	152	/*-----------------------------------------------------------------------
	153	* Stack sizes
	154	*
	155	* The stack sizes are set up in start.S using the settings below
	156	*/
	157	#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
	158
	159	/*-----------------------------------------------------------------------
	160	* Physical Memory Map
	161	*/
	162	#define CONFIG_NR_DRAM_BANKS 1
	163	#define PHYS_SDRAM_1 CSD0_BASE
	164	#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
4ac2e2d6 FE	165	#define CONFIG_BOARD_EARLY_INIT_F
	166
	167	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
	168	#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
	169	#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
	170	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
	171	GENERATED_GBL_DATA_SIZE)
	172	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
	173	CONFIG_SYS_GBL_DATA_OFFSET)
b5dc9b30 GL	174
	175	/*-----------------------------------------------------------------------
	176	* FLASH and environment organization
	177	*/
6d0f6bcf JCPV	178	#define CONFIG_SYS_FLASH_BASE CS0_BASE
	179	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	180	#define CONFIG_SYS_MAX_FLASH_SECT 262 /* max number of sectors on one chip */
	181	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */
	182	#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256KiB */
b5dc9b30	183
5a1aceb0	184	#define CONFIG_ENV_IS_IN_FLASH 1
ba8dcca7	185	#define CONFIG_ENV_SECT_SIZE (128 * 1024)
0e8d1586	186	#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
ba8dcca7	187	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
d23ff682 GL	188
d23ff682 GL	189	/* Address and size of Redundant Environment Sector */
ba8dcca7	190	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
0e8d1586	191	#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
d23ff682	192
b5dc9b30 GL	193
	194	/*-----------------------------------------------------------------------
	195	* CFI FLASH driver setup
	196	*/
6d0f6bcf	197	#define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */
00b1883a	198	#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
d23ff682	199	#define CONFIG_FLASH_SPANSION_S29WS_N 1 /* A non-standard buffered write algorithm */
6d0f6bcf JCPV	200	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
6d0f6bcf JCPV	201	#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */
b5dc9b30 GL	202
	203	/*
	204	* JFFS2 partitions
	205	*/
68d7d651	206	#undef CONFIG_CMD_MTDPARTS
b5dc9b30 GL	207	#define CONFIG_JFFS2_DEV "nor0"
	208
	209	#endif /* __CONFIG_H */