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Convert CONFIG_BOOTP_BOOTPATH et al to Kconfig
[people/ms/u-boot.git] / include / configs / mx31ads.h
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1/*
2 * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
3 *
4 * Configuration settings for the MX31ADS Freescale board.
5 *
3765b3e7 6 * SPDX-License-Identifier: GPL-2.0+
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7 */
8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
86271115 12#include <asm/arch/imx-regs.h>
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13
14 /* High Level Configuration Options */
3fd968e9 15#define CONFIG_MX31 1 /* This is a mx31 */
b5dc9b30 16
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17#define CONFIG_MACH_TYPE MACH_TYPE_MX31ADS
18
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19#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
20#define CONFIG_SETUP_MEMORY_TAGS 1
21#define CONFIG_INITRD_TAG 1
22
23/*
24 * Size of malloc() pool
25 */
6d0f6bcf 26#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
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27
28/*
29 * Hardware drivers
30 */
31
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32#define CONFIG_MXC_UART
33#define CONFIG_MXC_UART_BASE UART1_BASE
b5dc9b30 34
0a0b606f 35#define CONFIG_HARD_SPI 1
d255bb0e 36#define CONFIG_DEFAULT_SPI_BUS 1
9f481e95 37#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
0a0b606f 38
d7d6780f 39/* PMIC Controller */
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40#define CONFIG_POWER
41#define CONFIG_POWER_SPI
42#define CONFIG_POWER_FSL
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43#define CONFIG_FSL_PMIC_BUS 1
44#define CONFIG_FSL_PMIC_CS 0
45#define CONFIG_FSL_PMIC_CLK 1000000
9f481e95 46#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
d7d6780f 47#define CONFIG_FSL_PMIC_BITLEN 32
4e8b7544 48#define CONFIG_RTC_MC13XXX
0a0b606f 49
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50/* allow to overwrite serial and ethaddr */
51#define CONFIG_ENV_OVERWRITE
52#define CONFIG_CONS_INDEX 1
b5dc9b30 53
7602ed50 54#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
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55
56#define CONFIG_EXTRA_ENV_SETTINGS \
57 "netdev=eth0\0" \
58 "uboot_addr=0xa0000000\0" \
59 "uboot=mx31ads/u-boot.bin\0" \
60 "kernel=mx31ads/uImage\0" \
61 "nfsroot=/opt/eldk/arm\0" \
62 "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \
63 "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs " \
64 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
65 "bootcmd=run bootcmd_net\0" \
66 "bootcmd_net=run bootargs_base bootargs_nfs; " \
67 "tftpboot ${loadaddr} ${kernel}; bootm\0" \
68 "prg_uboot=tftpboot ${loadaddr} ${uboot}; " \
69 "protect off ${uboot_addr} 0xa003ffff; " \
70 "erase ${uboot_addr} 0xa003ffff; " \
71 "cp.b ${loadaddr} ${uboot_addr} ${filesize}; " \
72 "setenv filesize; saveenv\0"
b5dc9b30 73
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74#define CONFIG_CS8900
75#define CONFIG_CS8900_BASE 0xb4020300
76#define CONFIG_CS8900_BUS16 1 /* follow the Linux driver */
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77
78/*
79 * The MX31ADS board seems to have a hardware "peculiarity" confirmed under
80 * U-Boot, RedBoot and Linux: the ethernet Rx signal is reaching the CS8900A
81 * controller inverted. The controller is capable of detecting and correcting
82 * this, but it needs 4 network packets for that. Which means, at startup, you
83 * will not receive answers to the first 4 packest, unless there have been some
84 * broadcasts on the network, or your board is on a hub. Reducing the ARP
85 * timeout from default 5 seconds to 200ms we speed up the initial TFTP
86 * transfer, should the user wish one, significantly.
87 */
88#define CONFIG_ARP_TIMEOUT 200UL
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89
90/*
91 * Miscellaneous configurable options
92 */
b5dc9b30 93
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94#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
95#define CONFIG_SYS_MEMTEST_END 0x10000
b5dc9b30 96
6d0f6bcf 97#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
b5dc9b30 98
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99/*-----------------------------------------------------------------------
100 * Physical Memory Map
101 */
102#define CONFIG_NR_DRAM_BANKS 1
103#define PHYS_SDRAM_1 CSD0_BASE
104#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
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105
106#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
107#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
108#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
109#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
110 GENERATED_GBL_DATA_SIZE)
111#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
112 CONFIG_SYS_GBL_DATA_OFFSET)
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113
114/*-----------------------------------------------------------------------
115 * FLASH and environment organization
116 */
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117#define CONFIG_SYS_FLASH_BASE CS0_BASE
118#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
119#define CONFIG_SYS_MAX_FLASH_SECT 262 /* max number of sectors on one chip */
120#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */
121#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256KiB */
b5dc9b30 122
ba8dcca7 123#define CONFIG_ENV_SECT_SIZE (128 * 1024)
0e8d1586 124#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
ba8dcca7 125#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
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126
127/* Address and size of Redundant Environment Sector */
ba8dcca7 128#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
0e8d1586 129#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
d23ff682 130
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131/*-----------------------------------------------------------------------
132 * CFI FLASH driver setup
133 */
6d0f6bcf 134#define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */
00b1883a 135#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
d23ff682 136#define CONFIG_FLASH_SPANSION_S29WS_N 1 /* A non-standard buffered write algorithm */
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137#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
138#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */
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139
140/*
141 * JFFS2 partitions
142 */
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143#define CONFIG_JFFS2_DEV "nor0"
144
145#endif /* __CONFIG_H */